Large-area high-count-rate superconducting nanowire single-photon detector and implementation method

Abstract

The application discloses a kind of big photosensitive surface high counting rate superconducting nanowire single-photon detector and implementation method, including low dynamic inductance superconducting nanowire and discharge acceleration bias readout circuit.Low dynamic inductance superconducting nanowire adopts central symmetry distribution and parallel nanowire structure;Discharge acceleration bias readout circuit is a three-terminal circuit, including DC end, DC&RF end and readout end.The low dynamic inductance superconducting nanowire design method disclosed in the application can significantly expand the photosensitive surface of the detector while maintaining low dynamic inductance, thereby ensuring high counting rate of the detector, and the discharge acceleration bias readout circuit can effectively alleviate the latch condition of the detector under high counting rate conditions, therefore, the big photosensitive surface high counting rate superconducting nanowire single-photon detector disclosed in the application has important significance for laser radar applications requiring large photosensitive surface and high counting rate.

Description

Technical Field

[0001] This invention relates to the fields of lidar and superconducting single-photon detection technology, specifically to a high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface and its implementation method. Background Technology

[0002] Superconducting nanowire single-photon detectors, as one of the highest-performing photon detectors, have achieved significant breakthroughs in various performance indicators, including a broad response spectrum (covering the mid-infrared to X-ray range), extremely high system detection efficiency (over 98%), and extremely low dark count (less than 10^6). -5 High performance with extremely low timing jitter (below 3 ps) and a maximum count rate exceeding Gcps. In recent years, with the further development of applications such as deep space laser communication and long-distance laser ranging, more stringent requirements have been placed on the high-speed performance of superconducting nanowire single-photon detectors. This is because the high-speed performance of superconducting nanowire single-photon detectors directly limits the maximum communication rate of laser communication and also directly determines the dynamic range of laser detection.

[0003] Maximum count rate is one of the most important performance indicators of single-photon detectors, typically defined as the count rate at which the detection efficiency decreases by 3 dB. The dynamic inductance of superconducting nanowires limits the recovery time of superconducting nanowire single-photon detectors, thus limiting the maximum count rate. Simultaneously, to match large-aperture receivers, photon detectors require a large detection area. However, with increasing area, the electrical recovery time increases significantly. Currently, some works have increased the maximum count rate beyond Gcps using multiple independent nanowires, but these consume more circuit resources and limit scalability. Other works have introduced micron-wires to expand the detection area of ​​superconducting single-photon detectors, but have not yet achieved a breakthrough in high count rates. Still other works have effectively improved the maximum count rate without increasing readout complexity by connecting multiple nanowires in series and each with its own parallel resistor; however, the significant increase in inductance cannot be extended to large areas and further limits the maximum count rate and timing accuracy. Therefore, superconducting nanowire single-photon detectors with both large area and high maximum count rate remain an important research topic and are currently under continuous investigation. Summary of the Invention

[0004] Purpose of the invention: To address the current limitations of superconducting nanowire single-photon detectors in simultaneously meeting the requirements of a large photosensitive surface and a high count rate, this invention proposes a superconducting nanowire single-photon detector with a large photosensitive surface and a high count rate, as well as its implementation method.

[0005] Technical solution: A high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface, comprising:

[0006] Low dynamic inductance superconducting nanowires for photon detection;

[0007] Discharge-accelerated bias readout circuit is used to read out the number of photons detected by low dynamic inductance superconducting nanowires;

[0008] The low dynamic inductance superconducting nanowire is composed of several channels arranged in a centrally symmetrical manner, and each channel is composed of multiple nanowires connected in parallel.

[0009] The discharge acceleration bias readout circuit includes: an inductor L B Series resistor R0, inductor L0, AC coupling capacitor C B and low-noise amplifiers;

[0010] The inductor L B The two ends of the series resistor R0 are respectively used as the DC terminal and the DC & RF terminal. One end of the series resistor R0 is connected to the DC & RF terminal, and the other end of the series resistor R0 is connected to the AC coupling capacitor C. B The two are connected in series, with an inductor L0 connected to ground and an AC coupling capacitor C. B The other end is connected to a low-noise amplifier, from which the number of photons detected by the low-dynamic-inductance superconducting nanowire is read out.

[0011] The DC & RF terminals are connected to the low dynamic inductance superconducting nanowire and are used to provide bias current to the low dynamic inductance superconducting nanowire and to obtain the number of photons detected by the low dynamic inductance superconducting nanowire.

[0012] The DC terminal is used to input current to the discharge acceleration bias readout circuit.

[0013] Furthermore, each of the nanowires is connected in series with an on-grid resistor R to ground.

[0014] Furthermore, multiple nanowires in the same channel are arranged in a concentric circle pattern, with each nanowire being a concentric ring structure.

[0015] Furthermore, each nanowire receives the same number of photons.

[0016] Furthermore, each nanowire has the same area.

[0017] Furthermore, each nanowire is the same length.

[0018] Furthermore, each on-chip resistor R is a dumbbell-shaped structure, and all on-chip resistors R are connected as a whole.

[0019] Furthermore, the inductor L BThe value of the resistor R0 is between 560μH and 1.2mH, the value of the series resistor R0 is between 0 and 50Ω, the value of the inductor L0 is greater than or equal to the dynamic inductance of the nanowire, and the AC coupling capacitor C... B The value ranges from 80 nF to 240 nF.

[0020] This invention also discloses a method for implementing a large photosensitive surface high count rate superconducting nanowire single-photon detector, comprising:

[0021] Fabrication of low-dynamic-inductance superconducting nanowires;

[0022] Construct a discharge acceleration bias readout circuit;

[0023] The low dynamic inductance superconducting nanowire is connected to the discharge acceleration bias readout circuit, and the number of photons detected by the low dynamic inductance superconducting nanowire is read out by the discharge acceleration bias readout circuit.

[0024] The low dynamic inductance superconducting nanowires were fabricated according to the following steps:

[0025] Step 1: Deposit a niobium nitride thin film on the silicon nitride layer;

[0026] Step 2: Obtain nanowire patterns by electron beam exposure, and then obtain nanowires by reactive ion etching after development;

[0027] Step 3: Obtain the on-chip resistor pattern using electron beam exposure;

[0028] Step 4: Grow a Ti thin film using magnetron sputtering;

[0029] Step 5: Strip to obtain the on-chip resistor;

[0030] The nanowire pattern is composed of several channels arranged in a centrally symmetrical manner, and each channel is composed of multiple nanowires connected in parallel. The multiple nanowires in the same channel are arranged in a concentric circle, and each nanowire is a concentric ring structure.

[0031] The resistance pattern is such that an on-resistor is connected in series with ground on each of the nanowires;

[0032] The discharge acceleration bias readout circuit includes: inductor L B Series resistor R0, inductor L0, AC coupling capacitor C B and low-noise amplifier; the inductor L B The two ends of the series resistor R0 are respectively used as the DC terminal and the DC & RF terminal. One end of the series resistor R0 is connected to the DC & RF terminal, and the other end of the series resistor R0 is connected to the AC coupling capacitor C. B The two are connected in series, with an inductor L0 connected to ground and an AC coupling capacitor C. BThe other end is connected to a low-noise amplifier, from which the number of photons detected by the low dynamic inductance superconducting nanowire is read out; the DC & RF terminal is connected to the low dynamic inductance superconducting nanowire and is used to provide bias current to the low dynamic inductance superconducting nanowire and to obtain the number of photons detected by the low dynamic inductance superconducting nanowire; the DC terminal is used to input current to the discharge acceleration bias readout circuit.

[0033] Furthermore, each on-chip resistor has a dumbbell-shaped structure, and all on-chip resistors are connected as a whole.

[0034] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0035] (1) The present invention proposes a superconducting nanowire single-photon detector with a large photosensitive surface and a high counting rate, which can ensure a high counting rate while significantly expanding the photosensitive surface.

[0036] (2) The present invention proposes a high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface. By using the low dynamic inductance superconducting nanowire design method, it can be further extended to a larger photosensitive surface without significantly increasing the readout complexity.

[0037] (3) The discharge acceleration bias readout circuit proposed in this invention can also be applied to the bias readout of other superconducting nanowire single-photon detectors;

[0038] (4) The superconducting nanowire single-photon detector with large photosensitive surface and high count rate proposed in this invention has the advantages of simple structure, easy preparation, easy operation, no need for special personnel training, low cost and high working efficiency. Attached Figure Description

[0039] Figure 1 A schematic diagram of the low dynamic inductance superconducting nanowire and an SEM image of channel 4;

[0040] Figure 2 IV curves for superconducting nanowire single-photon detectors;

[0041] Figure 3 This is a schematic diagram of a traditional bias readout circuit;

[0042] Figure 4 Circuit diagram for accelerated discharge bias readout;

[0043] Figure 5 A comparison of simulation results for the traditional bias readout circuit and the discharge-accelerated bias readout circuit;

[0044] Figure 6 A comparison chart of the measured count rate results for the traditional bias readout circuit and the discharge-accelerated bias readout circuit;

[0045] Figure 7 This is a comparison chart of the measured response signals and time jitter of a traditional bias readout circuit and a discharge-accelerated bias readout circuit. Detailed Implementation

[0046] The technical solution of the present invention will now be further described in conjunction with the accompanying drawings and embodiments.

[0047] Example:

[0048] This embodiment discloses a high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface, which includes a low-dynamic-inductance superconducting nanowire and a discharge-accelerated bias readout circuit.

[0049] In this embodiment, the low dynamic inductance superconducting nanowires adopt a centrosymmetric distribution and parallel nanowire structure, which can reduce the dynamic inductance of the superconducting nanowires; the specific structure is as follows:

[0050] The low dynamic inductance superconducting nanowires are distributed in a centrosymmetric structure with multiple channels. In this embodiment, they are divided into four channels, each consisting of four nanowires connected in parallel. Assume the dynamic inductance of the nanowires with a total length of l is L. K Given the same length, the equivalent dynamic inductance of the device designed above is L. K / 16, readout channel number is 4. To mitigate electrical crosstalk between the nanowires, each of the four parallel nanowires is connected in series with an on-chip resistor R to ground. Due to the time constant τ = L K / R, therefore, the series resistor can also compress the device response time, thereby improving the maximum count rate to some extent. Considering the proximity effect of electron beam exposure, this embodiment designs the nanowires in a concentric circle arrangement to ensure the uniformity of a single nanowire as much as possible; at the same time, in order to make the number of photons received by each nanowire basically uniform, each nanowire is designed as a concentric ring structure with a basically the same area, that is, the radius of the concentric circle satisfies r1:r2:r3:r4=1: The relationship of 2 ensures that each nanowire has a substantially uniform length, thereby guaranteeing that the delay of the response pulse for each nanowire is substantially the same. The on-chip resistor R connected in series with each nanowire is obtained by peeling off a titanium thin film grown by magnetron sputtering. Since the peeling process can easily cause problems such as uneven edges or curling, which can cause the sample characteristics to deviate from the expected design, this embodiment designs the on-chip resistor R in a dumbbell shape and connects all the on-chip resistors R into a whole to make the edges of the on-chip resistor R as regular and flat as possible after peeling.

[0051] The low dynamic inductance superconducting nanowires proposed in this embodiment can be prepared according to the following steps:

[0052] Step 1: Deposit a niobium nitride film approximately 8 nm thick on a 135 nm thick silicon nitride layer;

[0053] Step 2: Obtain nanowire patterns through electron beam exposure, and after development, obtain meandering nanowires through reactive ion etching. The actual linewidth of the nanowires is about 80nm, and the period is 200nm.

[0054] Step 3: After obtaining the nanowires, the series resistance pattern is then obtained by electron beam exposure;

[0055] Step 4: Grow a Ti film approximately 50 nm thick using magnetron sputtering;

[0056] Step 5: Stripping to obtain titanium resistors. Characterization showed that the titanium resistors had a resistance of approximately 50 ohms at a low temperature of 4.2K.

[0057] The fabricated low-dynamic-inductance superconducting nanowires were optically encapsulated and then cooled in a GM refrigerator until the temperature dropped below 2.3 K, at which point they were characterized. Figure 2 The figure shows the IV curve characterization results of the above device. The superconducting switching current of the four channels is relatively uniform, all around 45 μA, and the hysteresis current is around 6 μA. The supercurrent-hysteresis ratio is ~8. The test results of the superconducting switching current and hysteresis current are the sum of the superconducting switching current and hysteresis current of the four parallel nanowires.

[0058] Figure 3 The diagram illustrates a conventional bias readout circuit. This circuit suffers from capacitor charging and discharging effects during readout, which significantly limits the maximum count rate of the superconducting nanowire single-photon detector. The capacitors involved in this charging and discharging effect during readout include the AC coupling capacitor C. B and the input capacitance C of the low-noise amplifier P After the detector detects a photon and loses quench, an AC pulse is transmitted through the capacitor to the load resistor R. L The above process charges the capacitor (gray arrow), causing it to accumulate charge. After the detector loses its quench, it gradually recovers, and simultaneously, the charged capacitor begins to discharge (black arrow). The current generated during this discharge causes the detector's actual bias current to exceed the set value. According to Kirchhoff's laws for circuits, this can be described by Equation 1. Figure 3 Voltage changes in traditional bias readout circuit models

[0059]

[0060] In the formula, C bt This represents the total capacitance in the circuit, including the AC coupling capacitance C of the Bias-Tee. B and the input capacitance C of the low-noise amplifier P U(t) represents the voltage across the capacitor, I o(t) represents the response signal output by the superconducting nanowire single-photon detector after photon quench.

[0061] To mitigate the impact of AC coupling capacitor charging and discharging effects on the maximum count rate of superconducting nanowire single-photon detectors, some studies have reported corresponding improvement methods. For example, the discharge current of the capacitor can be discharged through a "capacitor-ground" circuit, and an attenuator can be added between the superconducting nanowire single-photon detector and the bias readout circuit for isolation. Both of these methods can effectively alleviate the capacitor charging and discharging effect, but they also have a common drawback: they will significantly reduce the signal amplitude, which is extremely detrimental to the high time accuracy characteristics of superconducting nanowire single-photon detectors.

[0062] To alleviate the limitation of traditional bias readout circuits on the maximum count rate of superconducting nanowire single-photon detectors, this embodiment proposes a discharge-accelerated bias readout circuit, such as... Figure 4 As shown. The discharge acceleration bias readout circuit of this embodiment is a three-terminal circuit, including a DC terminal, a DC & RF terminal, and a readout terminal. This discharge acceleration bias readout circuit is based on the traditional bias readout circuit, with the inductor L... B and AC coupling capacitor C B A series resistor R0 was added between them, and then the AC coupling capacitor C was connected between the series resistor R0 and the AC coupling capacitor C. B Insert an inductor L0 between the two and ground it, i.e. Figure 4 As shown in medium gray shading.

[0063] Now combined Figure 4 The structure of the discharge acceleration bias readout circuit in this embodiment will be further explained. It mainly consists of an inductor L. B Series resistor R0, inductor L0, AC coupling capacitor C B Composed of a low-noise amplifier (LNA), with inductor L B The two ends are the DC terminal and the DC & RF terminal, respectively. One end of the series resistor R0 is the DC & RF terminal, and the other end of the series resistor R0 is connected to the AC coupling capacitor C. B The two are connected in series, with an inductor L0 connected to ground and an AC coupling capacitor C. B The other end is connected to a low-noise amplifier (LNA). The bias current input to the low dynamic inductance superconducting nanowire is fed into the DC input inductor LNA. B The signal is then input from the DC & RF terminal to the low dynamic inductance superconducting nanowire. When the low dynamic inductance superconducting nanowire detects a photon, it loses its quench, and the signal is input from the DC & RF terminal, then passes through a series resistor R0 and an AC coupling capacitor C. B The current flows to the low-noise amplifier (LNA) and is read out from the LNA. In this embodiment, the LNA can be equivalent to the input capacitor C. P and resistance R L Series connection. In this embodiment, the inductor LB The value of the series resistance R0 is between 560μH and 1.2mH, the value of the parallel inductance L0 connected to ground is greater than or equal to the dynamic inductance value of the low dynamic inductance superconducting nanowire, and the AC coupling capacitor C is between 0 and 50Ω. B The value ranges from 80 nF to 240 nF.

[0064] During the detection process, the capacitor charging and discharging effect still exists. Unlike traditional bias readout circuits, the series resistor R0 accelerates capacitor discharge, and the parallel inductor L0 provides an additional discharge path, further accelerating capacitor discharge. Figure 4 As shown by the black lines, most of the discharge current flows out through the inductor L0, with only a small portion flowing to the low dynamic inductance superconducting nanowire. This effectively mitigates the impact of capacitor charging and discharging effects on the operation of the superconducting nanowire single-photon detector. The increased series resistance R0, on the one hand, hinders the capacitor from discharging into the low dynamic inductance superconducting nanowire; on the other hand, it increases the total resistance of the branch, thus compressing the detector's recovery time and thereby improving the detector's maximum count rate to some extent.

[0065] Similarly, according to Kirchhoff's current and voltage laws, equations (2) and (3) can be used to describe the following: Figure 4 The voltage and current of the improved circuit shown change over time:

[0066]

[0067]

[0068] In the formula, i L (t) represents the instantaneous current flowing through inductor L0, C bt This represents the total capacitance in the circuit, including the AC coupling capacitance C of the Bias-Tee. B and the input capacitance C of the low-noise amplifier P U(t) represents the voltage across the capacitor, I o (t) represents the AC signal output by the superconducting nanowire single-photon detector after photon quench.

[0069] Based on the circuit model, a Monte Carlo simulation was performed, assuming a saturation detection efficiency of 1. The simulated output waveform is as follows: Figure 5 As shown in (a), the gray waveform represents the output waveform of the simulated traditional readout circuit, and the black waveform represents the output waveform of the simulated improved readout circuit. Comparing the two, it can be seen that the improved circuit using inductor grounding does not significantly reduce the amplitude of the response signal, but rather causes a noticeable overshoot, which is also a manifestation of the significantly faster capacitor discharge. The count rate simulation results obtained using the two circuits are as follows: Figure 5As shown in (b), the circle represents the count rate obtained using the traditional bias readout circuit simulation. It is evident that the count rate curve rises in the latter half, and with the increase in the number of incident photons, the detector latches up earlier, resulting in a maximum count rate of only 80 Mcps. (Furthermore, as the incident light intensity increases, the probability of multiple photons arriving simultaneously gradually rises, leading to a continuous increase in the detection probability, which is no longer equal to the system detection efficiency, thus also causing the count rate to rise.) Conversely, using the discharge-accelerated bias readout circuit significantly improves the detector latch-up problem, and the count rate does not rise in the latter half. Instead, due to the increase in the number of incident photons and the decrease in detection efficiency, the count rate growth slows down, ultimately reaching a maximum count rate of 166 Mcps (e.g., ...). Figure 5 (as shown in triangle (b)).

[0070] In the actual experiment, we used a continuous laser with a center wavelength of 1064 nm as the light source, and a digitally adjustable attenuator with a working wavelength of 1064 nm to change the number of incident photons, to irradiate the superconducting nanowire single-photon detector to test the maximum count rate. The test results for channel 4 are as follows: Figure 6 As shown, Figure 6 In (a) of the diagram, the black circle represents the test results of the conventional bias readout circuit. It can be seen that as the number of incident photons increases, the superconducting nanowire single-photon detector latches up earlier, with a maximum count rate of only 18.4 Mcps. The gray hollow triangle represents the test results of the discharge-accelerated bias readout circuit. As the number of incident photons increases, the latch-up situation of the superconducting nanowire single-photon detector is significantly improved, with a count rate of 37.8 Mcps when the efficiency decreases by 3 dB, while the dynamic range increases by 21 dB. Figure 6 (b) shows the total count rate of the four channels after using the discharge-accelerated bias readout circuit. The total count rate is 147 Mcps when the efficiency decreases by 3 dB.

[0071] A ps pulsed laser with a center wavelength of 1064 nm was used as the light source, along with a high-speed oscilloscope with a sampling rate of 40 GHz, to measure the response pulse and timing jitter of the superconducting nanowire single-photon detector. Tests were conducted using both a conventional bias readout circuit and a discharge-accelerated bias readout circuit designed to improve latch-up in the superconducting nanowire single-photon detector at high count rates. The test results are as follows: Figure 7As shown, using a discharge-accelerated bias readout circuit to improve latch-up in a superconducting nanowire single-photon detector at high count rates, the signal-to-noise ratio (SNR) of the superconducting nanowire single-photon detector's response signal slightly decreases from the original 113 mV to the current 97.9 mV, while the corresponding timing jitter increases from the original 114 ps (FWHM) to 138.6 ps (FWHM). Therefore, this discharge-accelerated bias readout circuit significantly improves the latch-up situation of the superconducting nanowire single-photon detector at high count rates while maintaining the SNR of the response pulse, thereby ensuring the timing accuracy of the superconducting nanowire single-photon detector.

[0072] In summary, the high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area proposed in this embodiment can maintain a high count rate while significantly increasing the photosensitive surface area. Furthermore, the low dynamic inductance superconducting nanowire design method proposed in this embodiment can be further extended to even larger photosensitive surfaces without significantly increasing readout complexity. Meanwhile, the discharge-accelerated bias readout circuit proposed in this embodiment can also be applied to the bias readout of other superconducting nanowire single-photon detectors. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area proposed in this embodiment is of great significance for lidar applications requiring large photosensitive surfaces and high count rates.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely one implementation method of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface, characterized in that: include: Low dynamic inductance superconducting nanowires for photon detection; Discharge-accelerated bias readout circuit is used to read out the number of photons detected by low dynamic inductance superconducting nanowires; The low dynamic inductance superconducting nanowires are composed of several channels arranged in a centrally symmetrical manner, with each channel consisting of multiple nanowires connected in parallel. The multiple nanowires within the same channel are arranged in concentric circles, with each nanowire forming a concentric ring structure. Each nanowire is connected in series with an on-chip resistor. R Arrival; The discharge acceleration bias readout circuit includes: an inductor L B Series resistors R 0. Inductance L 0. AC coupling capacitor C B and low-noise amplifiers; The inductor L B The two ends are respectively used as the DC terminal and the DC & RF terminal, and the series resistor R One end of the series resistor is connected to the DC & RF terminals. R The other end of 0 is connected to the AC coupling capacitor. C B The two are connected in series with an inductor between them. L 0 to ground, AC coupling capacitor C B The other end is connected to a low-noise amplifier, from which the number of photons detected by the low-dynamic-inductance superconducting nanowire is read out. The DC & RF terminals are connected to the low dynamic inductance superconducting nanowire and are used to provide bias current to the low dynamic inductance superconducting nanowire and to obtain the number of photons detected by the low dynamic inductance superconducting nanowire. The DC terminal is used to input current to the discharge acceleration bias readout circuit.

2. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area according to claim 1, characterized in that: Each nanowire receives the same number of photons.

3. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area according to claim 1, characterized in that: Each nanowire has the same area.

4. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area according to claim 1, characterized in that: Each nanowire is the same length.

5. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area according to claim 1, characterized in that: Each on-chip resistor R All of them have a dumbbell-shaped structure, and all on-chip resistors R Connected into a whole.

6. The high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface area according to claim 1, characterized in that: The inductor L B The value of the series resistor is between 560 μH and 1.2 mH. R The value of 0 is between 0 and 50Ω, and the inductance... L The value of 0 is greater than or equal to the dynamic inductance of the nanowire, and the AC coupling capacitance is... C B The value ranges from 80 nF to 240 nF.

7. A method for implementing a high-count-rate superconducting nanowire single-photon detector with a large photosensitive surface, characterized in that: include: Fabrication of low-dynamic-inductance superconducting nanowires; Construct a discharge acceleration bias readout circuit; The low dynamic inductance superconducting nanowire is connected to the discharge acceleration bias readout circuit, and the number of photons detected by the low dynamic inductance superconducting nanowire is read out by the discharge acceleration bias readout circuit. The low dynamic inductance superconducting nanowires were fabricated according to the following steps: Step 1: Deposit a niobium nitride thin film on the silicon nitride layer; Step 2: Obtain nanowire patterns by electron beam exposure, and then obtain nanowires by reactive ion etching after development; Step 3: Obtain the on-chip resistor pattern using electron beam exposure; Step 4: Grow a Ti thin film using magnetron sputtering; Step 5: Strip to obtain the on-chip resistor; The nanowire pattern is composed of several channels arranged in a centrally symmetrical manner, and each channel is composed of multiple nanowires connected in parallel. The multiple nanowires in the same channel are arranged in a concentric circle, and each nanowire is a concentric ring structure. The resistance pattern is such that an on-resistor is connected in series with ground on each of the nanowires; The discharge acceleration bias readout circuit includes: an inductor L B Series resistors R 0. Inductance L 0. AC coupling capacitor C B and low-noise amplifier; the inductor L B The two ends are respectively used as the DC terminal and the DC & RF terminal, and the series resistor R One end of the series resistor is connected to the DC & RF terminals. R The other end of 0 is connected to the AC coupling capacitor. C B The two are connected in series with an inductor between them. L 0 to ground, AC coupling capacitor C B The other end is connected to a low-noise amplifier, from which the number of photons detected by the low dynamic inductance superconducting nanowire is read out; the DC & RF terminal is connected to the low dynamic inductance superconducting nanowire and is used to provide bias current to the low dynamic inductance superconducting nanowire and to obtain the number of photons detected by the low dynamic inductance superconducting nanowire; the DC terminal is used to input current to the discharge acceleration bias readout circuit.

8. A method for implementing a large photosensitive surface area, high count rate superconducting nanowire single-photon detector according to claim 7, characterized in that: Each on-chip resistor has a dumbbell-shaped structure, and all on-chip resistors are connected as a whole.

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