Mainboard, hot plug control signal generator and control signal generation method thereof

Abstract

A motherboard, a hot plug control signal generator and a control signal generating method thereof are provided. The hot plug control signal generator includes a controller and a latch. The controller provides a control signal. The latch operates based on an operating power to generate a hot plug control signal. The latch causes the hot plug control signal to be a first logic value that disables the hot plug control signal and causes the hot plug control signal to be latched at the first logic value according to the control signal.

Description

Technical Field

[0001] This invention relates to a motherboard, a hot-insertion control signal generator, and a method for generating the control signal therefrom, and particularly to a hot-insertion control signal generator and a method for generating the control signal therefrom that can ensure the safety of the motherboard. Background Technology

[0002] In modern technology, hot-plug controllers can be used to manipulate the power switch on a motherboard. Specifically, when an abnormality occurs on the motherboard, the hot-plug controller can cut off the power switch to prevent power from flowing to the motherboard. However, in known computer systems, after a server tray is re-plugged, the server will again supply power to the motherboard. Therefore, it is possible to cause more serious damage to the motherboard before engineers can perform effective analysis and troubleshooting. Summary of the Invention

[0003] This invention relates to a motherboard, a hot-insertion control signal generator, and a method for generating the hot-insertion control signal thereon, which can latch the hot-insertion control signal generated by abnormal phenomena to ensure the safety of the motherboard.

[0004] According to an embodiment of the present invention, a hot-insertion control signal generator includes a controller and a latch. The controller provides a control signal. The latch is coupled to the controller. The latch operates based on an operating power supply to generate the hot-insertion control signal. The latch, according to the control signal, sets the hot-insertion control signal to a first logic value that disables it, and latches the hot-insertion control signal to the first logic value.

[0005] According to an embodiment of the present invention, the motherboard includes a hot-insertion controller and a hot-insertion control signal generator. The hot-insertion control signal generator includes a controller and a latch. The controller provides a control signal. The latch is coupled to the controller. The latch operates based on an operating power supply to generate the hot-insertion control signal. The latch, according to the control signal, sets the hot-insertion control signal to a first logic value that disables it, and latches the hot-insertion control signal to the first logic value.

[0006] According to an embodiment of the present invention, a method for generating a hot-insertion control signal includes: causing a controller to provide a control signal; providing a latch to operate based on an operating power supply to generate the hot-insertion control signal; providing the latch to disable the hot-insertion control signal to a first logic value according to the control signal; and latching the hot-insertion control signal to the first logic value.

[0007] Based on the above, the hot-insertion control signal generator of the present invention can, when an abnormality occurs on the motherboard, latch the generated hot-insertion control signal, enabling the hot-insertion controller to continuously cut off the power supply according to the latched hot-insertion control signal. In this way, before the fault is definitively eliminated, the motherboard will not be damaged again due to human error, effectively ensuring the safety of the motherboard. Attached Figure Description

[0008] The accompanying drawings are included to further illustrate the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] Figure 1 This is a schematic diagram of a hot-insertion control signal generator according to an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of one embodiment of the latch of the hot-insertion control signal generator according to an embodiment of the present invention;

[0011] Figure 3 This is a schematic diagram of another embodiment of the latch of the hot-insertion control signal generator according to an embodiment of the present invention;

[0012] Figure 4 This is a schematic diagram of a motherboard according to an embodiment of the present invention;

[0013] Figure 5 This is a flowchart illustrating the protection action of a motherboard according to an embodiment of the present invention;

[0014] Figure 6 This is a flowchart of a method for generating a hot-insertion control signal according to an embodiment of the present invention.

[0015] Explanation of icon numbers

[0016] 100, 410: Hot-insertion control signal generator;

[0017] 110, 411: Controller;

[0018] 120, 200, 300, 412: latches;

[0019] 211~213: Pull-up circuit;

[0020] 310: Reset the trigger settings;

[0021] 330: Reset setting latch circuit;

[0022] 400: Motherboard;

[0023] 401: Power Supply;

[0024] 420: Hot-plug controller;

[0025] 430: Power switch;

[0026] AS: Control signal;

[0027] BAT: Battery;

[0028] E, E': signal;

[0029] E1: First end;

[0030] E2: Second end;

[0031] E3: Third end;

[0032] GATE: Gate signal;

[0033] GND: Reference ground terminal;

[0034] HSCE: Hot-insertion control signal;

[0035] IV1, IV2: Inverters;

[0036] LED: Light Emitting Diode;

[0037] LG1: Logic gate;

[0038] LS: Latch signal;

[0039] M1~M5: Transistors;

[0040] ND1~ND3: NAND gates;

[0041] NO3: NOR gate;

[0042] R: Reset terminal;

[0043] R1, R2: Resistors;

[0044] S: Setting end;

[0045] S510~S540, S610~S640: Steps;

[0046] SW1, SW2, SWE: Switches;

[0047] SW3: Pull-down switch;

[0048] SWD: Latch release device;

[0049] SWE external switch;

[0050] V1, V2: Voltage;

[0051] VB: Operating power supply;

[0052] VCC, VPP: Power supply. Detailed Implementation

[0053] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0054] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a hot-insertion control signal generator according to an embodiment of the present invention. The hot-insertion control signal generator 100 includes a controller 110 and a latch 120. The controller 110 is coupled to the latch 120 and is used to provide a control signal AS to the latch 120. The latch 120 receives an operating power supply VB. The latch 120 operates based on the operating power supply VB and generates a hot-insertion control signal HSCE according to the control signal AS.

[0055] In this embodiment, both the controller 110 and the latch 120 can be mounted on the motherboard. Furthermore, when an abnormality occurs on the motherboard, the controller 110 can generate a control signal AS corresponding to the abnormality. Correspondingly, when the latch 120 receives the control signal AS indicating an abnormality on the motherboard, it can set the generated hot-insertion control signal HSCE to a disabled first logic value and latch the hot-insertion control signal HSCE to the first logic value, where the first logic value can be either 0 or 1, without specific limitations.

[0056] The aforementioned abnormal phenomena on the motherboard can be over-temperature (OT) and / or over-current (OC) phenomena occurring on the motherboard.

[0057] In this embodiment, the hot-insertion control signal HSCE can be transmitted to the hot-insertion controller on the motherboard. When the hot-insertion control signal HSCE is latched at a disabled first logic value, the hot-insertion controller can correspondingly generate a gate signal to turn off the power switch on the motherboard and stop power supplied, for example, by a rack power supply, from being input to the motherboard, thereby maintaining the safety of the motherboard. Because the hot-insertion control signal HSCE is latched, the power switch on the motherboard can remain off, preventing further damage to the motherboard due to human error.

[0058] More notably, the operating power VB received by the latch 120 of this disclosure is independent of the rack power received by the power switch. Therefore, when the power switch is turned off, the latch 120 can still continue to operate and maintain the latched state of the hot-insertion control signal HSCE. In this embodiment, the operating power VB can be provided by a battery or by an external power source.

[0059] It is worth noting that in this embodiment, the latch state of the hot-insertion control signal HSCE can only be released through a specific mechanism. Specifically, engineers must ensure that troubleshooting has been completed before initiating this specific mechanism. This ensures the safety of the motherboard.

[0060] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of one embodiment of the latch of the hot-insertion control signal generator according to an embodiment of the present invention. The latch 200 can receive the control signal AS via an external switch SWE. During the protection operation of the main board, the external switch SWE can be in a conducting state. Furthermore, when the external switch SWE is opened, the resistor RD can pull down the voltage of the control terminal of the switch SW1 to the reference ground voltage.

[0061] The latch 200 includes pull-up circuits 211-213, switches SW1 and SW2, and logic gate LG1. Pull-up circuits 211-213 receive the operating power supply VB and are coupled to a first terminal E1, a second terminal E2, and a third terminal E3, respectively. Pull-up circuits 211-213 pull up the voltages on the first terminal E1, the second terminal E2, and the third terminal E3 to the operating power supply VB. Switch SW1 is coupled between the first terminal E1 and the reference ground terminal GND and is turned on or off according to the control signal AS.

[0062] The input terminals of logic gate LG1 are coupled to the first terminal E1 and the second terminal E2, and receive voltages V1 and V2 from the first terminal E1 and the second terminal E2, respectively. Logic gate LG1 is used to perform logical operations on the voltages V1 and V2 from the first terminal E1 and the second terminal E2, and generates a hot-insertion control signal HSCE. In this embodiment, logic gate LG1 is an AND gate, and the above-mentioned logical operation is a logical AND operation. In this embodiment, logic gate LG1 operates based on the operating power supply VB.

[0063] Switch SW2 is coupled between the output of logic gate LG1 and the second terminal E2. The control terminal of switch SW2 is coupled to the third terminal E3.

[0064] The hot-insertion control signal generator 200 of this embodiment includes a latch releaser SWD. The latch releaser SWD may be a switching assembly coupled between the third terminal E3 and the reference ground terminal GND.

[0065] Incidentally, in this embodiment, switches SW1 and SW2 can be implemented using transistors, and pull-up circuits 211 to 213 can be implemented using resistors.

[0066] In terms of operational details, with switch SWE on, when the motherboard is in normal operation, the control signal AS can be a logic value of 0. Switch SW1 can be turned off, causing the voltage V1 on the first terminal E1 to be pulled high by pull-up circuit 211 to become the operating power supply VB, presenting a logic value of 1. Additionally, the voltage V2 on the second terminal E1 is pulled high by pull-up circuit 212 to become the operating power supply VB, presenting a logic value of 1. In this way, logic gate LG1 can generate a hot-insertion control signal HSCE, also with a logic value of 1, based on the voltages V1 and V2, both of which are logic values ​​of 1, enabling the motherboard to operate normally.

[0067] Incidentally, the voltage on terminal E3 can be pulled high by pull-up circuit 213 to become the operating power supply VB, and presents a logic value of 1. Therefore, switch SW2 can be turned on. Logic gate LG1 and switch SW2 form a latch-up circuit.

[0068] Furthermore, also with switch SWE on, when a motherboard malfunctions, control signal AS can be a logic value of 1, switch SW1 can be turned on, and the voltage V1 on the first terminal E1 is pulled down to a logic value of 0. Simultaneously, the output of logic gate LG1 can generate a hot-insertion control signal HSCE with a logic value of 0. This HSCE signal can cause the hot-insertion controller on the motherboard to cut off the power switch and prevent power from the rack power supply from being input to the motherboard, ensuring motherboard safety.

[0069] The key point is that, through the activated switch SW2, the voltage V2 on the second terminal E2 can be pulled low to a logic value of 0 by the output of logic gate LG1. Logic gate LG1 and switch SW2 form a latch-up circuit, which latches the hot-insertion control signal HSCE at the disabled logic value of 0.

[0070] In this embodiment, the latching state of the hot-insertion control signal HSCE can be released by turning on the latch releaser SWD. Alternatively, the latching state of the hot-insertion control signal HSCE can also be released by restarting the operating power supply VB. That is, after confirming that all motherboard faults have been eliminated, engineers can turn on the latch releaser SWD or restart the operating power supply VB to release the latching state of the hot-insertion control signal HSCE and restore the motherboard's operation.

[0071] Please refer to the following: Figure 3 , Figure 3This is a schematic diagram of another embodiment of the latch of the hot-insertion control signal generator according to an embodiment of the present invention. The latch 300 can receive the control signal AS via an external switch SWE. During the protection operation of the main board, the external switch SWE can be in a conducting state. Furthermore, when the external switch SWE is opened, the resistor RD can pull down the voltage of the control terminal of the switch SW1 to the reference ground voltage.

[0072] The latch 300 includes a reset-set (RS) trigger 310 and a pull-down switch SW3. The reset-set trigger 310 includes a reset-set latch (RS Latch) circuit 330, NAND gates ND1-ND3, NOR gate NO3, inverters IV1 and IV2, and transistors M3 and M4. The reset-set latch circuit 330 is composed of NAND gates ND2 and ND3. The setting terminal S of the reset-set latch circuit 330 receives the inverted signal of the control signal AS through inverter IV1, and the reset terminal R of the reset-set latch circuit 330 is coupled to the reference ground terminal GND through inverter IV2.

[0073] NAND gate ND1 and NOR gate NO3 are both coupled to the output of the reset latch circuit 330. The other input of NAND gate ND1 receives signal E, where signal E can be a logic value of 1. The other input of NOR gate NO3 receives signal E', where signal E' can be a logic value of 0. Transistors M3 and M4 are connected in series between the operating power supply VB and the reference ground GND. The control terminals of transistors M3 and M4 are respectively coupled to the outputs of NAND gate ND1 and NOR gate NO3. Transistors M3 and M4 are used to generate the latch signal LS.

[0074] The pull-down switch SW3 determines whether to pull down the hot-insertion control signal HSCE based on the latch signal LS. When the pull-down switch SW3 is on, the hot-insertion control signal HSCE can be pulled down to logic value 0. Conversely, when the pull-down switch SW3 is off, the hot-insertion control signal HSCE can be in a state of logic value 1 due to the voltage division of the power supply VCC corresponding to resistors R1 and R2.

[0075] In this embodiment, the pull-down switch SW3 can be constructed using transistor M5.

[0076] In terms of operational details, with switch SWE on, when the motherboard is in normal operation, the control signal AS can be a logic value of 0. At this time, the voltages on the setting terminal S and the reset terminal R of the reset setting latch circuit 330 are both logic values ​​of 0. The latch signal LS generated by the reset setting trigger 310 can then be equal to its initial value and a logic value of 0. Correspondingly, the pull-down switch SW3 is turned off, the hot-insertion control signal HSCE can be maintained at a logic value of 1, and the motherboard can operate normally.

[0077] Furthermore, also with switch SWE on, when a motherboard malfunctions, the control signal AS can be a logic value of 1. At this time, the reset setting latch circuit 330 can set the output signal generated by NOR gate NO1 to a logic value of 1 based on the voltage of logic value 1 on the setting terminal S. Furthermore, based on the output signal of NOR gate NO1 and signal E, NAND gate ND1 can generate an output signal with a logic value of 0, and turn on transistor M3. Correspondingly, NOR gate NO3 can generate an output signal with a logic value of 0 based on the output signal generated by NOR gate NO1 (which is a logic value of 1) and signal E' (which is a logic value of 0), and turn off transistor M4.

[0078] With transistor M3 turned on (transistor M4 turned off), the latch signal LS can be equal to the operating power supply VB, resulting in a logic value of 1. The pull-down switch SW3 can then be turned on, setting the hot-insertion control signal HSCE to a logic value of 0. Here, the hot-insertion control signal HSCE, with a logic value of 0, causes the hot-insertion controller on the motherboard to turn off the power switch and prevent power from the rack power supply from being input to the motherboard, ensuring motherboard safety.

[0079] Please note that because the reset terminal R of the reset setting latch circuit 330 is coupled to the reference ground terminal GND, the hot-insertion control signal HSCE can be latched at a logic value of 0. This effectively maintains the safety of the motherboard.

[0080] After engineers have effectively eliminated the abnormality of the motherboard, they can restart the operating power supply VB to release the latch state of the hot-insertion control signal HSCE and restore the motherboard to normal operation.

[0081] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of a motherboard according to an embodiment of the present invention. The motherboard 400 includes a hot-insertion control signal generator 410, a hot-insertion controller (HSC) 420, and a power switch 430. The hot-insertion control signal generator 410 is coupled to the hot-insertion controller 420. The hot-insertion control signal generator 410 includes a controller 411 and a latch 412. The controller 411 can be coupled to the latch 412 via a switch SWE. When the abnormal phenomenon protection mechanism of the motherboard 400 is executed, the switch SWE is in a conducting state. The operational details of the hot-insertion control signal generator 410 have been described in detail in the foregoing embodiments and implementation methods, and will not be repeated here. In other embodiments of the present invention, the motherboard 400 also includes a processor and chipset coupled to the controller 420, and electronic components such as a solid-state drive and memory coupled to the processor.

[0082] It is worth mentioning that the latch 412 can receive the operating power VB via battery BAT or via an external power source.

[0083] Furthermore, in this embodiment, the hot-insertion controller 420 is coupled to the hot-insertion control signal generator 410 and the power switch 430. The hot-insertion controller 420 receives the hot-insertion control signal HSCE generated by the hot-insertion control signal generator 410 and generates a gate signal GATE based on the hot-insertion control signal HSCE. The hot-insertion controller 420 provides the gate signal GATE to the control terminal of the power switch 430 to control the on and off states of the power switch 430.

[0084] In detail, when the hot-insertion control signal HSCE is enabled, the hot-insertion controller 420 can provide a gate signal GATE to turn on the power switch 430; conversely, when the hot-insertion control signal HSCE is disabled, the hot-insertion controller 420 can provide a gate signal GATE to turn off the power switch 430.

[0085] A power switch 430 is coupled to a power supply 401. The power supply 401 may be a rack power supply. The on / off state of the power switch 430 determines whether the power supply VPP generated by the power supply 401 is transmitted to the motherboard 400. In this embodiment, when the motherboard 400 is in a normal state, the power switch 430 is turned on and transmits the power VPP to the motherboard 400; conversely, when the motherboard 400 malfunctions, the power switch 430 is turned off and prevents the transmission of power VPP to the motherboard 400, ensuring the safety of the motherboard 400. In some embodiments of the present invention, electronic components on the motherboard 400, such as the controller 411, processor, chipset, solid-state drive, and memory, can be powered by the power supply 401, and these electronic components can operate independently of the operating power supply VP. In some embodiments of the present invention, the operating power supply VP can operate independently of the power supply 401.

[0086] Incidentally, the hot-insertion controller 420 and latch 412 can be connected to a light-emitting diode (LED). The cathode of the LED can receive the hot-insertion control signal HSCE and illuminate when the hot-insertion control signal HSCE is a logic value of 0, informing engineers that an abnormality has occurred on the mainboard 400.

[0087] In this embodiment of the invention, the controller 411 can be a power management chip, a current and / or temperature sensor, or a microprocessor chip with computing capabilities, without any specific limitations.

[0088] Please refer to Figure 5 , Figure 5This is a flowchart illustrating the protection operation of a motherboard according to an embodiment of the present invention. In step S510, when the motherboard is powered on, the motherboard is in a normal state, the controller maintains a preset state, the latch is not triggered, and the hot-plug control signal is output normally (in an enabled state). At this time, the hot-plug controller can turn on the power switch in the motherboard, enabling the motherboard to operate normally. Next, when a problem occurs on the motherboard, in step S520, an abnormal phenomenon occurs on the board (motherboard). There may be a short circuit in a component on the motherboard, causing excessive current (OC) and / or overheating (OT).

[0089] Next, the controller can detect the aforementioned OC and OT phenomena, and in step S530, the controller sends the corresponding control signal and triggers the latch, pulling the hot-insertion control signal low and latching it. In this way, the hot-insertion controller can cut off the power switch in the motherboard to protect the motherboard from further damage.

[0090] Next, under the condition that the line is latched, in step S540, the hot-insertion control signal can be manually reset to its initial state and become unlatched. Furthermore, after the problem is effectively resolved, the motherboard can return to step S510 and resume normal operation by manually resetting and powering on.

[0091] Please refer to the following: Figure 6 , Figure 6 This is a flowchart illustrating a method for generating a hot-insertion control signal according to an embodiment of the present invention. In step S610, a controller provides a control signal. In step S620, a latch is provided to operate based on the operating power supply to generate the hot-insertion control signal. In step S630, the latch is provided to disable the hot-insertion control signal to a first logic value according to the control signal. In step S640, the hot-insertion control signal is latched to the first logic value to effectively maintain the security of the motherboard.

[0092] The implementation details of the above steps have been described in detail in the aforementioned embodiments and implementation methods, and will not be repeated hereafter.

[0093] In summary, this invention generates a control signal by reflecting abnormal phenomena on the motherboard, and sets and latches the hot-plug control signal in a disabled state based on the control signal. By using the hot-plug control signal in the disabled state, the power switch on the motherboard can be turned off, preventing power from being transmitted into the motherboard's interior, effectively protecting the motherboard from further damage.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hot-insertion control signal generator, comprising: The controller provides control signals; as well as A latch, coupled to the controller, operates based on an operating power supply to generate a hot-insertion control signal. The latch, according to the control signal, causes the hot-insertion control signal to a first logic value that disables it, and latches the hot-insertion control signal at the first logic value. The latch includes: Multiple pull-up circuits are respectively coupled to the first terminal, the second terminal and the third terminal to pull up the voltage on the first terminal, the second terminal and the third terminal to the operating power supply. A first switch is coupled between the first terminal and the reference ground terminal, and is turned on or off according to the control signal; A logic gate having two inputs coupled to the first and second terminals respectively, performs logic operations on the voltages at the first and second terminals to generate the hot-insertion control signal; and A second switch is coupled between the first terminal and the output terminal of the logic gate. The control terminal of the second switch is coupled to the third terminal and is turned on or off according to the voltage on the third terminal. The latch receives the operating power via a battery or an external power source.

2. The hot-insertion control signal generator according to claim 1, wherein the hot-insertion control signal generator is disposed on the motherboard, and when the motherboard malfunctions, the controller provides the control signal to cause the latch to latch the hot-insertion control signal at the first logic value.

3. The hot-insertion control signal generator according to claim 1, wherein the logical operation is a logical AND operation.

4. The hot-insertion control signal generator according to claim 1 further includes: A latch releaser is used to short-circuit the output of the logic gate to the reference ground terminal and release the latch state of the hot-insertion control signal.

5. The hot-insertion control signal generator according to claim 1, wherein the latch comprises: The system resets the trigger, receives the control signal and the operating power supply, and generates a latching signal based on the operating power supply and the control signal. as well as A pull-down switch is used to determine whether to pull down the hot-insertion control signal based on the latch signal.

6. The hot-insertion control signal generator according to claim 5, wherein the reset setting trigger comprises: First NAND gate; The second NAND gate is coupled to the first NAND gate to form a reset setting latch circuit. The setting terminal of the reset setting latch circuit receives the inverse signal of the control signal. The reset terminal of the reset setting latch circuit is coupled to the reference ground terminal through a checker. The third NAND gate has a first input terminal coupled to the output terminal of the reset setting latch circuit, and the second input terminal of the third NAND gate receives a second logic value. The NOR gate has a first input terminal coupled to the output terminal of the reset setting latch circuit, and the second input terminal of the NOR gate receives the first logic value. as well as The first transistor and the second transistor are connected in series between the operating power supply and the reference ground terminal. The control terminals of the first transistor and the second transistor are respectively coupled to the output terminals of the third NAND gate and the NOR gate. The first transistor and the second transistor are used to generate the latch signal.

7. The hot-insertion control signal generator according to claim 6, wherein the latching state of the hot-insertion control signal is released after the operating power supply is restarted.

8. A motherboard, comprising: Hot-insertion controller, which receives hot-insertion control signals; as well as A hot-insertion control signal generator, coupled to the hot-insertion controller, the hot-insertion control signal generator comprising: The controller provides control signals; and A latch, coupled to the controller, operates based on an operating power supply to generate the hot-insertion control signal. The latch, according to the control signal, causes the hot-insertion control signal to a first logic value that disables it, and latches the hot-insertion control signal at the first logic value. The latch includes: Multiple pull-up circuits are respectively coupled to the first terminal, the second terminal and the third terminal to pull up the voltage on the first terminal, the second terminal and the third terminal to the operating power supply. A first switch is coupled between the first terminal and a reference ground terminal, and is turned on or off according to the control signal; A logic gate having two inputs coupled to the first and second terminals respectively, performs a logic operation on the voltages at the first and second terminals to generate the hot-insertion control signal; and A second switch is coupled between the first terminal and the output terminal of the logic gate. The control terminal of the second switch is coupled to the third terminal and is turned on or off according to the voltage on the third terminal. The latch receives the operating power via a battery or an external power source.

9. The motherboard of claim 8, wherein when an abnormality occurs on the motherboard, the controller provides the control signal to cause the latch to latch the hot-insertion control signal at the first logic value.

10. The motherboard according to claim 8, wherein the logical operation is a logical AND operation.

11. The motherboard according to claim 8, wherein the hot-plug control signal generator further comprises: A latch releaser is used to short-circuit the output of the logic gate to the reference ground terminal and release the latch state of the hot-insertion control signal.

12. The motherboard of claim 8, wherein the latch comprises: The system resets the trigger, receives the control signal and the operating power supply, and generates a latching signal based on the operating power supply and the control signal. as well as A pull-down switch is used to determine whether to pull down the hot-insertion control signal based on the latch signal.

13. The motherboard of claim 12, wherein the reset setting trigger comprises: First NAND gate; The second NAND gate is coupled to the first NAND gate to form a reset setting latch circuit. The setting terminal of the reset setting latch circuit receives the inverted signal of the control signal, and the reset terminal of the reset setting latch circuit is coupled to the reference ground terminal through an inverter. The third NAND gate has a first input terminal coupled to the output terminal of the reset setting latch circuit, and the second input terminal of the third NAND gate receives the operating power supply. The NOR gate has a first input terminal coupled to the output terminal of the reset setting latch circuit, and the second input terminal of the NOR gate receives the reverse voltage of the operating power supply. as well as The first transistor and the second transistor are connected in series between the operating power supply and the reference ground terminal. The control terminals of the first transistor and the second transistor are respectively coupled to the output terminals of the third NAND gate and the NOR gate. The first transistor and the second transistor are used to generate the latch signal.

14. The motherboard according to claim 13, wherein the latch state of the hot-insertion control signal is released after the operating power is restarted.

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