Timing simulation method, system, computer device and readable storage medium
Patent Information
- Application Number
- CN202210338646.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-01
- Publication Date
- 2026-10-23
- Estimated Expiration
- 2042-04-01
AI Technical Summary
[0002]目前，在对芯片进行时序验证时，譬如，在对DRAM(Dynamic Random AccessMemory,动态随机存取存储器)进行全芯片时序验证时，会使用到种类众多的测试向量(Patterns)；而在目前时序验证过程中，需要逐一对各所述测试向量进行仿真验证，这就导致目前的时序验证存在时序验证时间较长及时序验证效率较低等问题
[0046]上述时序仿真方法，通过将多个测试向量中具有重复时间段的测试向量进行分组得到多组测试向量组合，然后提前各测试向量组合中不同测试向量的重复时间段得到多个提取向量后对提取向量进行仿真，最后再对各测试向量组合中各测试向量的差异时间段进行仿真，在整个仿真过程中，同一测试向量组合中的不同测试向量的重复时间段可以一次进行仿真，大大缩短了整个时序仿真过程中的时序仿真时间，显著提高了仿真效率。
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Figure CN116933704B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a timing simulation method, system, computer device, and readable storage medium. Background Technology
[0002] Currently, when performing timing verification on chips, such as when performing full-chip timing verification on DRAM (Dynamic Random Access Memory), a wide variety of test patterns are used. However, in the current timing verification process, each of these test patterns needs to be simulated and verified one by one. This results in problems such as long timing verification time and low timing verification efficiency. Summary of the Invention
[0003] Therefore, it is necessary to provide a timing simulation method, system, computer device, and readable storage medium to solve the above-mentioned problems in the prior art.
[0004] To achieve the above objectives, this application provides a timing simulation method, comprising:
[0005] Obtain multiple test vectors;
[0006] The test vectors are grouped to obtain multiple test vector combinations. In each test vector combination, the different test vectors have both repeated time periods and different time periods.
[0007] Extract the repeated time periods of different test vectors in each of the test vector combinations to obtain multiple extracted vectors;
[0008] Simulations are performed based on the extracted vectors to obtain the corresponding initial simulation snapshots;
[0009] Based on the corresponding initial simulation snapshot, the time intervals of the differences between the test vectors in each of the test vector combinations are simulated.
[0010] In one embodiment, grouping the multiple test vectors to obtain multiple test vector combinations includes:
[0011] Compare each of the test vectors described;
[0012] The test vectors that have a preset time interval starting from the start time are assigned to the same test vector combination.
[0013] In one embodiment, the step of assigning the test vectors of repeating time periods with a preset time from the start time to the same test vector combination includes:
[0014] The test vectors of repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level;
[0015] Determine whether there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time;
[0016] If so, the test vectors with repeated time periods of the second-level preset time will be assigned to the same test vector combination of the second level.
[0017] In one embodiment, after assigning the test vectors of the repetitive time intervals with a second-level preset time to the same test vector combination at the second level, the method further includes:
[0018] Determine whether there are test vectors in the same test vector combination of the previous level that have a repeated time period with a preset time of the next level starting from the previous level; the preset time of the next level is greater than the preset time of the previous level.
[0019] If so, the test vectors with the same repeating time period of the next level preset time will be assigned to the same test vector combination of the next level.
[0020] In one embodiment, after assigning test vectors with repeating time intervals having a next-level preset time to the same test vector combination at the next level, the method further includes:
[0021] Repeat the process of assigning test vectors with a preset time period to the same test vector combination at the next level several times until the repeated time period in the same test vector combination at the highest level reaches the preset length.
[0022] In one embodiment, the difference between the preset times of each adjacent level is the same.
[0023] In one embodiment, the step of extracting the repetitive time periods of different test vectors in each test vector combination to obtain multiple extracted vectors includes:
[0024] Extract the repetitive time periods of different test vectors in each highest-level test vector combination to obtain multiple extracted vectors.
[0025] In one embodiment, the test vector includes data for testing or operating the chip under test, the data including logic 1s and logic 0s.
[0026] In one embodiment, the step of performing simulation based on each of the extracted vectors to obtain a corresponding initial simulation snapshot includes: inputting each of the extracted vectors into a simulator, wherein the simulator is used to perform simulation based on the input extracted vectors and output an initial simulation snapshot;
[0027] The step of simulating the difference time periods of each test vector in each test vector combination based on the corresponding initial simulation snapshot includes: inputting the initial simulation snapshot and the difference time periods of each test vector in each test vector combination into the simulator, and the simulator is further used to perform simulation based on the input difference time periods of the test vectors and the initial simulation snapshot, and output simulation results.
[0028] This application also provides a timing simulation system, including:
[0029] The acquisition module is used to acquire multiple test vectors;
[0030] A processing module, connected to the acquisition module, is configured to:
[0031] The test vectors are grouped to obtain multiple test vector combinations. In each test vector combination, the different test vectors have both repeated time periods and different time periods.
[0032] Extract the repeated time periods of different test vectors in each of the test vector combinations to obtain multiple extracted vectors;
[0033] Simulations are performed based on the extracted vectors to obtain the corresponding initial simulation snapshots;
[0034] Based on the corresponding initial simulation snapshot, the time intervals of the differences between the test vectors in each of the test vector combinations are simulated.
[0035] In one embodiment, the processing module includes:
[0036] A grouping processing unit, connected to the acquisition module, is used to group multiple test vectors to obtain multiple test vector combinations. In each test vector combination, different test vectors have repetitive time periods and different time periods.
[0037] An extraction unit, connected to the grouping processing unit, is used to extract the repetitive time periods of different test vectors in each test vector combination to obtain multiple extracted vectors.
[0038] The simulation unit, connected to the grouping processing unit and the extraction unit, is used to perform simulation based on each of the extracted vectors to obtain the corresponding initial simulation snapshot, and to simulate the time difference of each of the test vectors in each combination of test vectors based on the corresponding initial simulation snapshot.
[0039] In one embodiment, the simulation unit includes:
[0040] The first simulation unit is connected to the extraction unit and is used to perform simulation based on each of the extraction vectors to obtain the corresponding initial simulation snapshot;
[0041] The second simulation unit, connected to the group processing unit and the first simulation unit, is used to simulate the difference time periods in each of the test vector combinations.
[0042] In one embodiment, the test vector includes data for testing or operating the chip under test, the data including logic 1s and logic 0s.
[0043] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the timing simulation method as described in the above scheme.
[0044] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the timing simulation method as described in any of the above schemes.
[0045] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the timing simulation method as described in any of the above schemes.
[0046] The aforementioned timing simulation method groups test vectors with repetitive time periods into multiple test vector combinations. Then, it extracts multiple vectors by pre-calculating the repetitive time periods of different test vectors within each test vector combination and simulates these extracted vectors. Finally, it simulates the different time periods of each test vector within each test vector combination. Throughout the simulation process, the repetitive time periods of different test vectors within the same test vector combination can be simulated at once, greatly shortening the timing simulation time and significantly improving simulation efficiency.
[0047] The processing module in the aforementioned timing simulation system groups test vectors with repetitive time periods into multiple test vector combinations. Then, it extracts multiple vectors by pre-calculating the repetitive time periods of different test vectors within each test vector combination and simulates these extracted vectors. Finally, it simulates the different time periods of each test vector within each test vector combination. Throughout the simulation process, the repetitive time periods of different test vectors within the same test vector combination can be simulated at once, greatly shortening the timing simulation time and significantly improving simulation efficiency. Attached Figure Description
[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a flowchart of a timing simulation method provided in one embodiment of this application;
[0050] Figure 2 This is a schematic diagram of multiple test vectors in a timing simulation method provided in one embodiment of this application;
[0051] Figures 3 to 5 The timing simulation method provided in one embodiment of this application is for... Figure 2 A schematic diagram illustrating the simulation using multiple test vectors.
[0052] Figure 6 This is a schematic diagram illustrating the grouping of multiple test vectors in a timing simulation method provided in one embodiment of this application.
[0053] Figures 7 to 9 The following are structural block diagrams of timing simulation systems provided in different embodiments of this application.
[0054] Explanation of reference numerals in the attached figures:
[0055] 10 - Acquisition module, 20 - Processing module, 201 - Grouping processing unit, 202 - Extraction unit; 203 - Simulation unit, 2031 - First simulation unit, 2032 - Second simulation unit. Detailed Implementation
[0056] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0058] It is understood that the terms "first," "second," etc., used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first power input terminal may be referred to as a second power input terminal, and similarly, a second power input terminal may be referred to as a first power input terminal. Both the first power input terminal and the second power input terminal are power input terminals, but they are not the same power input terminal.
[0059] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0060] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.
[0061] Please see Figure 1 This application provides a timing simulation method, which may include the following steps:
[0062] S10: Obtain multiple test vectors;
[0063] S20: Group multiple test vectors to obtain multiple test vector combinations. In each test vector combination, different test vectors have repeated time periods and different time periods.
[0064] S30: Extract the repeated time periods of different test vectors in each test vector combination to obtain multiple extracted vectors;
[0065] S40: Perform simulation based on each extracted vector to obtain the corresponding initial simulation snapshot;
[0066] S50: Based on the corresponding initial simulation snapshot, simulate the time difference between each test vector in each test vector combination.
[0067] The aforementioned timing simulation method groups test vectors with repetitive time periods into multiple test vector combinations. Then, it extracts multiple vectors by pre-calculating the repetitive time periods of different test vectors within each test vector combination and simulates these extracted vectors. Finally, it simulates the different time periods of each test vector within each test vector combination. Throughout the simulation process, the repetitive time periods of different test vectors within the same test vector combination can be simulated at once, greatly shortening the timing simulation time and significantly improving simulation efficiency.
[0068] In one example, the test vector obtained in step S10 can be, but is not limited to, the test vector obtained during timing verification of the chip; specifically, the test vector obtained in step S10 can be the test vector obtained during full-chip timing verification of the DRAM. The test vector can be a timing waveform diagram.
[0069] In one example, step S20, which involves grouping multiple test vectors to obtain multiple test vector combinations, may include the following steps:
[0070] S201: Compare the test vectors;
[0071] S202: Assign test vectors that have a preset time interval from the start time to the same test vector combination.
[0072] Specifically, in step S201, multiple test vectors can be placed in the same coordinate system from the same starting point to compare each test vector; of course, multiple test vectors can also be superimposed to compare each test vector.
[0073] Specifically, in step S202, test vectors of repeating time-series waveforms with a preset time starting from the start time can be assigned to the same test vector combination. This ensures that each test vector in the same test vector combination has a repeating time period with a preset time.
[0074] As an example, step S202, which assigns test vectors for repeated time periods with a preset start time to the same test vector combination, may include the following steps:
[0075] S2021: Assign test vectors for repeated time periods with a first-level preset time from the start time to the same test vector combination at the first level;
[0076] S2022: Determine whether there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time;
[0077] S2023: If so, the test vectors of the repeated time periods with the second-level preset time will be assigned to the same test vector combination of the second level.
[0078] Specifically, in step S2021, test vectors of repeating time periods of the same time-series waveform with the same preset time of the first level can be assigned to the same test vector combination of the first level by comparison.
[0079] Specifically, in step S2022, each test vector in the same test vector combination that has been assigned to the first level is compared to determine whether there are test vectors in the same test vector combination that have the same time sequence waveform with the second level preset time and repeating time period.
[0080] Specifically, in step S2023, if in step S2022 it is determined that there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time from the start time, then the same test vector combination of the first level will be divided into the next level, and the test vectors with the same time waveform diagram with the second-level preset time will be assigned to the same test vector combination of the second level.
[0081] Through the above steps, the obtained multiple test vectors can be divided and combined into first-level and second-level partitions.
[0082] In one example, after step S2023, if there are still test vectors with repeated time periods longer than the preset time of the second level in the same test vector combination, step S2023, after assigning the test vectors with repeated time periods of the preset time of the second level to the same test vector combination of the second level, may also include the following steps:
[0083] S2024: Determine whether there are test vectors in the same test vector combination of the previous level that have a repeated time period with the preset time of the next level starting from the start time; the preset time of the next level is greater than the preset time of the previous level.
[0084] S2025: If so, the test vectors of the repeated time periods with the next level preset time will be assigned to the same test vector combination at the next level.
[0085] Specifically, in step S2024, it can be determined by comparison whether there are test vectors in the same test vector combination of the previous level that have the same time sequence waveform with the next level preset time and a repetitive time period from the start time.
[0086] Specifically, in step S2025, if in step S2024 it is determined that there is a test vector in the same test vector combination of the previous level that has a repeated time period from the start time to the next level preset time, then the same test vector combination of the previous level is divided into the next level, and the test vectors with the same time sequence waveform diagram with the next level preset time are assigned to the same test vector combination of the next level.
[0087] In one example, after step S2025, if the obtained same test vector combination still contains test vectors with a repetitive time period greater than the most recent preset time, the test vectors with the repetitive time period of the next level preset time will be assigned to the same test vector combination at the next level. The following steps may also be included:
[0088] S2026: Repeat the step of assigning test vectors with a preset time period to the same test vector combination at the next level several times until the repeated time period in the same test vector combination at the highest level reaches the preset length.
[0089] In one example, test vectors can be grouped continuously until the longest repetition time period is reached in the highest-level combination of the same test vectors.
[0090] The above method can maximize the division of test vectors with repetitive time periods that have the same timing waveform, thereby saving time required for subsequent simulations.
[0091] In one example, the difference between the preset times of each adjacent level can be the same.
[0092] In another example, the difference between the preset times of each adjacent level may not be the same. In this case, the length of the preset time of each level can be selected according to the timing waveform of the test vector.
[0093] In one example, step S30, extracting the repetitive time periods of different test vectors in each test vector combination to obtain multiple extracted vectors, may include the following steps:
[0094] Extract the recurring time periods of different test vectors in each highest-level test vector combination to obtain multiple extracted vectors.
[0095] If the test vectors can be divided into multi-level test vector combinations, by extracting the repetition time periods of different test vectors in the highest-level test vector combination, the maximum repetition time period range between different test vectors in each test vector combination can be obtained, thereby minimizing the subsequent simulation time.
[0096] In one example, the test vector includes data used to test or operate the chip under test, and the data may include logic 1s and logic 0s.
[0097] In one example, step S40, which involves performing a simulation based on each extracted vector to obtain the corresponding initial simulation snapshot, may include: inputting each extracted vector into the simulator, which then performs a simulation based on the input extracted vector and outputs the initial simulation snapshot.
[0098] Specifically, the simulator can be any existing simulator used for test vector simulation. The simulator performs simulation based on the extracted input vector to obtain the output initial simulation image. The specific method is not limited here.
[0099] It should be noted that the initial simulation snapshot is the simulation result obtained after simulating the multiple extracted vectors obtained in step S30.
[0100] In one example, in step S50, based on the corresponding initial simulation snapshot, the simulation of the difference time period of each test vector in each test vector combination may include: inputting the initial simulation snapshot and the difference time period of each test vector in each test vector combination into the simulator respectively; the simulator is also used to perform simulation based on the input difference time period of the test vector and the initial simulation snapshot, and output the simulation results.
[0101] Please combine Figures 2 to 5 ,by Figure 2 Using test vectors 1 to 7 as examples, the timing simulation method of this application is described in detail.
[0102] It should be noted that in other examples, the number of test vectors and the timing waveforms of each test vector are not based on... Figure 2 The examples provided are for reference only; you can adjust the settings according to your actual needs.
[0103] first, Figure 2 The test vectors in the example are examples of obtaining multiple test vectors in the simulation method of this application.
[0104] Secondly, Figure 2 The seven test vectors were compared.
[0105] Then, the test vectors for repeated time periods with a preset start time are grouped into the same test vector combination. Specifically, this can be done by first selecting, based on the timing waveform diagrams of the seven test vectors, as follows: Figure 2 Using the time t1 shown as the reference point, select snapshot1 = t1 - 10 picoseconds (picoseconds) for the first grouping of test vector combinations; then select as shown... Figure 2Using time t2 as the baseline, snapshot2 = t2 - 10ps is selected for the second group of test vectors. Then, the first group of test vectors obtained based on snapshot1 = t1 - 10ps is further graded: the first group of first-level test vectors obtained based on snapshot1 = t1 - 10ps is selected as follows... Figure 2 Using time t3 as the reference point, the first group of test vector combinations is classified into the second level. The first group of second-level test vector combinations is obtained based on snapshot3 = t3 - 10ps.
[0106] Through the above comparison and grouping, we can Figure 2 The seven test vectors are divided into three test vector combinations, with test vector 4 and test vector 5 forming one test vector combination (e.g., ...). Figure 3 As shown), test vector 3 and test vector 6 are combined into a single test vector combination (as shown). Figure 4 As shown), test vector 1, test vector 2, and test vector 7 are combined into a test vector combination (e.g., Figure 5 (As shown).
[0107] Next, the repeated time periods of different test vectors in the test vector combinations containing test vectors 4 and 5, test vectors 3 and 6, and test vectors 1, 2, and 7 are extracted to obtain multiple extracted vectors. The extraction storage point corresponding to the test vector combination containing test vectors 4 and 5 (i.e., the cutoff time point of the corresponding initial simulation snapshot after simulation) is as follows: Figure 3 Save Point 1 in the dataset yields the extraction vector, which is the timing waveform corresponding to the time interval from the start time to Save Point 1. The extraction storage point corresponding to the test vector combination containing test vectors 3 and 6 is as follows: Figure 4 Save Point 2 in the dataset yields the extraction vector, which is the timing waveform corresponding to the time interval from the start time to Save Point 2. The extraction storage point corresponding to the test vector combination containing test vector 1, test vector 2, and test vector 7 is as follows: Figure 5 The Save Point 3 parameter yields the extracted vector, which is the time-series waveform corresponding to the time interval from the start time to Save Point 3. After extracting the extracted vectors from each test vector combination, the time intervals of difference between each test vector in each combination are also obtained.
[0108] Next, simulations are performed based on each extracted vector to obtain the corresponding initial simulation snapshots; specifically, for example... Figure 3 , Figure 4 and Figure 5Snapshot vector simulation is performed on the extracted vectors from the test vector combinations to obtain the initial simulation snapshot of each test vector combination.
[0109] Finally, based on the corresponding initial simulation snapshot, for Figure 3 , Figure 4 and Figure 5 The simulation is performed on the time intervals of the differences between the test vectors in each combination of test vectors to obtain the desired simulation results.
[0110] In one example, an example of grouping multiple test vectors is as follows: Figure 6 As shown, for this example, the following limitations should be noted: taking the duration of each test vector in the test vectors (All Patterns) as 1000ns as an example, of course, in other examples, the duration of each test vector is not limited to this; specifically, it may include the following steps:
[0111] The test vectors for repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level. Figure 6 The test vectors are divided into two first-level test vector combinations (Group1 and Group2); the test vectors in both Group1 and Group2 have a repeating time period of the second-level preset time. Figure 6 Taking the first-level preset time of 100ns as an example;
[0112] The test vectors in the first-level test vector combination that have repetitive time intervals with the second-level preset time are assigned to the second-level test vector combination. Figure 6 The test vector combinations in Group 1 are further divided into second-level test vector combinations Group 1-1 and Group 1-2, and the test vector combinations in Group 2 are further divided into second-level test vector combinations Group 2-1 and Group 2-2. Among them, the test vectors in the second-level test vector combinations Group 1-1 and Group 2-1 all have a repeating time period of the third-level preset time, while the test vectors in the second-level test vector combinations Group 1-2 and Group 2-2 do not have a repeating time period of the third-level preset time. Figure 6 The example uses a preset time of 200ns for the second level.
[0113] The test vectors in the second-level test vector combination that have repeated time intervals with the third-level preset time are assigned to the third-level test vector combination. Figure 6The test vector combination in Group 1-1 is further divided into third-level test vector combinations Group 1-1-1 and Group 1-1-2, and the test vector combination in Group 2-1 is further divided into third-level test vector combinations Group 2-1-1 and Group 2-1-2; among them, the test vectors in the third-level test vector combination Group 1-1-2 all have a repeating time period of the fourth-level preset time, while the test vectors in the third-level test vector combinations Group 1-1-1, Group 2-1-1 and Group 2-1-2 do not have a repeating time period of the fourth-level preset time; Figure 6 The example uses a preset time of 300ns for the third level.
[0114] The test vectors in the third-level test vector combination that have repeated time intervals with the fourth-level preset time are divided into fourth-level test vector combinations. Figure 6 The test vector combination in Group 1-1-2 is further divided into fourth-level test vector combinations Group 1-1-2-1, Group 1-1-2-2, and Group 1-1-2-3 as examples; the test vectors in the fourth-level test vector combinations Group 1-1-2-1, Group 1-1-2-2, and Group 1-1-2-3 do not have the repetitive time period of the fifth-level preset time. Figure 6 The example uses a preset time of 400ns for the fourth level.
[0115] In another embodiment, please refer to Figure 7 This application also provides a timing simulation system, which may include: an acquisition module 10 for acquiring multiple test vectors; and a processing module 20 connected to the acquisition module 10, configured to:
[0116] Multiple test vectors are grouped to obtain multiple test vector combinations. In each test vector combination, different test vectors have both repeated time periods and different time periods.
[0117] Extract the repeated time periods of different test vectors in each test vector combination to obtain multiple extracted vectors;
[0118] Simulations are performed based on each extracted vector to obtain the corresponding initial simulation snapshot;
[0119] Based on the corresponding initial simulation snapshot, the time intervals of the differences between each test vector in each test vector combination are simulated.
[0120] The processing module 20 in the aforementioned timing simulation system groups test vectors with repetitive time periods among multiple test vectors to obtain multiple test vector combinations. Then, it extracts multiple vectors by pre-calculating the repetitive time periods of different test vectors in each test vector combination and simulates the extracted vectors. Finally, it simulates the difference time periods of each test vector in each test vector combination. In the entire simulation process, the repetitive time periods of different test vectors in the same test vector combination can be simulated at once, which greatly shortens the timing simulation time in the entire timing simulation process and significantly improves the simulation efficiency.
[0121] In one example, the test vectors acquired by the acquisition module 10 can be, but are not limited to, test vectors acquired during timing verification of the chip; specifically, the test vectors acquired by the acquisition module 10 can be test vectors acquired during full-chip timing verification of the DRAM. The test vectors can be timing waveform diagrams.
[0122] In one example, see Figure 8 The processing module 20 may include: a grouping processing unit 201, connected to the acquisition module 10, for grouping multiple test vectors to obtain multiple test vector combinations, wherein different test vectors in each test vector combination have repetitive time periods and differential time periods; an extraction unit 202, connected to the grouping processing unit 201, for extracting the repetitive time periods of different test vectors in each test vector combination to obtain multiple extracted vectors; and a simulation unit 203, connected to the grouping processing unit 201 and the extraction unit 202, for performing simulation based on each extracted vector to obtain a corresponding initial simulation snapshot, and simulating the differential time periods of each test vector in each test vector combination based on the corresponding initial simulation snapshot.
[0123] In one example, the group processing unit 201 can be configured as follows:
[0124] Compare each test vector;
[0125] Test vectors for repeated time periods with a preset start time are grouped into the same test vector combination.
[0126] Specifically, multiple test vectors can be placed in the same coordinate system from the same starting point to compare each test vector; of course, multiple test vectors can also be superimposed to compare each test vector.
[0127] Specifically, test vectors of repeating time-series waveforms with a preset time starting from the start time can be assigned to the same test vector combination. This ensures that each test vector in the same test vector combination has a repeating time period with a preset time.
[0128] In another example, the group processing unit 201 can be configured as follows:
[0129] Compare each test vector;
[0130] The test vectors of repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level;
[0131] Determine if there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time.
[0132] If so, the test vectors with repeated time periods of the second-level preset time will be assigned to the same test vector combination of the second level.
[0133] In yet another example, the group processing unit 201 can be configured as follows:
[0134] Compare each test vector;
[0135] The test vectors of repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level;
[0136] Determine if there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time.
[0137] If so, the test vectors of the repeated time periods with the second-level preset time will be assigned to the same test vector combination of the second level.
[0138] Determine if there are test vectors in the same test vector combination of the previous level that have a repeated time period with the preset time of the next level starting from the previous level; the preset time of the next level is greater than the preset time of the previous level.
[0139] If so, the test vectors with the same repeating time period of the next level preset time will be assigned to the same test vector combination of the next level.
[0140] In yet another example, the group processing unit 201 can be configured as follows:
[0141] Compare each test vector;
[0142] The test vectors of repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level;
[0143] Determine if there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time.
[0144] If so, the test vectors of the repeated time periods with the second-level preset time will be assigned to the same test vector combination of the second level.
[0145] Determine if there are test vectors in the same test vector combination of the previous level that have a repeated time period with the preset time of the next level starting from the previous level; the preset time of the next level is greater than the preset time of the previous level.
[0146] If so, the test vectors of the repeated time periods with the next level preset time will be assigned to the same test vector combination at the next level.
[0147] Repeat the process of assigning test vectors with a preset time period to the same test vector combination at the next level several times until the repeated time period in the same test vector combination at the highest level reaches the preset length.
[0148] In one example, test vectors can be grouped continuously until the longest repetition time period is reached in the highest-level combination of the same test vectors.
[0149] In one example, the difference between the preset times of each adjacent level can be the same.
[0150] In another example, the difference between the preset times of each adjacent level may not be the same. In this case, the length of the preset time of each level can be selected according to the timing waveform of the test vector.
[0151] In one example, extraction module 202 can be configured to extract the repetitive time periods of different test vectors in each highest-level test vector combination to obtain multiple extracted vectors.
[0152] If the test vectors can be divided into multi-level test vector combinations, by extracting the repetition time periods of different test vectors in the highest-level test vector combination, the maximum repetition time period range between different test vectors in each test vector combination can be obtained, thereby minimizing the subsequent simulation time.
[0153] In one example, see Figure 9 The simulation unit 203 may include: a first simulation unit 2031, which is connected to the extraction unit 202 and is used to perform simulation based on each extracted vector to obtain the corresponding initial simulation snapshot; and a second simulation unit 2032, which is connected to the group processing unit 201 and the first simulation unit 2031 and is used to simulate the difference time periods in each test vector combination.
[0154] In one example, the first simulation unit 2031 and the second simulation unit 2302 can be two independent simulators; of course, in other examples, the first simulation unit 2031 and the second simulation unit 2032 can be two independent simulation module units in the same simulator.
[0155] In one example, the test vector includes data for testing or operating the chip under test, the data including logic 1s and logic 0s.
[0156] In yet another embodiment, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement, as follows: Figures 1 to 5 The steps of the timing simulation method described in the corresponding embodiment.
[0157] In yet another embodiment, this application also provides a computer-readable storage medium having a computer program stored thereon, the computer program implementing, when executed by a processor, as follows: Figures 1 to 5 The steps of the timing simulation method described in the corresponding embodiment.
[0158] In yet another embodiment, this application also provides a computer program product, including a computer program that, when executed by a processor, implements as follows: Figures 1 to 5 The steps of the timing simulation method described in the corresponding embodiment.
[0159] In the description of this specification, references to terms such as "one embodiment," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0160] The technical features of the embodiments described above can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification.
[0161] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A timing simulation method, characterized in that, include: Obtain multiple test vectors; The test vectors are grouped to obtain multiple test vector combinations. In each test vector combination, the different test vectors have both repeated time periods and different time periods. Extract the repeated time periods of different test vectors in each of the test vector combinations to obtain multiple extracted vectors; Simulations are performed based on the extracted vectors to obtain the corresponding initial simulation snapshots; Based on the corresponding initial simulation snapshot, the time intervals of the differences between the test vectors in each of the test vector combinations are simulated.
2. The timing simulation method according to claim 1, characterized in that, The step of grouping multiple test vectors to obtain multiple test vector combinations includes: Compare each of the test vectors described; The test vectors that have a preset time interval starting from the start time are assigned to the same test vector combination.
3. The timing simulation method according to claim 2, characterized in that, The step of assigning test vectors that have a preset time interval from the start time to the same test vector combination includes: The test vectors of repeated time periods with a first-level preset time from the start time are assigned to the same test vector combination of the first level; Determine whether there are test vectors in the same test vector combination of the first level that have a repeated time period with a second-level preset time starting from the start time; the second-level preset time is greater than the first-level preset time; If so, the test vectors with repeated time periods of the second-level preset time will be assigned to the same test vector combination of the second level.
4. The timing simulation method according to claim 3, characterized in that, After assigning the test vectors of the repetitive time intervals with the second-level preset time to the same test vector combination at the second level, the method further includes: Determine whether there are test vectors in the same test vector combination of the previous level that have a repeated time period with a preset time of the next level starting from the previous level; the preset time of the next level is greater than the preset time of the previous level. If so, the test vectors with the same repeating time period of the next level preset time will be assigned to the same test vector combination of the next level.
5. The timing simulation method according to claim 4, characterized in that, After assigning test vectors with repetitive time intervals that have a preset time at the next level to the same test vector combination at the next level, it also includes: Repeat the process of assigning test vectors with a preset time period to the same test vector combination at the next level several times until the repeated time period in the same test vector combination at the highest level reaches the preset length.
6. The timing simulation method according to claim 5, characterized in that, The difference between the preset times of each adjacent level is the same.
7. The timing simulation method according to claim 5, characterized in that, The step of extracting the repetitive time periods of different test vectors in each of the test vector combinations to obtain multiple extracted vectors includes: Extract the repetitive time periods of different test vectors in each highest-level test vector combination to obtain multiple extracted vectors.
8. The timing simulation method according to any one of claims 1 to 7, characterized in that, The test vector includes data used to test or operate the chip under test, and the data includes logic 1 and logic 0.
9. The timing simulation method according to any one of claims 1 to 7, characterized in that, The step of performing simulation based on each of the extracted vectors to obtain the corresponding initial simulation snapshot includes: inputting each of the extracted vectors into the simulator, wherein the simulator is used to perform simulation based on the input extracted vectors and output the initial simulation snapshot; The step of simulating the difference time periods of each test vector in each test vector combination based on the corresponding initial simulation snapshot includes: inputting the initial simulation snapshot and the difference time periods of each test vector in each test vector combination into the simulator, and the simulator is further used to perform simulation based on the input difference time periods of the test vectors and the initial simulation snapshot, and output simulation results.
10. A timing simulation system, characterized in that, include: The acquisition module is used to acquire multiple test vectors; A processing module, connected to the acquisition module, is configured to: The test vectors are grouped to obtain multiple test vector combinations. In each test vector combination, the different test vectors have both repeated time periods and different time periods. Extract the repeated time periods of different test vectors in each of the test vector combinations to obtain multiple extracted vectors; Simulations are performed based on the extracted vectors to obtain the corresponding initial simulation snapshots; Based on the corresponding initial simulation snapshot, the time intervals of the differences between the test vectors in each of the test vector combinations are simulated.
11. The timing simulation system according to claim 10, characterized in that, The processing module includes: A grouping processing unit, connected to the acquisition module, is used to group multiple test vectors to obtain multiple test vector combinations. In each test vector combination, different test vectors have repetitive time periods and different time periods. An extraction unit, connected to the grouping processing unit, is used to extract the repetitive time periods of different test vectors in each test vector combination to obtain multiple extracted vectors. The simulation unit, connected to the grouping processing unit and the extraction unit, is used to perform simulation based on each of the extracted vectors to obtain the corresponding initial simulation snapshot, and to simulate the time difference of each of the test vectors in each combination of test vectors based on the corresponding initial simulation snapshot.
12. The timing simulation system according to claim 11, characterized in that, The simulation unit includes: The first simulation unit is connected to the extraction unit and is used to perform simulation based on each of the extraction vectors to obtain the corresponding initial simulation snapshot. The second simulation unit, connected to the group processing unit and the first simulation unit, is used to simulate the difference time periods in each of the test vector combinations.
13. The timing simulation system according to any one of claims 10 to 12, characterized in that, The test vector includes data used to test or operate the chip under test, and the data includes logic 1 and logic 0.
14. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the timing simulation method as described in any one of claims 1 to 9.
15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the timing simulation method as described in any one of claims 1 to 9.
16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the timing simulation method as described in any one of claims 1 to 9.
Citation Information
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Calculation multiplexing method, device and system for accelerating circuit simulation in circuit trimming
CN102411663A