Pad layout method and device of qubit layout, electronic equipment and medium

Abstract

The present application provides a pad layout method and device for a quantum bit layout, electronic equipment and medium, which can solve the problem of low efficiency and easy error in related art manual drawing of pads, can automatically draw pads, and can improve the efficiency and accuracy of layout drawing. The method comprises: determining a limiting frame outside a plurality of ion implantation layers; determining a corresponding first insertion point on the limiting frame according to the edge of each ion implantation layer closest to the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers; determining a second insertion point at other positions on the limiting frame except the first insertion point; wherein the sum of the number of first insertion points and the number of second insertion points is consistent with the number of conductive discs; generating a pad for connecting the conductive disc and the wire crossing the ion implantation layer at the first insertion point, and generating a pad for connecting the conductive disc and the wire not crossing the ion implantation layer at the second insertion point.

Description

Technical Field

[0001] This application relates to the field of circuit design, and in particular to a method, apparatus, electronic device, and medium for pad layout of quantum bit patterns. Background Technology

[0002] Quantum bits are the key unit of quantum chips. Due to the extremely small size of the electrodes on a qubit, it is difficult to solder them in the manufacturing process. Transmission lines are needed to lead the electrodes to larger pads, and these transmission lines are typically zigzag lines. However, because the transmission lines are very thin, breaks can easily occur at the bends during fabrication. Therefore, conductive pads need to be fabricated at the bends to improve the conductivity reliability of the transmission lines.

[0003] However, there are a large number of pads on a qubit, and each pad has a transmission line. In the design of the qubit layout, the pads need to be added manually step by step. Therefore, the layout drawing workload is very large, the layout drawing efficiency is very low, and the drawing process cannot guarantee accuracy and is prone to errors. Summary of the Invention

[0004] The purpose of this application is to provide a method, apparatus, medium, and device for pad layout of quantum bit patterns, in order to solve the problems of low efficiency and easy error in manual pad drawing in related technologies, and to automatically draw pads, thereby improving the efficiency and accuracy of layout drawing.

[0005] To address the aforementioned technical problems, in a first aspect, this application provides a method for pad layout of a quantum bit pattern, wherein the quantum bit pattern includes a conductive disk and multiple ion implantation layers located around the conductive disk, and the method includes:

[0006] A limiting frame is defined around the plurality of ion implantation layers;

[0007] Based on the edge of each ion implantation layer that is closest to the limiting frame, a corresponding first insertion point is determined on the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers;

[0008] A second insertion point is determined at a position other than the first insertion point on the limiting frame; wherein the sum of the number of the first insertion point and the number of the second insertion point is consistent with the number of the conductive disks;

[0009] A pad for connecting the conductive disk and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting the conductive disk and whose trace does not cross the ion implantation layer is generated at the second insertion point.

[0010] Optionally, determining a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer closest to the limiting frame includes:

[0011] Select any point as a reference point on the edge of each ion implantation layer that is closest to the limiting frame;

[0012] Find the intersection point of the perpendicular line from each reference point to the limiting frame and the limiting frame, and use the intersection point as the first insertion point.

[0013] Optionally, the limiting frame is a rectangle, the ion implantation layer includes a rectangular implantation region, and the reference point is a vertex of the rectangular implantation region.

[0014] Optionally, finding the intersection point of the perpendicular line from each reference point to the limiting frame and the limiting frame, and using the intersection point as the first insertion point, includes:

[0015] Determine the rectangular side containing the vertex that serves as the reference point; wherein, the side of the rectangular injection region closest to the limiting frame is perpendicular to the rectangular side containing the vertex;

[0016] Extend the rectangle containing the vertex toward the limiting frame to intersect the limiting frame to determine the intersection point, and use the intersection point as the first insertion point.

[0017] Optionally, the conductive pad includes a first conductive pad and a second conductive pad, the second conductive pad being located between two adjacent first conductive pads, the first conductive pad being used to connect to the pad generated at the first insertion point, and the second conductive pad being used to connect to the pad generated at the second insertion point;

[0018] Determining the second insertion point at a location other than the first insertion point on the limiting frame includes:

[0019] The number of second insertion points between two adjacent first insertion points is determined based on the number of second conductive disks between two adjacent first conductive disks; wherein, two adjacent first insertion points correspond to two adjacent first conductive disks.

[0020] The second insertion point is determined on the limiting frame segment between two adjacent first insertion points based on the number of second insertion points between two adjacent first insertion points; wherein the second insertion points are spaced apart on the limiting frame segment.

[0021] Optionally, the line connecting the second insertion point between two adjacent first insertion points to the center point of the qubit layout divides the fan-shaped region formed by the two adjacent first insertion points and the center point of the qubit layout into equal angles.

[0022] Optionally, the pad is rectangular, and the center point of the pad is either the first insertion point or the second insertion point.

[0023] Secondly, a pad layout apparatus for a quantum bit layout is provided, the quantum bit layout including a conductive pad and a plurality of ion implantation layers located around the conductive pad. The apparatus includes:

[0024] The first determining module is used to determine a limiting frame around the plurality of ion implantation layers;

[0025] The second determining module is used to determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers;

[0026] The third determining module is used to determine a second insertion point at a position other than the first insertion point on the limiting frame; wherein the sum of the number of the first insertion point and the number of the second insertion point is consistent with the number of the conductive disks;

[0027] The pattern generation module is used to generate pads at the first insertion point for connecting the conductive disk and whose traces cross the ion implantation layer, and to generate pads at the second insertion point for connecting the conductive disk and whose traces do not cross the ion implantation layer.

[0028] Optionally, the second determining module includes:

[0029] The selection unit is used to select any point as a reference point on the edge of each ion implantation layer that is closest to the limiting frame.

[0030] The search unit is used to find the intersection point of the perpendicular line from each reference point to the limit frame and the limit frame, and to use the intersection point as the first insertion point.

[0031] Optionally, the limiting frame is a rectangle, the ion implantation layer includes a rectangular implantation region, and the reference point is a vertex of the rectangular implantation region.

[0032] Optionally, the search unit is further configured to:

[0033] Determine the rectangular side containing the vertex that serves as the reference point; wherein, the side of the rectangular injection region closest to the limiting frame is perpendicular to the rectangular side containing the vertex;

[0034] Extend the rectangle containing the vertex toward the limiting frame to intersect the limiting frame to determine the intersection point, and use the intersection point as the first insertion point.

[0035] Optionally, the conductive pad includes a first conductive pad and a second conductive pad, the second conductive pad being located between two adjacent first conductive pads, the first conductive pad being used to connect to the pad generated at the first insertion point, and the second conductive pad being used to connect to the pad generated at the second insertion point;

[0036] The third determining module includes:

[0037] The first determining unit is configured to determine the number of second insertion points between two adjacent first insertion points based on the number of second conductive disks between two adjacent first conductive disks; wherein, two adjacent first insertion points correspond to two adjacent first conductive disks.

[0038] The second determining unit is used to determine the second insertion point on the limiting frame segment between two adjacent first insertion points based on the number of second insertion points between two adjacent first insertion points; wherein the second insertion points are spaced apart on the limiting frame segment.

[0039] Optionally, the line connecting the second insertion point between two adjacent first insertion points to the center point of the qubit layout divides the fan-shaped region formed by the two adjacent first insertion points and the center point of the qubit layout into equal angles.

[0040] Optionally, the pad is rectangular, and the center point of the pad is either the first insertion point or the second insertion point.

[0041] Thirdly, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the pad layout method for a quantum bit layout as described in any of the first aspects above.

[0042] Fourthly, a storage medium is provided, wherein a computer program is stored therein, wherein the computer program is configured to execute, at runtime, the pad layout method for a quantum bit layout as described in any of the first aspects above.

[0043] Fifthly, a quantum computer operating system is provided, wherein the quantum computer operating system realizes the pad layout of the quantum bit layout according to the method described in any one of the first aspects above.

[0044] In a sixth aspect, a quantum computer is provided, the quantum computer comprising the quantum computer operating system described in the fifth aspect above.

[0045] Based on the above-mentioned pad layout method for qubit layouts, this application targets qubit layouts with conductive pads and ion implantation layers. First, a limiting frame is determined around the ion implantation layer. Based on the edge of each ion implantation layer closest to the limiting frame, a corresponding first insertion point is determined on the limiting frame. Then, a second insertion point is determined on the limiting frame. Finally, a pad for connecting the conductive pad and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting the conductive pad and whose trace does not cross the ion implantation layer is generated at the second insertion point. This completes the pad drawing. The entire drawing process only requires manual setting of the limiting frame size, thus enabling automatic pad drawing and improving the efficiency and accuracy of layout drawing.

[0046] The pad layout apparatus, storage medium, and electronic device for quantum bit layout provided in this application belong to the same inventive concept as the pad layout method for quantum bit layout, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description

[0047] Figure 1 This is a schematic flowchart of a method for pad layout of a quantum bit pattern provided in an exemplary embodiment of this application;

[0048] Figure 2 A schematic diagram of a quantum bit layout provided for an exemplary embodiment of this application;

[0049] Figure 3 for Figure 1 A schematic diagram of the limiting frame determined by the pad layout method shown;

[0050] Figure 4 for Figure 1 A schematic diagram showing the first and second insertion points determined by the pad layout method shown.

[0051] Figure 5 for Figure 1 A schematic diagram of the pads generated by the pad layout method shown;

[0052] Figure 6 A schematic block diagram of a pad layout device for a quantum bit layout provided as an exemplary embodiment of this application. Detailed Implementation

[0053] The specific embodiments of this application will be described in more detail below with reference to the schematic diagrams. The advantages and features of this application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.

[0054] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0056] This application first provides a method for pad layout of a quantum bit pattern, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers and quantum computers. The quantum bit pattern includes an electrode structure, conductive disks surrounding the electrode structure, and multiple ion implantation layers surrounding the conductive disks. The electrode structure includes multiple first electrodes for introducing charge carriers and multiple second electrodes for controlling the quantum bits, with the number of first electrodes and ion implantation layers being equal. The conductive disk includes a first conductive disk and a second conductive disk, with the first conductive disk connected to the first electrode and the second conductive disk connected to the second electrode. The first and second conductive disks form an inner confinement frame, within which the electrode structure is located.

[0057] Please refer to Figure 2 In one specific example, the qubit layout includes six ion-implanted layers 21, 22, 23, 24, 25, and 26, six first conductive disks 11, and 21 second conductive disks 12. The six first conductive disks 11 and the 21 second conductive disks 12 are located on an inner confinement frame 10, which holds the electrode structure ( Figure 2 (Not shown) Enclosed within it. The ion implantation layer has a polygonal structure, consisting of a cone-shaped (quadrilateral implantation region) and a rectangle (rectangular implantation region). Figure 2 In the middle, ion implantation layers 21, 22, 23, and 24 are heptagonal, while ion implantation layers 25 and 26 are octagonal.

[0058] The following is a further description of a method for pad layout of a quantum bit pattern provided by an embodiment of the present invention.

[0059] See Figure 1 , Figure 1This is a schematic flowchart of a method for pad layout of a quantum bit pattern according to an exemplary embodiment of this application, including steps S11 to S14, wherein:

[0060] S11, a limiting frame is defined around the plurality of ion implantation layers.

[0061] Among them, in conjunction with reference Figure 3 The limiting frame 30 is located around 21, 22, 23, 24, 25, and 26. Once the limiting frame 30 is determined, the ion implantation layers 21, 22, 23, 24, 25, and 26, the first conductive disk 11, and the second conductive disk 12 are located within the limiting frame 30. The limiting frame 30 can be manually drawn by the user, provided by the quantum bit layout, or generated based on user-input parameters. For example, the user inputs the number of sides of the limiting frame and the length of each side, and then connects each side sequentially according to a preset order to determine the limiting frame.

[0062] The limiting frame can be a polygonal border of any shape composed of line segments. Generally speaking, the number of sides of the polygonal border should be minimized. In this embodiment, the limiting frame is a rectangle.

[0063] After determining the limiting frame around the plurality of ion implantation layers, step S12 is executed.

[0064] S12, determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame.

[0065] The number of first insertion points is equal to the number of ion-implanted layers, and the first conductive pad is used to connect to the pads generated at the first insertion points. Regardless of the shape of the ion-implanted layer, there will always be one edge closest to the limiting frame. (Combined with...) Figure 4 As shown, the edge of each ion implantation layer closest to the limiting frame 30 is the edge of the rectangular implantation region. Based on the edge of each ion implantation layer closest to the limiting frame, six first insertion points A can be determined on the limiting frame.

[0066] Optionally, step S12 may include the following steps:

[0067] S121, select any point as a reference point on the edge of each ion implantation layer that is closest to the limiting frame.

[0068] Combination Figure 4 As shown, the rectangular implantation region of the ion implantation layer 21 includes vertices b, c, and d. The edge with vertices c and d as endpoints is closest to the limiting frame 30. Any point on the edge with vertices c and d as endpoints can be selected as a reference point.

[0069] S122, find the intersection point of the perpendicular line from each reference point to the limiting frame and the limiting frame, and use the intersection point as the first insertion point.

[0070] Taking vertex c as the reference point as an example, combined with Figure 4 As shown, firstly, the side of the rectangle containing vertex c, which serves as the reference point, is determined. This side of the rectangle containing vertex c is perpendicular to the side of the rectangular injection area that is closest to the limiting frame 30. Then, the side of the rectangle containing vertex c is extended towards the limiting frame 30 to intersect with the limiting frame 30 to determine the intersection point. This intersection point is then used as the first insertion point A.

[0071] The rectangle containing vertex c has two sides: one with vertex c and vertex d as endpoints, and the other with vertex c and vertex b as endpoints. The side with vertex c and vertex d as endpoints is closest to the limiting frame 30, and the side with vertex c and vertex b as endpoints is perpendicular to the side with vertex c and vertex d as endpoints. Therefore, the side with vertex c and vertex b as endpoints is selected, and then this side is extended towards the limiting frame 30 to intersect with the limiting frame 30. The intersection point is the first insertion point A.

[0072] After determining a corresponding first insertion point on the limiting frame, step S13 is executed.

[0073] S13, determine a second insertion point at a position other than the first insertion point on the limiting frame.

[0074] The sum of the number of the first insertion point and the number of the second insertion point is the same as the number of the conductive pads. Furthermore, the second conductive pad is used to connect to the pads generated at the second insertion point.

[0075] Optionally, step S13 may include the following steps:

[0076] S131, determine the number of second insertion points between two adjacent first insertion points based on the number of second conductive disks between two adjacent first conductive disks. Wherein, two adjacent first insertion points correspond to two adjacent first conductive disks.

[0077] S132, based on the number of second insertion points between two adjacent first insertion points, determine the second insertion points on the limiting frame segment between two adjacent first insertion points. The second insertion points are spaced apart on the limiting frame segment.

[0078] Reference Figure 4The six first insertion points A divide the limiting frame into six limiting frame segments. Twenty-one second insertion points B can be determined in the empty spaces on the limiting frame according to a set rule. These 21 second insertion points B are distributed across different limiting frame segments, with each second insertion point B spaced at intervals within each segment. Figure 4 In the diagram, all points except the first insertion point A are the second insertion point B.

[0079] Determining the second insertion point B between the first insertion points A corresponding to ion implantation layers 21 and 24 may include the following steps:

[0080] First, determine the first conductive pads 11 corresponding to ion implantation layers 21 and 24, respectively. That is, determine the first conductive pads corresponding to two adjacent ion implantation layers. Regardless of the shape of the ion implantation layer, there must be an edge that is closest to the inner layer limiting frame 10. Combined with... Figure 4 As shown, the edge of each ion implantation layer closest to the inner layer limiting frame 10 is the shortest side of the cone-shaped region. The first conductive disk 11 corresponding to each ion implantation layer can be determined based on the shortest side of each ion implantation layer. For example, the first conductive disk closest to the shortest side of the ion implantation layer from the inner layer limiting frame is taken as the first conductive disk corresponding to that ion implantation layer.

[0081] Next, the number of second conductive disks 12 between the first conductive disks 11 corresponding to ion implantation layer 21 and the first conductive disks 11 corresponding to ion implantation layer 24 is determined. That is, the number of second conductive disks between the first conductive disks corresponding to two adjacent ion implantation layers is determined. Combined with... Figure 4 As shown, the number of second conductive disks 12 between the first conductive disk 11 corresponding to the ion implantation layer 21 and the first conductive disk 11 corresponding to the ion implantation layer 24 is 1.

[0082] Next, the number of second insertion points B between the first insertion point A corresponding to ion implantation layer 21 and the first insertion point A corresponding to ion implantation layer 24 is determined. That is, the number of second insertion points between the first insertion points of adjacent ion implantation layers is determined. If the number of second conductive disks 12 between the first conductive disks 11 corresponding to ion implantation layer 21 and the first conductive disks 11 corresponding to ion implantation layer 24 is 1, then the number of second insertion points B between the first insertion point A corresponding to ion implantation layer 21 and the first insertion point A corresponding to ion implantation layer 24 is 1. If the number of second conductive disks 12 between the first conductive disks 11 corresponding to ion implantation layer 21 and the first conductive disks 11 corresponding to ion implantation layer 22 is 11, then the number of second insertion points B between the first insertion point A corresponding to ion implantation layer 21 and the first insertion point A corresponding to ion implantation layer 22 is 11.

[0083] Finally, a second insertion point B is provided between the first insertion point A corresponding to ion implantation layer 21 and the first insertion point A corresponding to ion implantation layer 24. The second insertion point B can be provided at equal intervals between the first insertion points A corresponding to ion implantation layer 21 and the first insertion point A corresponding to ion implantation layer 24, or it can be provided at unequal intervals between the two first insertion points A.

[0084] Optionally, for cases where there are two or more second insertion points on a limiting frame segment, as a preferred embodiment, the line connecting the corresponding second insertion point on each limiting frame segment to the center point of the qubit layout divides the fan-shaped region formed by the first insertion point on the current limiting frame segment and the center point of the qubit layout into equal angles. For example... Figure 4 As shown, there are 13 points in total, including the two first insertion points A and the 11 second insertion points B on the rightmost limiting frame segment. The angle between any two adjacent lines connecting these 13 points to the center point of the electrode structure is equal.

[0085] After determining the second insertion point at a position other than the first insertion point on the limiting frame, step S14 is executed.

[0086] S14, a pad for connecting the conductive disk and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting the conductive disk and whose trace does not cross the ion implantation layer is generated at the second insertion point.

[0087] Optionally, the pad is rectangular, and the center point of the pad is either the first insertion point or the second insertion point.

[0088] Among them, in conjunction with reference Figure 5 The first insertion point A generates the first pad 31, and the second insertion point B generates the second pad 32. The transmission line between the first pad 31 and the first conductive pad 11 needs to cross the corresponding ion implantation layer, while the transmission line between the second pad 32 and the second conductive pad 12 does not cross the ion implantation layer.

[0089] Based on the above-mentioned pad layout method for qubit layouts, this application targets qubit layouts with conductive pads and ion implantation layers. First, a limiting frame is determined around the ion implantation layer. Based on the edge of each ion implantation layer closest to the limiting frame, a corresponding first insertion point is determined on the limiting frame. Then, a second insertion point is determined on the limiting frame. Finally, a pad for connecting the conductive pad and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting the conductive pad and whose trace does not cross the ion implantation layer is generated at the second insertion point. This completes the pad drawing. The entire drawing process only requires manual setting of the limiting frame size, thus enabling automatic pad drawing and improving the efficiency and accuracy of layout drawing.

[0090] The above combination Figure 1 The method for pad layout of a quantum bit layout provided in the embodiments of this application is described in detail. The apparatus for implementing the method for pad layout of a quantum bit layout provided in the embodiments of this application is described in detail below with reference to section 6.

[0091] For example, see Figure 6 , Figure 6 A schematic block diagram of a pad layout apparatus for a quantum bit layout provided as an exemplary embodiment of this application, and... Figure 1 Corresponding to the process shown, the qubit layout pad patterning device 600 includes:

[0092] The first determining module 610 is used to determine a limiting frame around the plurality of ion implantation layers;

[0093] The second determining module 620 is used to determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers;

[0094] The third determining module 630 is used to determine a second insertion point at a position other than the first insertion point on the limiting frame; wherein the sum of the number of the first insertion point and the number of the second insertion point is consistent with the number of the conductive disks;

[0095] The pattern generation module 640 is used to generate pads at the first insertion point for connecting the conductive disk and whose traces cross the ion implantation layer, and to generate pads at the second insertion point for connecting the conductive disk and whose traces do not cross the ion implantation layer.

[0096] Optionally, the second determining module 620 includes:

[0097] The selection unit is used to select any point as a reference point on the edge of each ion implantation layer that is closest to the limiting frame.

[0098] The search unit is used to find the intersection point of the perpendicular line from each reference point to the limit frame and the limit frame, and to use the intersection point as the first insertion point.

[0099] Optionally, the limiting frame is a rectangle, the ion implantation layer includes a rectangular implantation region, and the reference point is a vertex of the rectangular implantation region.

[0100] Optionally, the search unit is further configured to:

[0101] Determine the rectangular side containing the vertex that serves as the reference point; wherein, the side of the rectangular injection region closest to the limiting frame is perpendicular to the rectangular side containing the vertex;

[0102] Extend the rectangle containing the vertex toward the limiting frame to intersect the limiting frame to determine the intersection point, and use the intersection point as the first insertion point.

[0103] Optionally, the conductive pad includes a first conductive pad and a second conductive pad, the second conductive pad being located between two adjacent first conductive pads, the first conductive pad being used to connect to the pad generated at the first insertion point, and the second conductive pad being used to connect to the pad generated at the second insertion point;

[0104] The third determining module 630 includes:

[0105] The first determining unit is configured to determine the number of second insertion points between two adjacent first insertion points based on the number of second conductive disks between two adjacent first conductive disks; wherein, two adjacent first insertion points correspond to two adjacent first conductive disks.

[0106] The second determining unit is used to determine the second insertion point on the limiting frame segment between two adjacent first insertion points based on the number of second insertion points between two adjacent first insertion points; wherein the second insertion points are spaced apart on the limiting frame segment.

[0107] Optionally, the line connecting the second insertion point between two adjacent first insertion points to the center point of the qubit layout divides the fan-shaped region formed by the two adjacent first insertion points and the center point of the qubit layout into equal angles.

[0108] Optionally, the pad is rectangular, and the center point of the pad is either the first insertion point or the second insertion point.

[0109] This application also provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0110] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing the following steps:

[0111] S11, define a limiting frame around multiple ion implantation layers.

[0112] S12, determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame.

[0113] S13, determine a second insertion point at a position other than the first insertion point on the limiting frame.

[0114] S14, a pad for connecting a conductive disk and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting a conductive disk and whose trace does not cross the ion implantation layer is generated at the second insertion point.

[0115] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0116] This application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0117] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0118] Specifically, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0119] S11, define a limiting frame around multiple ion implantation layers.

[0120] S12, determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame.

[0121] S13, determine a second insertion point at a position other than the first insertion point on the limiting frame.

[0122] S14, a pad for connecting a conductive disk and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting a conductive disk and whose trace does not cross the ion implantation layer is generated at the second insertion point.

[0123] Optionally, the electronic device may have one or more processors. The processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor, implemented by reading software code stored in memory.

[0124] Optionally, the electronic device may contain one or more memories. The memory may be integrated with the processor or disposed separately from it; this application does not limit this. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or disposed separately on different chips. This application does not specifically limit the type of memory or the arrangement of the memory and processor.

[0125] For example, the electronic device may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0126] It should be understood that the processor in the embodiments of this application can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0127] It should also be understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0128] This application also provides a quantum computer operating system, which implements the pad layout of the quantum bit layout according to any of the above-described method embodiments provided in this application.

[0129] Embodiments of this application also provide a quantum computer, which includes the quantum computer operating system described above.

[0130] The above embodiments can be implemented, in whole or in part, by software, hardware (such as circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0131] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0132] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0133] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0134] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0135] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0136] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0137] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0138] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0139] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0140] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for pad layout in a quantum bit pattern, characterized in that, The quantum bit layout includes a conductive disk and multiple ion implantation layers located around the conductive disk. The method includes: A limiting frame is defined around the plurality of ion implantation layers; Based on the edge of each ion implantation layer that is closest to the limiting frame, a corresponding first insertion point is determined on the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers; A second insertion point is determined at a position other than the first insertion point on the limiting frame; wherein the sum of the number of the first insertion point and the number of the second insertion point is consistent with the number of the conductive disks; A pad for connecting the conductive disk and whose trace crosses the ion implantation layer is generated at the first insertion point, and a pad for connecting the conductive disk and whose trace does not cross the ion implantation layer is generated at the second insertion point.

2. The method according to claim 1, characterized in that, The step of determining a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame includes: Select any point as a reference point on the edge of each ion implantation layer that is closest to the limiting frame; Find the intersection point of the perpendicular line from each reference point to the limiting frame and the limiting frame, and use the intersection point as the first insertion point.

3. The method according to claim 2, characterized in that, The limiting frame is a rectangle, the ion implantation layer includes a rectangular implantation region, and the reference point is a vertex of the rectangular implantation region.

4. The method according to claim 3, characterized in that, The step of finding the intersection point of the perpendicular line from each reference point to the limiting frame and the limiting frame, and using the intersection point as the first insertion point, includes: Determine the rectangular side containing the vertex that serves as the reference point; wherein, the side of the rectangular injection region closest to the limiting frame is perpendicular to the rectangular side containing the vertex; Extend the rectangle containing the vertex toward the limiting frame to intersect the limiting frame to determine the intersection point, and use the intersection point as the first insertion point.

5. The method according to any one of claims 1-4, characterized in that, The conductive pad includes a first conductive pad and a second conductive pad, the second conductive pad being located between two adjacent first conductive pads. The first conductive pad is used to connect to the pad generated at the first insertion point, and the second conductive pad is used to connect to the pad generated at the second insertion point. Determining the second insertion point at a location other than the first insertion point on the limiting frame includes: The number of second insertion points between two adjacent first insertion points is determined based on the number of second conductive disks between two adjacent first conductive disks; wherein, two adjacent first insertion points correspond to two adjacent first conductive disks. The second insertion point is determined on the limiting frame segment between two adjacent first insertion points based on the number of second insertion points between two adjacent first insertion points; wherein the second insertion points are spaced apart on the limiting frame segment.

6. The method according to claim 5, characterized in that, The line connecting the second insertion point between two adjacent first insertion points to the center point of the qubit layout divides the fan-shaped region formed by the two adjacent first insertion points and the center point of the qubit layout into equal angles.

7. The method according to claim 1, characterized in that, The pad is rectangular, and the center point of the pad is either the first insertion point or the second insertion point.

8. A pad layout device for a quantum bit layout, characterized in that, The quantum bit layout includes a conductive disk and multiple ion implantation layers located around the conductive disk; the device includes: The first determining module is used to determine a limiting frame around the plurality of ion implantation layers; The second determining module is used to determine a corresponding first insertion point on the limiting frame based on the edge of each ion implantation layer that is closest to the limiting frame; wherein the number of first insertion points is equal to the number of ion implantation layers; The third determining module is used to determine a second insertion point at a position other than the first insertion point on the limiting frame; wherein the sum of the number of the first insertion point and the number of the second insertion point is consistent with the number of the conductive disks; The pattern generation module is used to generate pads at the first insertion point for connecting the conductive disk and whose traces cross the ion implantation layer, and to generate pads at the second insertion point for connecting the conductive disk and whose traces do not cross the ion implantation layer.

9. An electronic device, characterized in that, It includes a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the pad layout method for a quantum bit layout according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a computer program or instructions that, when executed on a computer, cause the computer to perform a pad layout method for a quantum bit layout as described in any one of claims 1-7.

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