Apparatus and method for supporting variable exponent bit-width multi-precision posit encoding and decoding operations

Abstract

The application provides a multi-precision Posit coding and decoding operation device and method supporting variable exponent bit width, the device comprising a multi-precision Posit decoder, a multi-precision Posit operation unit and a multi-precision Posit encoder; the multi-precision Posit decoder receives Posit input data, a precision mode control signal and an exponent bit width es configuration signal, completes a decoding operation and obtains valid sign, exponent and mantissa value outputs; the multi-precision Posit operation unit completes corresponding operations and sends operation results to the multi-precision Posit encoder, and the multi-precision Posit encoder completes encoding of Posit output data. The application realizes dynamic configuration of the exponent bit width at runtime, can simultaneously support the advantages of large dynamic range and high numerical precision of the Posit format in the same hardware, and simultaneously realizes efficient multi-precision Posit coding and decoding operation of hardware.

Description

TECHNICAL FIELD

[0001] The present application relates to a multi-precision Posit encoding and decoding operation device and method supporting variable exponent bit width. BACKGROUND

[0002] The Posit format (Reference: Gustafson J L, Yonemoto I T. Beating floating point at its own game: Posit arithmetic[J]. Supercomputing frontiers and innovations, 2017, 4(2): 71-86.) has attracted extensive attention from academia and industry since its proposal, and has been proven to have potential advantages in some neural network applications: that is, using low-precision Posit format instead of high-precision traditional floating-point format, while reducing the computational complexity and storage requirements, the model accuracy can also remain unchanged. This is due to the balance between dynamic range and numerical precision of the Posit format, and the dynamically configurable exponent bit width es makes this balance more flexible (the larger the exponent bit width es, the more biased to large dynamic range; the smaller the exponent bit width es, the more biased to high numerical precision), which greatly improves the flexibility of Posit operation.

[0003] On the other hand, the computational precision of different network layers and operations in neural network applications is often different. By implementing flexible precision configuration in operation, not only can the computational efficiency be greatly improved and the energy consumption be reduced, but also the parameter storage requirement of neural network can be reduced under low-precision operation. However, due to the unique regime field of the Posit format, its encoding and decoding process is more complex than that of the traditional floating-point format. If various precision Posit encoding and decoding units are implemented in hardware at the same time, it will greatly increase the hardware overhead and increase the cost of Posit operation. Therefore, implementing a hardware-efficient multi-precision Posit encoding and decoding unit can better meet the neural network operation based on the Posit format.

[0004] The documents "Wang Zhongfeng, Xu Mingyang, Fang Chao, et al. Floating point multiplication operation circuit based on posit data format [P]. Jiangsu Province: CN111290732B, 2023-03-14." and "Liang Feng, Wu Bin, Zhang Guohuo, et al. A posit floating point operation processor and operation processing system [P]. Shaanxi Province: CN111538472B, 2022-11-04." propose multiplication, addition and other operation circuits based on the Posit format, which involve encoding and decoding of Posit data, but only support single-precision and fixed exponent bit width Posit encoding and decoding. The paper "Zhang H, Ko S B. Efficient multiple-precision posit multiplier [C] / / 2021 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2021: 1-5." proposes a multiplier that supports multiple-precision Posit operations, but still fixes the size of the exponent bit width at each precision. The Posit multiply-accumulate operation unit proposed in the paper "Neves N, Tomas P, Roma N. Dynamic fused multiply-accumulate posit unit with variable exponent size for low-precision DSP applications [C] / / 2020 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2020: 1-6." supports variable exponent bit width, but does not provide an efficient multiple-precision operation solution. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a multiple-precision Posit encoding and decoding operation device and method that supports variable exponent bit width to overcome the shortcomings of the prior art.

[0006] The multiple-precision Posit decoder receives Posit input data, precision mode control signals and exponent bit width es configuration signals, performs decoding operations and obtains valid sign, exponent and mantissa value outputs.

[0007] The multi-precision Posit operation unit completes corresponding operation according to the obtained effective sign, exponent and mantissa value, and sends the operation result to the multi-precision Posit encoder, and the multi-precision Posit encoder completes encoding of the Posit output data according to the precision mode control signal and the exponent bit width es configuration signal.

[0008] The multi-precision Posit decoder includes a multi-precision two's complement module, a multi-precision leading 0 / 1 count module, a multi-precision regime shift module and a multi-precision mask to exponent mantissa module.

[0009] The multi-precision two's complement module realizes multi-precision two's complement operation by using a segmented method, specifically including: first, dividing the input operand into N segments of sub-operand according to the supported lowest precision mode (where N is the bit width of the input operand divided by the bit width of the supported lowest precision mode, for example, the input bit width is 32-bit value, and the bit width of the supported lowest precision mode is 8-bit, then N = 32 / 8 = 4), that is, sub-operand 0 to sub-operand N-1, and determining the effective sign of each segment of sub-operand according to the precision mode control signal, completing all bit inversion operation for negative numbers and all bit unchanged operation for positive numbers through exclusive or operation of the sub-operand and the corresponding effective sign, determining whether the result after exclusive or operation needs to be added 1 according to the precision mode control signal, the effective sign of the sub-operand and the carry generated by the low bit, finally, splicing the obtained N segments of sub-result, and performing or operation of the sign bit and the effective sign value according to the precision mode control signal to obtain the value after multi-precision two's complement operation.

[0010] The multi-precision leading 0 / 1 counting module adopts a segmented counting method, and the counting result in a low-precision mode is processed by an adder and a selector to obtain a counting result in a high-precision mode. Specifically, the operand to be processed is divided into N segments of sub-operands (where N is the bit width of the operand to be processed divided by the bit width of the supported lowest-precision mode) according to the supported lowest precision, i.e., sub-operand 0 to sub-operand N-1. N groups of parallel leading 0 / 1 counting modules are used to calculate the respective leading 0 or 1 numbers of the N groups of sub-operands, which are respectively cpm[0] to cpm[N-1], and the respective data valid signals of the N groups of sub-operands, which are respectively vpm[0] to vpm[N-1]. When the data valid signal vpm is 1, cpm is the exact leading 0 or leading 1 number. Otherwise, when the data valid signal vpm is 0, it represents that the sub-operand input is all 0 or all 1, and cpm is 0 at this time. Cpm is the leading 0 / 1 number of the sub-operand, and there are N groups, i.e., cpm[0] is the leading 0 / 1 number of sub-operand 0. Similarly, cpm[1], cpm[2], …, cpm[N-1] are respectively the leading 0 / 1 numbers of sub-operand 1 to sub-operand N-1. Vpm is the data valid signal of the sub-operand, and there are N groups, i.e., vpm[0] is the data valid signal of sub-operand 0. Similarly, vpm[1], vpm[2], …, vpm[N-1] are respectively the data valid signals of sub-operand 1 to sub-operand N-1.

[0011] When the precision mode control signal is the supported lowest precision, cpm[0] to cpm[N-1] are the required leading 0 / 1 counting results. Otherwise, the counting results of every two adjacent segments of sub-operands are processed by step-by-step two-by-two combination to obtain the counting results of the next precision mode.

[0012] The multi-precision regime shift module supports multi-precision shift by using a segmented and hierarchical shift method, and specifically includes: dividing the operand into N sub-operands (where N is the value of the bit width of the operand divided by the bit width of the lowest precision mode supported) according to the lowest precision mode supported, i.e., sub-operand 0 to sub-operand N-1, and determining the left shift amount of each sub-operand according to a precision mode control signal; in the lowest precision mode supported, the maximum shift amount of each sub-operand is the bit width of the sub-operand, which is stored in a number of L bits, where L is the value obtained by performing log2 operation on the bit width of the sub-operand; in the highest precision mode supported, the maximum shift amount is the total bit width of the operand, which is stored in a number of K bits, where K is the value obtained by performing log2 operation on the total bit width of the operand; performing segmented and hierarchical shift, and sending the N sub-operands into respective shifters in parallel to complete 1-L level shift; in the lowest precision mode supported, the sub-results 0 to N-1 output by the N groups of shifters are the final shift results, and the high bits overflowed during left shift are discarded directly; if the precision mode control signal is a higher precision mode, then the result of the left shift of the high-bit shifter is subjected to bitwise OR operation with the bits overflowed during left shift of the low-bit shifter, so as to realize consecutive shift in the high precision mode.

[0013] In the multi-precision mask exponent mantissa module, the exponent segment and the mantissa segment masks are determined according to the input exponent bit width es configuration signal and the precision mode control signal, and meanwhile, the operand containing only the exponent segment and the mantissa segment output by the multi-precision regime shift module is also subjected to left shift by es-bit to ensure that the value of the exponent segment is right-aligned and the value of the mantissa segment is left-aligned; the shifted values are subjected to bitwise AND operation with the exponent segment mask and the mantissa segment mask respectively, to obtain the results of the exponent segment and the mantissa segment.

[0014] According to the precision mode control signal, it is determined whether the mask corresponding to each bit of the operand is the exponent segment mask or zero, so as to determine the exponent segment mask which is equal in length to the operand; the value of the mantissa segment mask is obtained by inverting all bits of the exponent segment mask.

[0015] The multi-precision Posit operation unit generally includes a multi-precision addition and subtraction operation unit, a multi-precision multiplication operation unit, a multi-precision multiplication and addition operation unit, a multi-precision division operation unit and a multi-precision square root operation unit, which accepts the output of the multi-precision Posit decoder, i.e., the valid sign, exponent and mantissa values, and completes corresponding operations in the above multi-precision Posit operation unit to obtain the valid sign, exponent and mantissa values of the operation result; the user can add operation units such as multi-precision addition, subtraction, multiplication and division as needed.

[0016] The multi-precision Posit encoder comprises a regime and exponent segment separation module, a multi-precision combined exponent and mantissa segment module, a multi-precision combined regime, exponent and mantissa segment module, and a multi-precision two's complement module; the functions realized by the two multi-precision two's complement modules are the same, one is located at the input side of the multi-precision Posit decoder, and the other is located at the output side of the multi-precision Posit encoder.

[0017] In the regime and exponent segment separation module, the value of the low es bits of the valid exponent input in each precision mode is the value of the exponent segment, and the value of the high bits is the value of the exponent scale factor k represented by the regime segment; an exponent segment mask with the same bit width is generated according to the precision mode control signal and the exponent bit width es configuration signal, and is bitwise ANDed with the valid exponent input to determine the value of the exponent segment; the exponent segment mask is inverted in its entirety, and then bitwise ANDed with the valid exponent input again, and the obtained result is right-shifted by es bits, so as to determine the value of k; in addition, the initial value of the regime segment and the actual bit width of the regime segment are determined according to the value of k.

[0018] In the multi-precision combined exponent and mantissa segment module, the exponent segment and the mantissa segment are combined together, and multi-precision shifting is performed to overflow the redundant bits in the high bits of the exponent segment.

[0019] In the multi-precision combined regime, exponent and mantissa segment module, the initial value of the regime segment is combined with the result output by the multi-precision combined exponent and mantissa segment module, multi-precision shifting is performed to overflow the redundant bits in the high bits of the regime segment, and the redundant bits are rounded according to the precision mode control signal, so as to obtain the absolute value of the result.

[0020] In the multi-precision two's complement module, multi-precision two's complement operation is realized by using a segmented method according to the valid sign input, so as to obtain the output of the multi-precision Posit encoder.

[0021] The application further provides a multi-precision Posit encoding and decoding operation method supporting variable exponent bit width, and the following calculation process is completed by the multi-precision Posit decoder:

[0022] In step a1, the input Posit data is subjected to multi-precision two's complement operation in the multi-precision two's complement module according to the precision mode control signal and the valid sign bit.

[0023] In step a2, the operation result after the two's complement operation is sent to the multi-precision leading 0 / 1 counting module, the number of leading 0 or leading 1 of the operation result in the corresponding precision mode is calculated, so as to determine the actual bit width of the regime segment.

[0024] Step a3, according to the actual bit width of the regime segment, the regime field of the multi-precision operand is shifted left in the multi-precision regime shifting module, and the low bits are filled with zeros, so as to obtain an operand containing only the exponent segment and the mantissa segment;

[0025] Step a4, in the multi-precision mask-exponent-mantissa module, according to the input exponent bit width es configuration signal and the precision mode control signal, the mask of the exponent segment and the mantissa segment is determined, and the mask is ANDed with the operand obtained in step a3, so as to obtain the values of the exponent segment and the mantissa segment, respectively;

[0026] Step a5, according to the outputs of step a2 and step a4, the effective sign, the effective exponent and the effective mantissa value of the input operand are determined, wherein the effective sign is the highest bit of the corresponding operand determined according to the precision mode control signal; the effective exponent is calculated as follows: first, the value of the exponent ratio factor k represented by the regime segment is determined according to the actual bit width of the regime determined in step a2, then the value of k is left shifted by es bits and ORed with the value of the exponent segment determined in step a4, so as to obtain the value of the effective exponent; the effective mantissa is calculated as follows: on the basis of the value of the mantissa segment determined in step a4, according to the precision mode control signal, hidden bits are added at the corresponding bit positions, so as to obtain the effective mantissa;

[0027] The following calculation process is completed by the multi-precision Posit encoder:

[0028] Step b1, for the effective exponent input, the exponent ratio factor k value and the exponent segment value in each precision mode are separated in the regime and exponent segment separation module: for each effective exponent, the low es bit value of the bit width is the encoding value of the exponent segment of the Posit data, which is an unsigned number; the value of the high bit is the exponent ratio factor k value obtained by encoding the regime segment of the Posit data, which is a signed number; at the same time, the initial value and the actual bit width of the regime segment are determined according to the value of k;

[0029] Step b2, according to the precision mode control signal, the separated value of the exponent segment and the effective mantissa without hidden bits are combined in the multi-precision combined regime, exponent and mantissa segment module, and the excess 0s in the high bits of the exponent segment in the combination are shifted left through multi-precision shifting, only the required es bits are reserved, and the whole after shifting is X;

[0030] Step b3, in the multi-precision combined regime, exponent and mantissa segment module, the initial value of the regime segment determined in step b1 and the whole X obtained in step b2 are combined, and according to the actual bit width of the regime segment, the excess bits of the regime segment are shifted left through multi-precision shifting, and the excess bits are rounded according to the precision requirement, so as to obtain the absolute value of the output result;

[0031] Step b4, in the multi-precision binary complement module, according to the effective symbol input, the absolute value obtained in step b3 is subjected to multi-precision binary complement, and a posit output result, that is, the output of the multi-precision posit encoder, is obtained.

[0032] Beneficial effects: the present application not only realizes the dynamic configuration of the exponent bit width during operation, thereby being able to support the advantages of the large dynamic range and high numerical precision of the posit format in the same hardware, but also realizes the high-efficiency multi-precision posit encoding and decoding operation of hardware, compared with the posit encoders of various precisions realized in hardware at the same time, the present application can realize smaller area overhead and higher energy efficiency, thereby better meeting the needs of the multi-precision operation of the neural network based on the posit format. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and / or other aspects of the present application will become apparent and more readily appreciated from the following description, taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a multi-precision posit decoder and encoder operation method schematic diagram.

[0035] Figure 2 is a multi-precision binary complement operation device schematic diagram.

[0036] Figure 3 is a multi-precision leading 0 / 1 count operation device schematic diagram.

[0037] Figure 4 is a multi-precision left shift operation device schematic diagram.

[0038] Figure 5 is a posit decoder operation device schematic diagram supporting variable exponent bit width.

[0039] Figure 6 is a posit decoder operation device schematic diagram supporting variable exponent bit width. DETAILED DESCRIPTION

[0040] The present application provides a multi-precision posit encoding and decoding operation device and method supporting variable exponent bit width, like Figure 1As shown, the device includes a multi-precision Posit decoder, a multi-precision Posit operation unit and a multi-precision Posit encoder; wherein the multi-precision Posit decoder receives Posit input data, and a precision mode control signal, an exponent bit width es configuration signal, and completes the decoding operation in the internal submodule to obtain the effective sign, exponent and mantissa value output. After completing the above decoding operation, the user can customize to add operation units such as Posit multi-precision addition, subtraction, multiplication and division, etc., according to the effective sign, exponent and mantissa value obtained by the above decoding to complete the corresponding operation. For example, for the Posit multiplication operation, the operation unit needs to complete the calculation of the exclusive or of the sign bit, the addition of the exponent value and the multiplication of the mantissa value. Finally, the effective sign, exponent and mantissa value of the above operation result are sent into the multi-precision Posit encoder, and the encoding of the Posit output data is completed according to the precision mode control signal and the exponent bit width es configuration signal.

[0041] Specifically, in the multi-precision Posit decoder, the main calculation process is as follows:

[0042] Step a1, the input Posit data is completed in the multi-precision two's complement module according to the precision mode control signal and the effective sign bit to complete the multi-precision two's complement operation;

[0043] Step a2, the operation number after completing the two's complement operation is sent into the multi-precision leading 0 / 1 count module to calculate the leading 0 or leading 1 number (i.e. the number of consecutive 0 or consecutive 1 bits in the high bit) of the operation number under the corresponding precision mode, so as to determine the actual bit width of the regime segment;

[0044] Step a3, according to the actual bit width of the regime segment, the regime field of the multi-precision operation number is shifted to the left in the multi-precision regime shift module, and the low bit is filled with zero, so as to obtain the operation number containing only the exponent segment and the mantissa segment;

[0045] Step a4, in the multi-precision mask exponent mantissa module, the mask of the exponent segment and the mantissa segment is determined according to the input exponent bit width es configuration signal and the precision mode control signal, and the mask is operated with the operation number obtained in step a3 bit by bit to obtain the value of the exponent segment and the mantissa segment, respectively;

[0046] Step a5, determine the effective sign, effective exponent and effective mantissa value of the input operand according to the output of step a2 and step a4. The effective sign is the highest bit of the corresponding operand determined according to the precision mode control signal; for the effective exponent: first determine the exponent scale factor k value represented by the regime segment according to the actual bit width of the regime determined in step a2, then left shift the k value by es bits and perform a bitwise OR operation with the value of the exponent segment determined in step a4 to obtain the effective exponent value; for the effective mantissa: on the basis of the mantissa segment value determined in step a4, add hidden bits to the corresponding bit positions according to the precision mode control signal to obtain the effective mantissa.

[0047] In the multi-precision Posit encoder, the main calculation process is as follows:

[0048] Step b1, for the effective exponent input, separate the exponent scale factor k value and the exponent segment value in each precision mode in the regime and exponent segment separation module: for each effective exponent, the value of the low es bits of its bit width is the encoding value of the exponent segment of the Posit data, which is an unsigned number; the value of the remaining high bits is the exponent scale factor k value obtained by encoding the regime segment of the Posit data, which is a signed number; at the same time, determine the initial value (initial value: 000…001 or 111…110) and the actual bit width of the regime segment according to the k value;

[0049] Step b2, according to the precision mode control signal, combine the separated exponent segment value and the effective mantissa input without hidden bits in the multi-precision combined regime, exponent and mantissa segment module, and left shift the excess 0s in the high bits of the exponent segment in the combination through multi-precision shifting, only keeping the needed es bits. The whole after shifting is X;

[0050] Step b3, in the multi-precision combined regime, exponent and mantissa segment module, combine the regime segment initial value determined in step b1 and the whole X obtained in step b2, and according to the actual bit width of the regime segment, left shift the excess bits of the regime segment through multi-precision shifting, and round off the excess bits according to the precision requirement to obtain the absolute value of the output result;

[0051] Step b4, in the multi-precision two's complement module, perform multi-precision two's complement on the absolute value obtained in step b3 according to the effective sign input to obtain the Posit output result, that is, the output of the multi-precision Posit encoder.

[0052] In order to realize the above-mentioned multi-precision Posit decoding and encoding function, one scheme is to realize single-precision Posit decoders and encoders of each precision in hardware, so that the corresponding precision coding and decoding units are enabled according to the precision mode control signal in operation, however, this implementation scheme greatly reduces the hardware utilization, increases the area overhead and computing power consumption. Therefore, in the present scheme, the segmented, hardware reuse and other means are fully utilized, so that the multi-precision coding and decoding operation of the Posit format can be effectively supported with little hardware overhead. Specifically, in the multi-precision binary complement, multi-precision leading 0 / 1 count, multi-precision shift and other operations existing in the Posit decoder and encoder, the present application adds part of selection and control logic in the high-precision data path to support parallel low-precision operation through segmentation and hardware reuse and other means, thereby realizing the hardware-efficient multi-precision binary complement device, multi-precision leading 0 / 1 count device, and multi-precision shift device. In addition, through masking and shifting and other means, support for variable exponent bit width can also be realized.

[0053] Multi-precision binary complement:

[0054] Binary complement, that is, for negative numbers, the sign bit is kept unchanged, and the rest of the bits are all inverted and then added by 1; for positive numbers, all bits remain unchanged. In the multi-precision Posit decoder, the input operand needs to be first binary complemented to ensure correct decoding of negative numbers. Similarly, in the Posit encoder, the absolute value result obtained also needs to be binary complemented to obtain the Posit output.

[0055] In order to realize the multi-precision binary complement operation and reduce the area overhead, as shown in Figure 2 , the present scheme adopts the segmented method to control the delay at a low level while reducing the area overhead. Specifically, the input operand is first divided into N segment sub-operands (where N is the value of the bit width of the input operand divided by the bit width of the lowest precision mode supported) according to the lowest precision mode supported, that is, sub-operand 0 to sub-operand N-1, and the effective sign of each segment sub-operand is determined according to the precision mode control signal. The sub-operand and its corresponding effective sign can complete the operation of inverting all bits for negative numbers and keeping all bits unchanged for positive numbers through XOR operation. In addition, according to the precision mode control signal, the effective sign of the sub-operand, and the carry generated by the low bit, it is determined whether the result after XOR operation needs to be added by 1. Finally, the N segment sub-results are spliced, and the precision mode control signal is used to perform or operation between the sign bit and the effective sign value at the sign bit, so as to obtain the value after multi-precision binary complement operation.

[0056] According to the above idea, binary complement operation under any multi-precision can be supported and realized.

[0057] Multiple-precision leading 0 / 1 count

[0058] In the Posit decoder, the actual bit-width of the regime field needs to be determined by the leading 0 or 1 count, so as to determine the value of the exponential scale factor k represented by the regime field, and the values of the exponent segment and the mantissa segment after the regime field.

[0059] In order to support the leading 0 / 1 count under multiple precision, avoid the additional hardware overhead of repeated counting under different precisions, such as Figure 3 As shown in the figure, the present scheme also adopts the method of segmented counting, and the counting result under low precision mode can be processed by the adder and the selector to obtain the counting result under high precision.

[0060] Specifically, the operand to be processed is divided into N sub-operands (where N is the bit width of the operand to be processed divided by the bit width of the lowest precision mode supported) according to the lowest precision supported, i.e. sub-operand 0 to sub-operand N-1, and N groups of parallel leading 0 / 1 count modules are used to calculate the respective leading 0 or 1 count (cpm[0] to cpm[N-1]) and the data valid signal (vpm[0] to vpm[N-1]) of the N groups of sub-operands. For each group of sub-operands, when the data valid signal vpm is 1, cpm is the exact leading 0 or 1 count; otherwise, when the data valid signal vpm is 0, it means that the sub-operand input is all 0 or all 1, and at this time cpm is also 0 accordingly.

[0061] When the precision mode control signal is the lowest precision supported (i.e. precision mode 1), the count results of cpm[0]~cpm[N-1] are the required count results; otherwise, the count results of each adjacent two sub-operations are processed to obtain the count results of the next precision mode, and the processing procedure is as follows: given the leading 0 / 1 numbers and the data valid signals of the two groups of low-precision sub-operations, which are as follows: the leading 0 / 1 number of sub-operation 0 is cpm[0], and the data valid signal is vpm[0]; the leading 0 / 1 number of sub-operation 1 is cpm[1], and the data valid signal is vpm[1]. To calculate the leading 0 / 1 number (i.e. cph[0]) and the data valid signal (i.e. vph[0]) of the corresponding operation in the higher precision mode, only the leading 0 / 1 numbers (i.e. cpm[0] and cpm[1]) and the data valid signals (i.e. vpm[0] and vpm[1]) of the above-mentioned two sub-operations are processed through selection and addition logic to obtain: when vpm[1] is 1, it represents that the count of sub-operation 1 is valid, and the value of cph[0] is equal to cpm[1], and vph[0] is also equal to 1; when vpm[1] is 0, if the highest bits of sub-operation 1 and sub-operation 0 are different (i.e. one sub-operation is the leading 0 count, and the other sub-operation is the leading 1 count), the value of cph[0] is equal to the bit width of the sub-operation, and vph[0] is equal to 1; if vpm[1] is 0, and sub-operation 1 and sub-operation 0 are both the leading 0 or the leading 1, the value of cph[0] is equal to the bit width of sub-operation 1 plus the value of cpm[0], and the value of vph[0] is also equal to vpm[0].

[0062] According to the above operation, the leading 0 / 1 count results and the data valid signals in the low-precision mode are processed in pairs to obtain the leading 0 / 1 count results and the data valid signals in the higher precision mode, until the leading 0 / 1 count results and the data valid signals in the precision mode M (i.e. the highest precision mode supported) are obtained. According to the above idea, the present scheme supports the leading 0 / 1 count in any multi-precision mode, and supports the low-precision mode by adding only a few selectors and adders, thereby avoiding the repeated leading 0 / 1 count process and achieving high hardware efficiency.

[0063] Multi-precision shift:

[0064] In the Posit decoder, after the actual bit-width of the regime segment is determined by the leading 0 / 1 counter, the operands are left-multiplied in the multi-precision regime shift module to move the sign segment and the regime segment out, so as to determine the values of the exponent segment and the mantissa segment. In the Posit encoder, the multi-precision left shift is used in the multi-precision combine exponent and mantissa segment module and the multi-precision combine regime, exponent and mantissa segment module to shift the excess bits of the exponent segment and the regime segment out, respectively, so as to realize the correct encoding of the Posit format.

[0065] Since dynamic shift is involved, if each shift is implemented for each precision mode to be supported, a large area overhead will be generated. Therefore, as shown in Figure 4 the present scheme adopts segmented and hierarchical shift to fully reuse hardware, and realizes efficient support for multi-precision shift with only partial selection and control logic added.

[0066] Specifically, first, the operand is divided into N segment sub-operands (where N is the bit-width of the operand divided by the bit-width of the lowest precision mode supported) according to the lowest precision mode supported, i.e. sub-operand 0 to sub-operand N-1, and the left shift amount of each segment sub-operand is determined according to the precision mode control signal. In the lowest precision mode supported (i.e. precision mode 1), the maximum shift amount of each sub-operand is the bit-width of the sub-operand, which can be saved by a number of L bits (where L is the value obtained by log2 operation on the bit-width of the sub-operand); in the highest precision mode supported (i.e. precision mode M), the maximum shift amount is the total bit-width of the operand, which can be saved by a number of K bits (where K is the value obtained by log2 operation on the total bit-width of the operand). Next, segmented and hierarchical shift is performed, i.e. the N sub-operands are sent into respective shifters in parallel (which can be implemented by structures such as barrel shifters, etc.), and 1-L level shift is completed. In the precision mode 1 (i.e. the lowest precision mode supported), the sub-results 0 to N-1 output by the N groups of shifters are the final shift results, and the high bits shifted out can be directly discarded; if the precision mode control signal is a higher precision mode, the result of the left shift of the high-bit shifter needs to be bitwise ORed with the bits shifted out when the low-bit shifter is left shifted, so as to realize consecutive shift in the high precision mode.

[0067] According to the above design idea, efficient hardware shift process in any multi-precision can be realized with only partial selection and bitwise OR logic added.

[0068] Multi-precision mask and shift support variable exponent bit-width:

[0069] In general Posit operation units, since only fixed exponent bit width es is supported, in the Posit decoding process, the operand containing only the exponent segment and the mantissa segment is obtained by regime shift, and the value of the highest fixed es bit of the operand is the value of the exponent segment; in the Posit encoding process, only the fixed es bit width is used to save the value of the exponent segment, and the value is combined into the regime segment. This design is simple to implement, but the fixed exponent bit width limits the dynamic range or numerical precision that can be represented by the Posit format, and cannot support high numerical precision or large dynamic range in the same hardware. Therefore, the Posit encoding and decoding operation device proposed in the present scheme not only supports high-precision operation in hardware, but also supports variable exponent bit width, greatly improving the flexibility of Posit operation in neural networks.

[0070] In a specific implementation, since the exponent bit width is variable, the value of the exponent segment can only be saved by the largest exponent bit width in the decoding and encoding processes. For example, when the exponent bit width es configuration signal is 3 bits, representing the exponent bit width value of 0-7, at least 7 bits of value are required to accurately save the value of the exponent segment. By performing bitwise AND operation with the same bit width exponent mask, the irrelevant position 0 can be removed, and by shifting, the excess bits of the exponent segment can be shifted out during encoding, thereby realizing the support of variable exponent bit width by Posit encoding and decoding.

[0071] Specifically, in the multi-precision Posit decoder, according to the input exponent bit width configuration signal and precision mode control signal, the exponent segment and mantissa segment masks can be determined, and at the same time, the operand containing only the exponent segment and mantissa segment output by the multi-precision regime shift module is also left shifted by es-bit to ensure that the value of the exponent segment is right-aligned (unsigned number, high bits are padded with 0, which does not affect the size of the exponent segment value), and the value of the mantissa segment is left-aligned (low bits are padded with 0, which does not affect the size of the mantissa segment value). By performing bitwise AND operation on the shifted value and the exponent segment mask and the mantissa segment mask, the results of the exponent segment and the mantissa segment can be obtained, as shown in Figure 5 .

[0072] For the exponent segment mask, in a specific embodiment, assuming that the exponent bit width configuration signal es is 3-bit, that is, the real exponent segment has a bit width of 0-7, the generated exponent segment mask is shown in the following table. According to the precision mode control signal, the mask corresponding to each bit of the operand is selected as the exponent segment mask or zero, thereby determining the exponent segment mask equal to the operand. In addition, the value of the mantissa segment mask can be obtained by inverting all bits of the exponent segment mask.

[0073] Table 1 is the exponent segment mask generated by the 3-bit exponent bit width configuration signal es:

[0074] Table 1

[0075] exponent bit width es exponent segment mask 000 000_0000 001 000_0001 010 000_0011 011 000_0111 100 000_1111 101 001_1111 110 011_1111 111 111_1111

[0076] by Figure 6 For example, the operand contains two sub-operands, each with an exponent segment and a mantissa segment. By shifting it left by es-bit and generating the exponent segment mask and mantissa segment mask according to the exponent bit width configuration signal and the precision mode control signal (the gray filled part represents the mask value of 1, and the blank part represents the mask value of 0), the left-shifted operand is bitwise ANDed with the mask to obtain the values ​​of the exponent segment and mantissa segment.

[0077] For the multi-precision Posit encoder, in the regime and exponent segment separation module, the value of the low es bit of the effective exponent input in each precision mode is the value of the exponent segment, and the value of the high bit is the value of the exponent scale factor k represented by the regime segment. According to the precision mode control signal and the exponent bit width configuration signal, an exponent segment mask with the same bit width is generated, and the value of the exponent segment can be determined by bitwise AND operation with the effective exponent input; after all the above exponent segment masks are inverted, they are bitwise ANDed with the effective exponent input again, and the result is right-shifted by es bits to determine the k value.

[0078] In the multi-precision combined exponent and mantissa segment module, the exponent segment and mantissa segment are combined. However, since the exponent segment value must be stored using the maximum bit width, and the actual bit width of the exponent segment may be smaller than the maximum bit width, shifting is required to overflow the excess bits in the upper bits of the exponent segment. For example, when the exponent bit width configuration signal es is 3'b101, although this means the actual exponent segment width is 5, the hardware can only store the exponent segment using the maximum bit width of 7 bits. Therefore, under this exponent bit width configuration signal, the upper two bits of the 7-bit value used to represent the exponent segment are invalid and must be shifted out. In different precision modes, the exponent bit width configuration signal can be used to determine the shift amount for each sub-operand. Then, according to the multi-precision shifting strategy proposed above, segmented and hierarchical shifting can achieve higher hardware utilization.

[0079] Therefore, through the masking and shifting ideas proposed above, efficient support for runtime configurability of the exponent bit width can be achieved in both the multi-precision Posit decoder and encoder, thereby improving the flexibility of Posit operations.

[0080] Example:

[0081] Application scenarios: the application provides a multi-precision posit coding and decoding operation device and method supporting variable exponent bit width, which is particularly suitable as a codec of an operation unit based on a posit format and is applied in a neural network hardware accelerator. The application not only realizes dynamic configuration of the exponent bit width at runtime, thereby supporting the advantages of a large dynamic range and high numerical precision of the posit format in operation, which helps to improve the calculation precision of the accelerator. On the other hand, the application supports multi-precision posit coding and decoding operation, which helps the accelerator to realize flexible precision configuration in the operation process and greatly improves the calculation efficiency. In addition, for the two's complement, leading 0 / 1 count and shift process in the posit coding process, the application realizes a multi-precision two's complement device, a multi-precision leading 0 / 1 count device and a multi-precision shift device based on segmentation and hardware multiplexing, etc., which realizes high area efficiency and energy efficiency and reduces the hardware overhead of the device deployed in the accelerator.

[0082] Specific embodiments: the method and device provided by the application realize a multi-precision posit coding and decoding device supporting variable exponent bit width based on 1*16-bit and 2*8-bit. In the following operation, the precision mode control signal is set to 8-bit mode, and the exponent bit width es configuration signal bit width is 3 bits, and the value represented is 1.

[0083] For the multi-precision posit decoder, it is assumed that there is a 16-bit input operand: 1000_1010_0010_1001. In the 8-bit precision mode, the high 8-bit sub-operation number 1 (i.e. 1000_1010) and the low 8-bit sub-operation number 0 (i.e. 0010_1001) are respectively decoded to obtain the effective symbol, exponent and mantissa value. The decoding steps are as follows:

[0084] Step a1: the input posit data is subjected to multi-precision two's complement operation in the multi-precision two's complement module according to the precision mode control signal and the effective symbol bit. For the sub-operation number 1 and the sub-operation number 0, the effective symbols are 1 and 0 respectively, and in the segmented two's complement process, the carry generated by the low 8-bit does not need to be propagated to the high 8-bit, so the multi-precision two's complement result is: 0111_0110_0010_1001.

[0085] Step a2: The operation number after the completion of the binary complement operation is sent to the multi-precision leading 0 / 1 counting module, and the leading 0 or leading 1 number of the operation number under the corresponding precision mode is calculated to determine the actual bit width of the regime segment. For the sub-operation number 1 (i.e. 0111_0110), the leading 1 number of the regime segment is 3, and the actual bit width of the regime segment is 4. For the sub-operation number 0 (i.e. 0010_1001), the leading 0 number of the regime segment is 1, and the actual bit width of the regime segment is 2.

[0086] Step a3: According to the actual bit width of the regime segment, the regime field of the multi-precision operation number is left shifted in the multi-precision regime shift module, and the low bits are filled with zeros, so as to obtain the operation number containing only the exponent segment and the mantissa segment. For the sub-operation number 1 (i.e. 0111_0110), it needs to be left shifted by 5-bit, and for the sub-operation number 0 (i.e. 0010_1001), it needs to be left shifted by 3-bit. Multi-precision segmented shift is adopted, and the result after the left shift of the sub-operation number 1 does not need to be bitwise OR operated with the overflow bits after the left shift of the sub-operation number 0. Thus, the shifted result is 1100_0000_0100_1000.

[0087] Step a4: In the multi-precision mask exponent mantissa module, the exponent segment and the mantissa segment mask are determined according to the input exponent bit width es configuration signal and the precision mode control signal, and the mask is bitwise AND operated with the operation number obtained in step 3 to obtain the values of the exponent segment and the mantissa segment. Specifically, in this example, the exponent bit width es configuration signal is 3-bit, and the actual value is 1, so the generated exponent segment mask is 000_0001. The result after the shift in step 3 is left shifted by es bits (the actual value of es in this operation is 1) to ensure that the value of the exponent segment is right-aligned and the value of the mantissa segment is left-aligned, and the same bit width exponent mask and mantissa mask determined according to the precision mode control signal are bitwise AND operated to obtain the value of the exponent segment of the sub-operation number 1 as 1 and the value of the mantissa segment as 1000_0000, and the value of the exponent segment of the sub-operation number 0 as 0 and the value of the mantissa segment as 1001_0000.

[0088] Step a5: Determine the effective sign, the effective exponent and the effective mantissa value of the input operands according to the outputs of step a2 and step a4. For the effective sign, the effective sign of sub-operand 1 and sub-operand 0 are determined to be 1 and 0 respectively according to the precision mode control signal. For the effective exponent, first, the exponent scale factor represented by the regime segment of sub-operand 1 and sub-operand 0 are determined to be 2 and -1 respectively according to the actual bit-width of the regime segment obtained in step a2. Then, the k value is left shifted by es bits and bitwise ORed with the value of the exponent segment obtained in step a4 to obtain the effective exponent of sub-operand 1 and sub-operand 0 as 5 and -2 respectively. For the effective mantissa, the value of the mantissa segment obtained in step a4 is appended with hidden bits at the high bits according to the precision mode control signal to obtain the effective mantissa of sub-operand 1 and sub-operand 0 as 1100_0000 and 1100_1000 respectively.

[0089] For the multi-precision Posit encoder, it is assumed that there exists an effective sign input 10 (2-bit, representing the effective sign of the two 8-bit sub-results to be output respectively), an effective exponent input 0000_0101_1111_1110 (16-bit, each 8-bit is a signed number, representing the effective exponent of the two 8-bit sub-results to be output respectively) and an effective mantissa input 1100_0000_1100_1000 (16-bit, each 8-bit is the effective mantissa of the two 8-bit sub-results to be output respectively). The multi-precision Posit decoding process is as follows:

[0090] Step b1 : For the effective exponent input, separate the exponent scale factor k value and the exponent segment value in the regime and exponent segment separation module under each precision mode, and determine the initial value and the actual bit-width of the regime segment according to the k value. Therefore, the exponent scale factor k value and the exponent segment value of sub-result 1 are determined to be 2 and 1 respectively, and the exponent scale factor k value and the exponent segment value of sub-result 0 are determined to be -1 and 0 respectively. In addition, according to the k value, the initial value of the regime segment of sub-result 1 and sub-result 0 are determined to be 000_0001 and 1111_1110 respectively.

[0091] Step b2: According to the precision mode control signal, combine the separated exponent segment value with the value without hidden bits in the multi-precision combined regime, exponent and mantissa segment module, and left shift the excess 0s at the high bits of the exponent segment by multi-precision shifting to remove the excess 0s and only keep the required es bits, and the whole after shifting is X. For sub-result 1, the whole X is 11_0000_0000_0000; for sub-result 0, the whole X is 01_0010_0000_0000.

[0092] Step b3: In the multi-precision combination regime, index and mantissa segment module, the regime segment initial value determined in step b1 and the whole X obtained in step b2 are continued to be combined together, and according to the actual bit width of the regime segment, the redundant bits of the regime segment are left shifted out through multi-precision shifting, and the redundant bits are rounded according to the precision requirement, to obtain the absolute value of the output result. For the sub-result 1, the obtained absolute value is: 0111_0110; for the sub-result 0, the obtained absolute value is: 0010_1001

[0093] Step b4: In the multi-precision two's complement module, according to the effective symbol input, the absolute value obtained in step b3 is subjected to multi-precision two's complement, to obtain the Posit encoding result. For the sub-result 1, the effective symbol input is 1, so the two's complement value is: 1000_1010; for the sub-result 0, the effective symbol input is 0, so the two's complement value is: 0010_1001. Therefore, the output of the multi-precision Posit encoder is: 1000_1010_0010_1001.

[0094] In addition, in specific embodiments, based on the multi-precision Posit encoding and decoding operation device and method supporting variable index bit width proposed in the application, a 32-bit multi-precision Posit decoder and Posit encoder are realized, which supports 1*32-bit or 2*16-bit or 4*8-bit multi-precision encoding and decoding, and supports variable index bit width. At the same time, the above functions are realized by using a single-precision Posit encoding and decoding unit also supporting variable index bit width, so that four 8-bit single-precision Posit decoders and encoders, two 16-bit single-precision Posit decoders and encoders, and one 32-bit single-precision Posit decoder and encoder are simultaneously realized in hardware, so as to enable the required Posit decoder and encoder according to the precision mode control signal.

[0095] The 32-bit multi-precision Posit decoder and Posit encoder realized by the present scheme are synthesized with single-precision Posit decoders and encoders based on 8-bit, 16-bit and 32-bit in TSMC 28nm process, and the delay, area and power consumption of the two are shown in Table 2 and Table 3 respectively:

[0096] Table 2

[0097]

[0098] Table 3

[0099]

[0100]

[0101] It can be seen that, based on the 32-bit single-precision Posit decoder and the Posit encoder, the scheme realizes the support for parallel low-precision Posit encoding and decoding by means of segmentation and hardware multiplexing, etc., under the condition of increasing a small amount of hardware overhead.

[0102] Specifically, for the multi-precision Posit decoder, to realize the equivalent multi-precision support function of the scheme by using the single-precision Posit decoder, it is necessary to realize the combination of four groups of 8-bit decoders, two groups of 16-bit decoders and one group of 32-bit decoders, and compared with this, the scheme realizes the area reduction of 38.76% and the power consumption reduction of 52.26%, and achieves high area efficiency and energy efficiency. In addition, the multi-precision Posit decoder has almost no additional delay overhead compared with the 32-bit single-precision Posit decoder, which ensures that the scheme can realize high computing performance when supporting parallel low-precision. For the multi-precision Posit encoder, compared with the combination of four groups of 8-bit encoders, two groups of 16-bit encoders and one group of 32-bit encoders, the scheme also realizes the area reduction of 15.15% and the power consumption reduction of 30.54%, and reduces the hardware overhead of supporting multi-precision Posit encoding.

[0103] The application provides a multi-precision Posit encoding and decoding operation device and method supporting variable exponent bit width, and there are many methods and ways to realize the technical scheme, and the above description is only the preferred embodiment of the application, and it should be pointed out that, for ordinary technical personnel in the technical field, some improvements and refinements can be made without departing from the principle of the application, and these improvements and refinements should also be regarded as the protection range of the application. The components not explicitly described in the embodiment can be realized by using the existing technology.

Claims

1. A multi-precision Posit encoding and decoding device supporting variable exponent bit width, characterized in that: Including multi-precision Posit decoder, multi-precision Posit operation unit and multi-precision Posit encoder; The multi-precision Posit decoder receives Posit input data, a precision mode control signal, and an exponent width es configuration signal, completes a decoding operation, and obtains a valid sign, exponent, and mantissa value output; The multi-precision Posit operation unit performs corresponding operations according to the obtained valid sign, exponent and mantissa values, and sends the operation results to the multi-precision Posit encoder, and the multi-precision Posit encoder completes the encoding of the Posit output data according to the precision mode control signal and the exponent bit width es configuration signal; The multi-precision Posit decoder includes a multi-precision binary complement module, a multi-precision leading 0 / 1 counting module, a multi-precision regime shift module and a multi-precision mask exponent mantissa module; In the multi-precision masked exponent and mantissa module, the masks of the exponent and mantissa segments are determined according to the input exponent bit width es configuration signal and the precision mode control signal. At the same time, the operand output by the multi-precision regime shift module, which only contains the exponent and mantissa segments, is also left-shifted by es bits to ensure that the exponent segment value is right-aligned and the mantissa segment value is left-aligned. The shifted values ​​are bitwise ANDed with the exponent segment mask and the mantissa segment mask respectively to obtain the results of the exponent segment and mantissa segment. The mask corresponding to each bit of the operand is selected as the exponent segment mask or zero according to the precision mode control signal, thereby determining an exponent segment mask of the same length as the operand; all bits of the exponent segment mask are inverted to obtain the value of the mantissa segment mask; The multi-precision Posit encoder includes a regime and exponent segment separation module, a multi-precision combined exponent and mantissa segment module, a multi-precision combined regime, exponent and mantissa segment module, and a multi-precision two's complement module; In the regime and exponent segment separation module, the value of the low es bit of the effective exponent input in each precision mode is the value of the exponent segment, and the value of the high bit is the value of the exponent scale factor k represented by the regime segment. According to the precision mode control signal and the exponent bit width es configuration signal, an exponent segment mask with the same bit width is generated, and the mask is bitwise ANDed with the effective exponent input to determine the value of the exponent segment; after all the exponent segment masks are inverted, they are bitwise ANDed with the effective exponent input again, and the result is right-shifted by es bits to determine the k value; according to the k value, the initial value of the regime segment and the actual bit width of the regime segment are determined.

2. The device according to claim 1, characterized in that The multi-precision binary complement module uses a segmented method to implement a multi-precision binary complement operation, specifically including: firstly dividing the input operand into N segments of sub-operands according to the lowest precision mode supported, namely, sub-operand 0 to sub-operand N-1, and determining the effective sign of each segment of sub-operand according to the precision mode control signal, performing an exclusive OR operation on the sub-operand and its corresponding effective sign to complete the inversion operation of all bits of negative numbers and the operation of keeping all bits unchanged for positive numbers; determining whether the result after the exclusive OR operation needs to be added by 1 according to the precision mode control signal, the effective sign of the sub-operand, and the carry generated by the low bit; finally, splicing the obtained N segments of sub-results, and performing an OR operation with the effective sign value at the sign bit according to the precision mode control signal to obtain the value after the multi-precision binary complement operation.

3. The device according to claim 2, characterized in that The multi-precision leading 0 / 1 counting module adopts a segmented counting method, and the counting result in the low-precision mode is processed by an adder and a selector to obtain the counting result in the high-precision mode, specifically comprising: dividing the operand to be processed into N segments of sub-operands according to the lowest precision supported, that is, sub-operand 0 to sub-operand N-1, and calculating the leading 0 or 1 number of each of the N groups of sub-operands through N groups of parallel leading 0 / 1 counting modules, respectively: cpm[0]~cpm[N-1], and the data valid signals of each of the N groups of sub-operands, respectively: vpm[0]~vpm[N-1], respectively, when the data valid signal vpm is 1, cpm is the exact leading 0 or leading 1 number; otherwise, when the data valid signal vpm is 0, it means that the sub-operand input is all 0 or all 1, and at this time cpm is 0; When the precision mode control signal is the lowest supported precision, cpm[0]~cpm[N-1] are the required leading 0 / 1 counting results; otherwise, the counting results of each adjacent sub-operand are processed in pairs at each level to obtain the counting results of the next precision mode.

4. The device according to claim 3, characterized in that The multi-precision regime shift module adopts the segmented and hierarchical shifting method to realize the support for multi-precision shift, specifically including: dividing the operand into N segments of sub-operands according to the lowest precision mode supported, that is, sub-operand 0 to sub-operand N-1, and determining the left shift amount of each segment of sub-operand according to the precision mode control signal. In the lowest precision mode supported, the maximum shift amount of each sub-operand is the bit width of the sub-operand, which is saved as an L-bit number, where L is the value after the log2 operation of the bit width of the sub-operand; in the highest precision mode supported, the maximum shift amount is the operand The total bit width of the operand is stored as a K-bit number, where K is the value after doing log2 operation on the total bit width of the operand; segmented and hierarchical shifting is performed, and the N sub-operands are sent to their respective shifters in parallel to complete the 1-L level shift; in the lowest precision mode supported, the sub-result 0 to sub-result N-1 output by the N groups of shifters are the final shift results, and the high bits of the left shift overflow are directly discarded; if the precision mode control signal is a higher precision mode, the result after the high-order shifter is left-shifted is bitwise ORed with the overflowed bit when the low-order shifter is left-shifted to achieve coherent shifting in high-precision mode.

5. The device according to claim 4, characterized in that In the multiple-precision combined exponent and mantissa segment module, the exponent segment and the mantissa segment are combined together, and the redundant bits in the high order of the exponent segment are overflowed by multiple-precision shifting.

6. The device according to claim 5, characterized in that In the multi-precision combined regime, exponent, and mantissa segment module, the initial value of the regime segment is further combined with the result output by the multi-precision combined exponent and mantissa segment module, and the excess bits in the high order of the regime segment are overflowed by multi-precision shifting, and the excess bits are rounded according to the precision mode control signal to obtain the absolute value of the result; In the multi-precision binary complement module, a segmented method is used to implement binary complement operations under multiple precision according to the valid symbol input, and the output of the multi-precision Posit encoder is obtained.

7. A multi-precision Posit encoding and decoding method supporting variable exponent bit width, characterized in that: The following calculation process is completed by the multi-precision Posit decoder: Step a1: The input Posit data is subjected to a multiple-precision two's complement operation in a multiple-precision two's complement module according to the precision mode control signal and the valid sign bit; Step a2: The operand after the two's complement operation is sent to the multi-precision leading 0 / 1 counting module to calculate the number of leading 0s or leading 1s of the operand in the corresponding precision mode, thereby determining the actual bit width of the regime segment; Step a3: According to the actual bit width of the regime segment, the regime field of the multi-precision operand is shifted left in the multi-precision regime shift module, and the low-order bits are padded with zeros, thereby obtaining an operand containing only the exponent segment and the mantissa segment; Step a4: In the multi-precision masked exponent and mantissa module, the masks of the exponent segment and the mantissa segment are determined according to the input exponent bit width es configuration signal and the precision mode control signal, and the mask is bitwise ANDed with the operand obtained in step a3 to obtain the values ​​of the exponent segment and the mantissa segment, respectively. Step a5, determining a valid sign, a valid exponent, and a valid mantissa value of the input operand based on the outputs of steps a2 and a4, wherein the valid sign is the most significant bit of the corresponding operand determined according to the precision mode control signal; The effective exponent is calculated by first determining the exponent scaling factor k represented by the regime segment based on the actual bit width of the regime determined in step a2, then shifting the k value left by es bits and performing a bitwise OR operation on the k value with the exponent segment value determined in step a4 to obtain the effective exponent value. The effective mantissa is calculated by adding a hidden bit to the corresponding bit position based on the mantissa segment value determined in step a4 and the precision mode control signal to obtain the effective mantissa. The following calculation process is completed by the multi-precision Posit encoder: Step b1: For valid exponent input, separate the exponent scale factor k value and exponent segment value in each precision mode in the regime and exponent segment separation module: For each valid exponent, the low-order es bit value of its bit width is the encoded value of the Posit data exponent segment, which is an unsigned number; the remaining high-order bit value is the exponent scale factor k value obtained by encoding the Posit data regime segment, which is a signed number; at the same time, the initial value and actual bit width of the regime segment are determined based on the k value; Step b2: Based on the precision mode control signal, the separated exponent segment value is combined with the valid mantissa input without hidden bits in the multi-precision combination regime, exponent, and mantissa segment module. The redundant zeros in the high-order bits of the exponent segment in the combination are left-shifted by multi-precision shifting, leaving only the required es bits. The shifted total is X. Step b3: In the multi-precision combination module of the regime, exponent, and mantissa segments, the initial value of the regime segment determined in step b1 is further combined with the overall X obtained in step b2. Based on the actual bit width of the regime segment, the excess bits of the regime segment are shifted left using a multi-precision shift. The excess bits are rounded according to the required precision to obtain the absolute value of the output result. Step b4, in the multiple-precision two's complement module, based on the valid sign input, performs multiple-precision two's complement on the absolute value obtained in step b3 to obtain a Posit output result, i.e., the output of the multiple-precision Posit encoder.

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