半导体存储器、刷新方法和电子设备
By introducing marked storage areas and flag bits into the DRAM memory, the problem of not being able to accurately locate the attack target under Row Hammer attacks is solved, and a more efficient refresh strategy and power consumption optimization are achieved.
CN116935916BActive Publication Date: 2026-07-17CHANGXIN MEMORY TECH INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-08
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing DRAM memory cannot accurately locate the target of a Row Hammer attack, resulting in poor refresh performance and high power consumption.
Method used
Introducing a marked storage area into the DRAM memory, the hammered row of the row hammering event is marked by the first flag bit, and the state of adjacent storage rows is determined by the second flag bit, thus identifying the attack target and optimizing the refresh strategy.
Benefits of technology
It improves the handling of hammer impact events, reduces power consumption, and enhances the reliability and efficiency of the memory.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN116935916B_ABST
Abstract
本公开实施例提供了一种半导体存储器、刷新方法和电子设备，该半导体存储器包括主存储区域和标记存储区域，主存储区域中设置多个存储行，标记存储区域中设置多个第一标志位；其中，每一存储行与一个第一标志位具有对应关系，且第一标志位用于指示存储行是否为行锤击事件的锤击行。这样，由于半导体存储器中新增了标记存储区域，通过第一标志位可以标记行锤击事件的锤击行，明确行锤击的攻击对象，能够提高行锤击事件的处置效果且节省功耗。
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