Digital buffer device with self-correction

Abstract

A digital buffer device with self-correction includes a first buffer circuit, a sensing circuit, and a correction circuit. The first buffer circuit has a buffer input for receiving an input signal and a buffer output as an output of the digital buffer device. The sensing circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one sensing signal indicative of variations in circuit characteristics of the at least one second buffer circuit. The at least one second buffer circuit is of the same type as the first buffer circuit. The correction circuit has a correction input for receiving the input signal and a correction output coupled to the buffer output. The correction circuit is for correcting the first buffer circuit based on the input signal and the at least one sensing signal to generate an output signal.

Description

Technical Field

[0001] This invention relates to a digital buffer device, and more particularly to a digital buffer device with self-correction. Background Technology

[0002] Storage systems, such as memory devices based on double-data-rate (DDR) or low-power DDR memory technologies, employ digital buffers to buffer signals, ensuring that the buffered signals are correctly processed by the internal circuitry of the memory system. If the signal is an instruction, clock, or data signal and the quality of the buffered signal is degraded, the internal circuitry may misinterpret the buffered signal, leading to operational problems in the memory system.

[0003] For example, digital buffers are susceptible to process variations, which can cause deviations in the rising or falling edges of the buffered signal. Designing digital buffers to ensure signal quality is difficult and time-consuming for circuit designers. Summary of the Invention

[0004] The purpose of this invention is to provide a self-correcting digital buffer device. This digital buffer device is capable of detecting variations in the circuit characteristics of a plurality of buffer circuits of one type included in the digital buffer device, and is capable of correcting one of the plurality of buffer circuits based on an input signal and the detection result to generate an output signal.

[0005] To at least achieve the above objectives, the present invention provides a self-calibrating digital buffer device, comprising a first buffer circuit, a detection circuit, and a calibration circuit. The first buffer circuit has a buffer input for receiving an input signal and a buffer output as an output of the digital buffer device. The detection circuit includes at least one second buffer circuit for receiving at least one reference signal and generating at least one detection signal to represent a variation in the circuit characteristics of the at least one second buffer circuit. The at least one second buffer circuit is a buffer of the same type as the first buffer circuit. The calibration circuit has a calibration input for receiving an input signal and a calibration output coupled to the buffer output. The calibration circuit is used to calibrate the first buffer circuit according to the input signal and the at least one detection signal to generate an output signal.

[0006] Therefore, the digital buffer device can detect variations in the circuit characteristics of multiple buffer circuits of one type (e.g., a first buffer circuit and a second buffer circuit) included in the digital buffer device to generate the at least one detection signal, and correct the first buffer circuit based on the input signal and the at least one detection signal to generate an output signal. Thus, the signal quality of the output signal of the digital buffer device is enhanced. Attached Figure Description

[0007] Figure 1 The schematic diagram illustrates an exemplary architecture of a self-correcting digital buffer device, which represents various embodiments of the present invention;

[0008] Figure 2 According to Figure 1 A block diagram of one embodiment of a digital buffer device with a model architecture;

[0009] Figure 3 For example, according to Figure 2 Circuit diagram of an embodiment of a digital buffer device;

[0010] Figure 4 For example Figure 3 A schematic diagram illustrating an example of the variation in circuit characteristics of the buffer circuit described herein;

[0011] Figure 5 For example Figure 3 A schematic diagram illustrating an example of output signal variation in the buffer circuit described herein;

[0012] Figure 6 For example Figure 3 A schematic diagram of another example of the output signal variation of the buffer circuit described herein; and

[0013] Figure 7 Here is a block diagram illustrating another embodiment of the detection circuit.

[0014] The annotations in the attached figures are explained as follows:

[0015] 1, 2, 2A Digital Buffer Device

[0016] 10, 10A First Buffer Circuit

[0017] Detection circuits 20, 20_1, 20_1A, and 20_2

[0018] 21, 21_1-21_P, 21_1A-21_4A Second Buffer Circuit

[0019] 30, 30_1, 30_1A correction circuit

[0020] 31_1, 31_2 Third Buffer Circuit

[0021] 40, 40_1 voltage divider

[0022] CM1-CM4 Correction Transistors

[0023] DT, DT_1-DT_P detection signals

[0024] IN input signal

[0025] LH_1-LH_P latches

[0026] LT line

[0027] Transistors M11, M12, M31, M32, M33, and M34

[0028] N11 Buffer Input

[0029] N12 Buffer Output

[0030] N31 calibration input terminal

[0031] N32 Calibration Output Terminal

[0032] NC_1-NC_P calibration terminals

[0033] OUT output signal

[0034] RS, RS_1-RS_P reference signals

[0035] RST reset signal

[0036] SW switchgear

[0037] TG_1-TG_P Transmission Gate

[0038] Voltage values ​​of V1, V2, V3, V4

[0039] VDD power supply voltage

[0040] VI Input Signal

[0041] VIL, VIH voltage

[0042] VO output signal

[0043] VT1-VT7 curves Detailed Implementation

[0044] To facilitate understanding of the objectives, features, and effects of the present invention, embodiments and accompanying drawings are provided for a detailed description of the invention.

[0045] Please see Figure 1The diagram illustrates an exemplary architecture of a self-correcting digital buffer device, representing various embodiments of the invention. For example... Figure 1 As shown, a self-calibrating digital buffer device 1 is capable of detecting circuit characteristic variations of a plurality of buffer circuits of one type included in the digital buffer device 1 to generate at least one detection signal, and is capable of correcting one of the plurality of buffer circuits based on an input signal IN and at least one detection signal (i.e., a detection result) to generate an output signal OUT. The digital buffer device 1 includes a first buffer circuit 10, a detection circuit 20, and a correction circuit 30.

[0046] The first buffer circuit 10 has a buffer input terminal N11 for receiving the input signal IN and a buffer output terminal N12.

[0047] The detection circuit 20 includes at least one second buffer circuit 21 for receiving at least one reference signal RS and generating at least one detection signal to indicate a circuit characteristic variation of at least one second buffer circuit 21, wherein at least one second buffer circuit 21 is a buffer of the same type as the first buffer circuit 10.

[0048] The correction circuit 30 has a correction input terminal N31 for receiving the input signal IN, and a correction output terminal N32 coupled to the buffer output terminal N12 of the first buffer circuit 10. The correction circuit 30 is used to correct the first buffer circuit 10 according to the input signal IN and at least one detection signal DT to generate an output signal OUT, wherein the buffer output terminal N12 of the first buffer circuit 10 serves as the output of the digital buffer device 1.

[0049] Please refer to Figure 2 ,according to Figure 1 The exemplary architecture is shown in block diagram as an embodiment of a digital buffer device. For example... Figure 2 As shown, the digital buffer device 2 includes a first buffer circuit 10, a detection circuit 20_1, and a correction circuit 30_1. The first buffer circuit 10 of the digital buffer device 2 is the same as the first buffer circuit of the digital buffer device 1, and... Figure 2 The connection method between the first buffer circuit 10 and the detection circuit 20_1 in the middle is the same as Figure 1 The connection methods between corresponding parts are similar.

[0050] and Figure 1 compared to, Figure 2 The following is an embodiment of the circuit configuration and connection of the detection circuit 20_1 and the correction circuit 30_1 of the digital buffer device 2.

[0051] exist Figure 2In this embodiment, the detection circuit 20_1 includes multiple second buffer circuits 21_1-21_P. The second buffer circuits 21_1-21_P receive multiple different reference signals RS_1-RS_P and generate multiple detection signals DT_1-DT_P to represent variations in the circuit characteristics of the multiple second buffer circuits 21_1-21_P, where P is an integer greater than 1. In this embodiment, the multiple second buffer circuits 21_1-21_P and the first buffer circuit 10 are of the same type of buffer. Therefore, the detection signals DT_1-DT_P can also be used to represent variations in the circuit characteristics of the first buffer circuit 10.

[0052] The calibration circuit 30_1 has a calibration input terminal N31, multiple calibration terminals NC_1-NC_P, and a calibration output terminal N32. The calibration input terminal N31 receives the input signal IN. The multiple calibration terminals NC_1-NC_P respectively receive multiple detection signals DT_1-DT_P. The calibration output terminal N32 is coupled to the buffer output terminal N12 of the first buffer circuit 10. Therefore, the calibration circuit 30_1 is used to calibrate the first buffer circuit 10 based on the input signal IN and the multiple detection signals DT_1-DT_P to generate an output signal OUT.

[0053] As shown above, the digital buffer device 2 uses a detection circuit 20_1 to detect variations in the circuit characteristics of multiple buffer circuits of a certain type (e.g., second buffer circuits 21_1-21_P) to generate detection signals DT_1-DT_P. Since the second buffer circuits 21_1-21_P and the first buffer circuit 10 belong to the same type of buffer, the detection signal DT_1-DT_P represents the variation in the circuit characteristics of the first buffer circuit 10. The digital buffer device 2 uses a correction circuit 30_1 to correct the first buffer circuit 10 based on the input signal IN and the detection signals DT_1-DT_P to generate an output signal OUT. Figure 2 As shown, the buffer output terminal N12 of the first buffer circuit 10 is coupled to the correction output terminal N32 of the correction circuit 30, and can be used as the output terminal of the digital buffer device 2 to generate the output signal OUT.

[0054] Furthermore, the first buffer circuit 10 and the plurality of second buffer circuits 21_1-21_P are buffers of the same type, meaning that these buffer circuits are manufactured with the same or similar structures and / or with the same or similar processes, etc. In one example, the first buffer circuit 10 and the second buffer circuits 21_1-21_P are based on the same buffer circuit architecture and are manufactured in a single wafer using the same or similar processes. Therefore, the second buffer circuits 21_1-21_P exhibit the same or similar circuit characteristic variations as the first buffer circuit 10, such that the detection signals DT_1-DT_P generated by the second buffer circuits 21_1-21_P can be configured to appropriately and accurately represent the circuit characteristic variations of the first buffer circuit 10. Of course, in some embodiments, the second buffer circuits are buffers of the same type, while the first buffer circuits may be implemented with the same or different dimensions.

[0055] In some embodiments, it may be based on Figure 1 The architecture is designed to implement digital buffer devices as inverting buffers, non-inverting buffers, or tri-state digital buffers. In some examples, digital buffer device 1 or 2 can be implemented as a tri-state digital buffer, such as an active high tri-state digital buffer, an active low tri-state digital buffer, or an inverting tri-state digital buffer.

[0056] In some embodiments, it may be based on Figure 1 The architecture implements the digital buffer device as an integrated circuit (IC) or within an IC, as a block or part of an IC. For example, the input buffer based on digital buffer device 1 or 2 can be implemented in a memory device, such as a memory device compliant with DDR series memory technology or low-power DDR (LPDDR) series memory technology.

[0057] In high-data-rate signal transmission scenarios of memory systems based on DDR or even LPDDR series memory technologies, signal quality is crucial to the robustness of the memory system. Signal quality degradation can occur severely at one or more process corners.

[0058] In this regard, the architecture of the digital buffer device 1 can be configured to detect the process corners during the manufacturing of the digital buffer device 1 (and the IC) via the detection circuit 20 of the digital buffer device 1. Based on... Figure 2In one example, the detection circuit 20_1 of the digital buffer device 2 can be implemented to generate detection signals DT_1-DT_P based on multiple different reference signals RS_1-RS_P, which represent multiple input signals at different signal levels (e.g., from low to high levels) within the input range of a buffer circuit of the same type. The detection signals DT_1-DT_P represent the corresponding output signal level (or logic value) of the buffer circuit of that type relative to the multiple input signals at different signal levels. In this way, the detection signals DT_1-DT_P can be used to represent variations in the circuit characteristics of the buffer circuit of that type, and these variations can be associated with process corners.

[0059] Furthermore, the digital buffer device (e.g., digital buffer device 1 or 2) may be configured to correct the first buffer circuit (which may be affected by process, voltage, and temperature (PVT) variations at the corresponding process corner) via a correction circuit (e.g., correction circuit 30 or 30_1) of the digital buffer device (e.g., digital buffer device 1 or 2). The correction circuit (e.g., correction circuit 30 or 30_1) may be configured to determine, based on the input signal IN and the detection signals DT_1-DT_P, whether to correct the first buffer circuit 10 for detected circuit characteristic variations (which correspond to the process corner), and / or determine which of the multiple correction (or compensation) operations provided in the correction circuit (e.g., correction circuit 30 or 30_1) can be enabled to correct the first buffer circuit 10 to generate the output signal OUT. For example, for a specific process corner where the first buffer circuit 10 may output a signal with an unacceptable setup time and / or hold time, a correction circuit (e.g., correction circuit 30 or 30_1) may be configured to enable pull-up and / or pull-down voltages when the specific process corner is detected, to correct the first buffer circuit 10 to generate the output signal OUT. In this way, the output signal OUT can be enhanced, for example, by improving the setup time and / or hold time to meet the requirements.

[0060] Generally, specific process corners that may cause signal quality to fail to meet requirements can be identified through computer simulation or experimentation. When one or more such specific process corners are identified, the circuit designer can configure the digital buffer device (e.g., digital buffer device 1 or 2) to be able to correct (or self-correct) the first buffer circuit 10 by configuring detection circuitry (e.g., detection circuit 20 or 20_1) and correction circuitry (e.g., correction circuit 30 or 30_1).

[0061] The following illustrates an exemplary embodiment of how a digital buffer device can calibrate (or self-calibrate) buffer circuit 10 by configuring a detection circuit (e.g., detection circuit 20 or 20_1) and a calibration circuit (e.g., calibration circuit 30 or 30_1).

[0062] Please refer to Figure 3 Its display is based on Figure 2 An embodiment of a digital buffer device is illustrated with a circuit diagram. For example... Figure 3 As shown, the digital buffer device 2A includes a first buffer circuit 10A, a detection circuit 20_1A, and a correction circuit 30_1A.

[0063] The first buffer circuit 10A has a buffer input terminal N11 for receiving the input signal IN and a buffer output terminal N12. The first buffer circuit 10A includes a logic inverter, which can be manufactured using any standard technology, such as complementary metal-oxide-semiconductor (CMOS) or other technologies. For illustration, the first buffer circuit 10A includes a logic inverter, which is a CMOS logic inverter. For example, the logic inverter includes a transistor M11 (e.g., a P-type metal-oxide-semiconductor field-effect transistor (MOSFET, or PMOS)) and a transistor M12 (e.g., an N-type MOSFET or NMOS), wherein the control terminals (e.g., gates) of transistors M11 and M12 are coupled to the buffer input terminal N11, transistor M11 is coupled between the power supply voltage VDD and the buffer output terminal N12, and transistor M12 is coupled between the buffer output terminal N12 and ground (or other power supply voltage).

[0064] Please refer to Figure 4 illustrated in the diagram Figure 3 The circuit characteristics of that type of buffer circuit (e.g., the first buffer circuit 10A) vary. For example, process corner simulation is performed for the first buffer circuit 10A of this type (e.g., a CMOS logic inverter including transistors M11 and M12), where the input signal VI varies from 0V to 1.2V, and the corresponding output signal VO is simulated for each of multiple process corners. Figure 4 In this diagram, each curve VT1-VT7 represents a portion of a voltage transfer curve corresponding to a specific process corner, and the point on the voltage transfer curve where VO equals VI is a transition threshold of the voltage transfer curve. The intersection of the line LT representing VO = VI with curves VT1-VT7 represents multiple corresponding transition thresholds. Table 1 below lists the process corners and related conditions for curves VT1-VT7.

[0065] Table 1

[0066]

[0067] Please refer to Figure 4 It can be observed that at some process corners, such as those represented by curves VT1 and VT2, the switching thresholds of these curves are closer to the boundary line representing the voltage VIL. The voltage VIL is the maximum input voltage that will be identified as a low input logic level, and the voltage VIL may be required by the IC product or standard technology. In the case of curves VT1 and VT2, if... Figure 5 The input signal VI shown is applied to the logic inverter. When the input signal VI changes from a high level to a low level, the logic inverter may produce an output signal VO with variation (e.g., jitter) on the rising edge.

[0068] Please refer to Figure 4 It can also be observed that in some process corners, such as those represented by curves VT6 and VT7, the switching thresholds of these curves are closer to the boundary line representing voltage VIH. Voltage VIH is the minimum input voltage that will be recognized as a high input logic level, and voltage VIH may be required by the IC product or standard technology. In the case of curves VT6 and VT7, if... Figure 6 The input signal VI shown is applied to the logic inverter. When the input signal VI changes from a low level to a high level, the logic inverter may produce an output signal VO with variation (e.g., jitter) on the falling edge.

[0069] In worse cases, jitter may occur, causing the setup or hold time required for the output signal VO to fail to meet the required standards. In this situation, if the input signal VI is an instruction, clock, or data signal, and the signal quality of the output signal VO (e.g., setup or hold time) is degraded and not corrected, subsequent circuitry coupled to the logic inverter (e.g., internal circuitry of a memory system) may misinterpret the output signal VO, or in the worst case, the subsequent circuitry may fail.

[0070] Therefore, by configuring the detection circuit 20_1A and the correction circuit 30_1A, the circuit designer can design the digital buffer device 2A to be able to correct (or self-correct) the first buffer circuit 10A (e.g., a logic inverter).

[0071] Please refer to again Figure 3The detection circuit 20_1A includes multiple second buffer circuits 21_1A-21_4A. The second buffer circuits 21_1A-21_4A are used to receive multiple different reference signals RS_1-RS_4 and generate multiple detection signals DT_1-DT_4 to represent variations in the circuit characteristics of the multiple second buffer circuits 21_1A-21_4A. In this embodiment, the multiple second buffer circuits 21_1A-21_4A are buffers of the same type as the first buffer circuit 10A, for example... Figure 3 The diagram shows a logic inverter including transistors M11 and M12. Therefore, the detection signals DT_1-DT_4 can also be used to represent variations in the circuit characteristics of the first buffer circuit 10A. Furthermore, a voltage divider 40 can be implemented to generate multiple different reference signals RS_1-RS_4.

[0072] The calibration circuit 30_1A has a calibration input terminal N31, multiple calibration terminals NC_1-NC_4, and a calibration output terminal N32. The calibration input terminal N31 receives the input signal IN. The multiple calibration terminals NC_1-NC_4 respectively receive multiple detection signals DT_1-DT_4. The calibration output terminal N32 is coupled to the buffer output terminal N12 of the first buffer circuit 10A. In this configuration, the calibration circuit 30_1A calibrates the first buffer circuit 10A based on the input signal IN and the multiple detection signals DT_1-DT_4 to generate an output signal OUT.

[0073] In one embodiment, the correction circuit 30_1A may be implemented based on a buffer circuit of the same type as the first buffer circuit 10A. For example, as Figure 3 As shown, the correction circuit 30_1A includes a third buffer circuit 31_1, a correction transistor (e.g., a pull-up transistor) CM1, and a correction transistor (e.g., a pull-down transistor) CM3. The third buffer circuit 31_1 is coupled between correction transistors CM1 and CM3 and is of the same type as the first buffer circuit 10A. Correction transistor CM1 is coupled between the power supply voltage VDD (e.g., 1.2V) and the third buffer circuit 31_1, with the correction terminal NC_1 coupled to the control terminal of correction transistor CM1 to receive the detection signal DT_1. Correction transistor CM3 is coupled between the third buffer circuit 31_1 and ground (or another power supply), with the correction terminal NC_3 coupled to the control terminal of correction transistor CM3 to receive the detection signal DT_3. Of course, in some embodiments, the third buffer circuit is a buffer of the same type, and the first buffer circuit can be implemented with the same or different dimensions.

[0074] For example, such as Figure 3As shown, the correction circuit 30_1A further includes a third buffer circuit 31_2, a correction transistor (e.g., a pull-up transistor) CM2, and a correction transistor (e.g., a pull-down transistor) CM4. The third buffer circuit 31_2 is coupled between the correction transistors CM2 and CM4, and is of the same type as the first buffer circuit 10A. The correction transistor CM2 is coupled between the power supply voltage VDD (e.g., 1.2V) and the third buffer circuit 31_2, and its correction terminal NC_2 is coupled to the control terminal of the correction transistor CM2 to receive the detection signal DT_2. The correction transistor CM4 is coupled between the third buffer circuit 31_2 and ground (or another power supply), and its correction terminal NC_4 is coupled to the control terminal of the correction transistor CM4 to receive the detection signal DT_4.

[0075] In addition, such as Figure 3 As shown, the buffer input terminals of the third buffer circuits 31_1 and 31_2 are used to receive the input signal IN, for example, coupled to the correction input terminal N31, and the buffer output terminals of the third buffer circuits 31_1 and 31_2 are coupled to the correction output terminal N32. In one example, the third buffer circuits 31_1 and 31_2 are connected in parallel between the correction input terminal N31 and the correction output terminal N32.

[0076] Please refer to this again. Figure 4 To correct the first buffer circuit 10A to generate the output signal OUT based on the input signal IN and multiple detection signals DT_1-DT_4, the circuit designer can design different reference signals considering process corners where one or more worse scenarios may occur and corrections need to be performed. Therefore, for example, multiple voltage values ​​V1, V2, V3, V4 (e.g., 0.54V, 0.57V, 0.63V, 0.66V) can be selected and respectively... Figure 4 The dashed lines shown represent the thresholds for initiating correction.

[0077] The voltage values ​​V1-V4, which serve as the thresholds for initiating correction, are discussed below. Please refer to... Figure 4The switching threshold of the aforementioned curve VT1 (or VT2) is close to the boundary line representing voltage VIL, resulting in significant jitter. To reduce jitter, in the case of curve VT1 (or VT2), the digital buffer device 2A needs to correct the first buffer circuit 10A, so that the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A (or the digital buffer device 2A that generates the output signal OUT at the buffer output terminal N12) shifts to the right and approaches the intermediate voltage between voltage VIL and VIH. Voltages VIL and VIH can be set according to the power supply voltage VDD; for example, if VDD = 1.2V, VIL = 0.35*VDD = 0.42V and VIH = 0.65*VDD = 0.78V, the intermediate voltage is 0.6V. Therefore, voltages V1 and V2 (e.g., 0.54V and 0.57V) can be selected as the voltage levels of reference signals RS_1 and RS_2, respectively. If the logic inverter (e.g., the second buffer circuit 21_2A) outputs an output signal VO representing logic 0 when the input signal VI is 0.57V, then the correction circuit 30_1A needs to correct the first buffer circuit 10A, causing the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A to shift to the right. If the logic inverter (e.g., the second buffer circuit 21_1A) outputs an output signal VO representing logic 0 when the input signal VI is 0.54V, then the correction circuit 30_1A needs to significantly correct the first buffer circuit 10A (e.g., in the case of curve VT1 or VT2), causing the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A to shift to the right, as indicated by arrow A1 associated with curve VT2.

[0078] On the other hand, as discussed above, Figure 4The switching threshold of curve VT6 (or VT7) is close to the boundary line representing voltage VIH, resulting in greater jitter. To reduce jitter, digital buffer device 2A needs to correct the first buffer circuit 10A in the case of curve VT6 (or VT7), so that the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A shifts to the left and approaches the intermediate voltage between voltage VIL and VIH. Therefore, voltages V3 and V4 (e.g., 0.63V and 0.66V) can be selected as the voltage levels of reference signals RS_3 and RS_4, respectively. If the logic inverter (e.g., the second buffer circuit 21_3A) outputs an output signal VO representing logic 1 when the input signal VI is 0.63V, then the correction circuit 30_1A needs to correct the first buffer circuit 10A, so that the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A shifts to the left. If the logic inverter (e.g., the second buffer circuit 21_4A) outputs an output signal VO representing logic 1 when the input signal VI is 0.66V, then the correction circuit 30_1A needs to significantly correct the first buffer circuit 10A (e.g., in the case of curve VT6 or VT7), so that the switching threshold of the voltage transfer curve of the corrected first buffer circuit 10A is shifted to the left, as indicated by arrow A2 associated with curve VT6.

[0079] Furthermore, in some cases, if the logic inverter (e.g., the second buffer circuits 21_1A-21_4A) exhibits a voltage transfer curve as represented by curves VT3, VT4, or VT5, it may not be necessary for the digital buffer device 2A to maintain the voltage transfer curve and perform correction.

[0080] From the above about Figure 4 The need for calibration of the digital buffer device 2A can be derived from the process corner simulation of the input buffer circuit 10A (e.g., a logic inverter). Furthermore, voltage values ​​V1-V4 can be determined and associated with a threshold used to initiate calibration. To achieve calibration, reference signals RS_1-RS_4 can be set to voltage values ​​V1-V4 respectively, causing the detection circuit 20_1A to generate corresponding detection signals DT_1-DT_4 to indicate variations in the circuit characteristics of this type of buffer circuit, wherein the second buffer circuits 21_1A-21_4A of the detection circuit 20_1A are of the same type as the first buffer circuit 10A. The calibration circuit 30_1A can be implemented as including multiple third buffer circuits (e.g., third buffer circuits 31_1 and 31_2) and multiple calibration transistors (e.g., calibration transistors CM1-CM4). Therefore, in view of the above... Figure 4The correction circuit 30_1A is capable of performing correction based on the input signal IN and the detection signals DT_1-DT_4. The implementation of correction by the digital buffer device 2A can be summarized in Table 2 below. In Table 2, the circuit characteristic variations can be divided into 5 cases, and the digital buffer device 2A provides 5 correction modes, each corresponding to one of the correction operations provided by the correction circuit 30_1A. Furthermore, in Table 2, the on / off states of the detection signals DT_1-DT_4, the reference signals RS_1-RS_4, and the correction transistors CM1-CM4 are associated and indicated, where "L" represents logic 0 or a low logic level, and "H" represents logic 1 or a high logic level.

[0081] Table 2

[0082]

[0083] Referring to Table 2, when the detection circuit 20_1A outputs detection signals DT_1-DT_4 corresponding to logic values ​​L, L, L, L respectively, it indicates that the switching threshold of the voltage transfer curve of the first buffer circuit 10A is closer to the boundary line representing voltage VIL. In this case, the detection circuit 20_1A is configured to be in correction mode 1 according to the detection signals DT_1-DT_4, wherein correction transistors CM1 and CM2 will be turned on when correction transistors CM3 and CM4 are turned off. When the input signal IN applied to the first buffer circuit 10A, the third buffer circuits 31_1 and 31_2 changes from a high voltage level to a low voltage level, transistors M11 of the first buffer circuit 10A, M31 of the third buffer circuit 31_1 and M33 of the third buffer circuit 31_2 are turned on, while transistors M12 of the first buffer circuit 10A, M32 of the third buffer circuit 31_1 and M34 of the third buffer circuit 31_2 are turned off. Since the buffer output terminal N12 of the first buffer circuit 10A is coupled to the buffer output terminals of the third buffer circuits 31_1 and 31_2 through the correction output terminal N32, after the input signal IN changes from high level to low level, the pull-up voltage generated by the conduction of correction transistors CM1 and CM2 can be applied to the buffer output terminal N12, thereby causing the voltage level of the buffer output terminal N12 to rise faster and reducing the jitter of the rising edge of the output signal OUT. Conversely, when the input signal IN changes from low voltage level to high voltage level, transistor M11 of the first buffer circuit 10A, transistor M31 of the third buffer circuit 31_1, and transistor M33 of the third buffer circuit 31_2 will be turned off when transistor M12 of the first buffer circuit 10A is turned on. At the same time, because correction transistors CM3 and CM4 are turned off in correction mode 1, transistors M32 of the third buffer circuit 31_1 and M34 of the third buffer circuit 31_2 are turned off. In this way, when the input signal IN changes from a low voltage level to a high voltage level, the detection circuit 20_1A will not perform a correction operation in correction mode 1. Overall, the detection circuit 20_1A performs a correction operation in correction mode 1 after the input signal IN changes from a high voltage level to a low voltage level. Therefore, the voltage transfer curve of the corrected first buffer circuit 10A can be shifted to the right to obtain a positive voltage value (e.g., approximately 60mV).

[0084] Referring to Table 2, when the detection circuit 20_1A outputs detection signals DT_1-DT_4 corresponding to logic values ​​H, L, L, and L respectively, it indicates that the switching threshold of the voltage transfer curve of the first buffer circuit 10A is close to the boundary line representing voltage VIL. In this case, the detection circuit 20_1A is configured to be in correction mode 2 according to the detection signals DT_1-DT_4, in which the correction transistor CM2 will be turned on when the correction transistors CM1, CM3, and CM4 are turned off. Therefore, because the correction transistors CM1 and CM3 are turned off in correction mode 2, the third buffer circuit 31_1 is turned off. When the input signal IN changes from a high voltage level to a low voltage level, the transistor M11 of the first buffer circuit 10A and the transistor M33 of the third buffer circuit 31_2 will be turned on when the transistors M12 of the first buffer circuit 10A and M34 of the third buffer circuit 31_2 are turned off. Since the buffer output terminal N12 of the first buffer circuit 10A is coupled to the buffer output terminals of the third buffer circuits 31_1 and 31_2 through the correction output terminal N32, after the input signal IN changes from high to low, the pull-up voltage generated by the conduction of the correction transistor CM2 can be applied to the buffer output terminal N12, thereby causing the voltage level of the buffer output terminal N12 to rise faster and reducing the jitter of the rising edge of the output signal OUT. Conversely, when the input signal IN changes from low to high voltage, the transistor M11 of the first buffer circuit 10A and the transistor M33 of the third buffer circuit 31_2 will be turned off when the transistor M12 of the first buffer circuit 10A is turned on. At the same time, because the correction transistor CM4 is turned off in correction mode 2, the third buffer circuit 31_2 is turned off. In this way, when the input signal IN changes from low to high voltage, the detection circuit 20_1A will not perform correction operation in correction mode 2. Overall, the detection circuit 20_1A performs a correction operation in correction mode 2 after the input signal IN changes from a high voltage level to a low voltage level. Therefore, the voltage transfer curve of the corrected first buffer circuit 10A can be shifted to the right to obtain a positive voltage value (e.g., about 30mV).

[0085] Please refer to Table 2. When the detection circuit 20_1A outputs detection signals DT_1-DT_4 corresponding to logic values ​​H, H, L, and L respectively, this indicates that the voltage transfer curve of the first buffer circuit 10A is... Figure 3The curves VT3, VT4, or VT5 shown represent the same normal behavior. In this case, the detection circuit 20_1A is configured in correction mode 3 according to the detection signals DT_1-DT_4, in which correction transistors CM1, CM2, CM3, and CM4 are all turned off. Therefore, in correction mode 3, the third buffer circuits 31_1 and 31_2 are turned off. In correction mode 3, the detection circuit 20_1A does not perform a correction operation (or special correction operation) for the first buffer circuit 10A. In other words, in correction mode 3, the detection circuit 20_1A performs an internal correction operation to maintain the voltage transfer curve of the first buffer circuit 10A. Therefore, in correction mode 3, the voltage transfer curve of the first buffer circuit 10A is maintained.

[0086] Referring to Table 2, when the detection circuit 20_1A outputs detection signals DT_1-DT_4 corresponding to logic values ​​H, H, H, and L respectively, it indicates that the switching threshold of the voltage transfer curve of the first buffer circuit 10A is close to the boundary line representing voltage VIH. In this case, the detection circuit 20_1A is configured to be in correction mode 4 according to the detection signals DT_1-DT_4, in which the correction transistor CM3 will be turned on when the correction transistors CM1, CM2, and CM4 are turned off. Therefore, because the correction transistors CM2 and CM4 are turned off in correction mode 4, the third buffer circuit 31_2 is turned off. When the input signal IN changes from a high voltage level to a low voltage level, the transistor M11 of the first buffer circuit 10A is turned on. The third buffer circuit 31_1 is turned off because the transistor M31 of the third buffer circuit 31_1 is turned off due to the correction transistor CM1 being turned off in correction mode 4, and the transistor M32 of the third buffer circuit 31_1 is turned off after the input signal IN changes from a high voltage level to a low voltage level. In this way, when the input signal IN changes from a high voltage level to a low voltage level, the detection circuit 20_1A will not perform a correction operation in correction mode 4. Conversely, when the input signal IN changes from a low voltage level to a high voltage level, transistor M11 of the first buffer circuit 10A and transistor M31 of the third buffer circuit 31_1 will be turned off when transistors M12 of the first buffer circuit 10A and M34 of the third buffer circuit 31_1 are turned on. Since the buffer output terminal N12 of the first buffer circuit 10A is coupled to the buffer output terminals of the third buffer circuits 31_1 and 31_2 through the correction output terminal N32, after the input signal IN changes from a low level to a high level, the pull-down voltage generated by the conduction of the correction transistor CM3 can be applied to the buffer output terminal N12, thereby causing the voltage level of the buffer output terminal N12 to drop faster and reducing the jitter of the falling edge of the output signal OUT. Overall, the detection circuit 20_1A performs a correction operation in correction mode 4 after the input signal IN changes from a low voltage level to a high voltage level. Therefore, the voltage transfer curve of the corrected first buffer circuit 10A can be shifted to the left to obtain a positive voltage value (e.g., about 30mV).

[0087] Referring to Table 2, when the detection circuit 20_1A outputs detection signals DT_1-DT_4 corresponding to logic values ​​H, H, H, and H respectively, it indicates that the switching threshold of the voltage transfer curve of the first buffer circuit 10A is closer to the boundary line representing voltage VIH. In this case, the detection circuit 20_1A is configured to be in correction mode 5 according to the detection signals DT_1-DT_4, wherein correction transistors CM1 and CM2 will be turned off when correction transistors CM3 and CM4 are turned on. When the input signal IN changes from a high voltage level to a low voltage level, transistor M11 of the first buffer circuit 10A will be turned on when transistor M12 of the first buffer circuit 10A is turned off. Meanwhile, the third buffer circuits 31_1 and 31_2 are disconnected because transistor M31 of the third buffer circuit 31_1 and transistor M33 of the third buffer circuit 31_2 are disconnected due to the disconnection of correction transistors CM1 and CM2 in correction mode 5. Transistors M32 of the third buffer circuit 31_1 and M34 of the third buffer circuit 31_2 are disconnected after the input signal IN changes from a high voltage level to a low voltage level. Therefore, when the input signal IN changes from a high voltage level to a low voltage level, the detection circuit 20_1A will not perform a correction operation in correction mode 5. Conversely, when the input signal IN changes from a low voltage level to a high voltage level, transistors M11 of the first buffer circuit 10A, M31 of the third buffer circuit 31_1, and M33 of the third buffer circuit 31_2 will be disconnected when transistors M12 of the first buffer circuit 10A, M32 of the third buffer circuit 31_1, and M34 of the third buffer circuit 31_2 are turned on. Since the buffer output terminal N12 of the first buffer circuit 10A is coupled to the buffer output terminals of the third buffer circuits 31_1 and 31_2 through the correction output terminal N32, after the input signal IN changes from low to high, the pull-down voltage generated by the conduction of the correction transistors CM3 and CM4 can be applied to the buffer output terminal N12, thereby causing the voltage level of the buffer output terminal N12 to drop faster and reducing the jitter of the falling edge of the output signal OUT. Overall, the detection circuit 20_1A performs a correction operation in correction mode 5 after the input signal IN changes from low to high voltage. Therefore, the voltage transfer curve of the first buffer circuit 10A after correction can shift to the left to obtain a positive voltage value (e.g., about 60mV).

[0088] In implementations of the digital buffer device 2A, the number of third buffer circuits is determined by the designer for the calibration purpose. In some embodiments, one, two, or more third buffer circuits may be used. Furthermore, the designer may determine the number of calibration transistors (e.g., pull-up or pull-down transistors or other circuit components with the same function) depending on the calibration purpose. For example, calibration transistors CM1-CM4 are optional, and the calibration circuit 30_1A may include only one, two, or three calibration transistors. In some examples based on the digital buffer device 2A, the calibration circuit 30_1A may be implemented as including three or more third buffer circuits and having more than four calibration transistors, while the detection circuit 20_1A may be implemented to provide corresponding detection signals for selectively controlling the calibration transistors for the calibration purpose, similar to the above-described method for... Figure 3 The example illustrates this approach.

[0089] Furthermore, the digital buffer device (e.g., 1, 2, or 2A) can be further implemented with a power-saving mechanism for the detection circuitry. Please refer to [reference needed]. Figure 7 Another embodiment of the detection circuit (e.g., detection circuit 20, 20_1, or 20_1A) is illustrated by a block diagram. Compared to detection circuit 20, 20_1, or 20_1A, Figure 7 The detection circuit 20_2 further includes a transmission gate and a storage circuit (e.g., a latch) for power saving.

[0090] like Figure 7 As shown, the detection circuit 20_2 includes multiple second buffer circuits 21_1-21_P, multiple transmission gates TG_1-TG_P, and a storage circuit including multiple latches LH_1-LH_P. Each of the multiple second buffer circuits 21_1-21_P is coupled to a corresponding transmission gate and latch. The multiple second buffer circuits 21_1-21_P are used to receive multiple different reference signals RS_1-RS_P respectively and generate multiple detection signals DT_1-DT_P to represent the circuit characteristic variations of the multiple second buffer circuits 21_1-21_P, where P is an integer greater than 1. The multiple second buffer circuits 21_1-21_P are buffers of the same type as the first buffer circuit 10. Therefore, the detection signals DT_1-DT_P can also be used to represent the circuit characteristic variations of the first buffer circuit 10. The second buffer circuits 21_1-21_P generate their respective output signals (e.g., detection signals DT_1-DT_P), and when a reset signal is applied to the transmission gates TG_1-TG_P, such as Figure 7The lower half of the waveform shows the output signals of the transmission gates TG_1-TG_P when they are in an asserted state (e.g., high voltage level or logic 1). When the enable signal EN applied to the latches LH_1-LH_P is in an asserted state (e.g., high voltage level or logic 1), the output signals of the second buffer circuits 21_1-21_P are stored by the latches LH_1-LH_P, and the latches LH_1-LH_P output detection signals DT_1-DT_P. After the latches LH_1-LH_P output the detection signals DT_1-DT_P and the correction circuit (e.g., 30_1 or 30_1A) performs a correction operation based on the detection signals DT_1-DT_P, a device that generates multiple reference signals RS_1-RS_P (e.g., ...) Figure 3 The voltage divider 40 in the circuit can be disconnected, and then the second buffer circuit 21_1-21_P can also be disconnected. For example, as Figure 7 As shown, the switching device SW is coupled between the power supply voltage VDD and the voltage divider 40_1. Figure 7 The voltage divider 40_1 in the middle can be according to Figure 3 This is achieved using a voltage divider 40. The switching device SW is controlled by a reset signal RST. For example, after the reset signal RST experiences both a rising edge and a falling edge, as... Figure 7 As shown in the lower half of the waveform, the switching element SW can be set to open, thus cutting off the voltage divider 40_1, and also disconnecting the second buffer circuits 21_1-21_P. In this way, Figure 7 In addition to performing the detection circuit 20_2 in the middle, Figure 2 In addition to similar functions to the detection circuit 20, it can further save power. For example, the switching device SW can be implemented by logic circuitry.

[0091] exist Figure 7 In the above embodiments, the transmission gate is optional and the latch can be coupled to a second buffer circuit with or without the transmission gate, or other implementations can be applied to store the detection signal. Furthermore, the functions of the switching device SW and the voltage divider 40_1 can be modified or implemented through other suitable circuit configurations.

[0092] Furthermore, in the above embodiments, for control, power saving, or other purposes, the buffer circuit (e.g., the first and second buffer circuits illustrated above) can be implemented as an inverted tri-state buffer circuit. For example, some logic circuitry can be added to the buffer circuit (e.g., the first and second buffer circuits illustrated above) to enable or disable the buffer circuitry via one or more control signals. For example, some logic circuitry can be added to the buffer circuit (e.g., the first and second buffer circuits illustrated above) to enable or disable the operation of passing the power supply voltage to the buffer circuitry via one or more control signals to save power.

[0093] In a further embodiment, the input buffer for receiving the clock enable signal can be implemented as a digital buffer device (e.g., 1, 2, or 2A) to meet the requirements of Double Data Rate (DDR) series memory standards (e.g., one of DDR1, DDR2, DDR3, DDR4, LPDDR1, LPDDR2, LPDDR3, or LPDDR4). The digital buffer device can be implemented as an inverting buffer, with the clock enable signal used as the input signal IN. Of course, the implementation of the invention is not limited to the above examples.

[0094] As described above, embodiments of the digital buffer device are capable of detecting variations in the circuit characteristics of a plurality of buffer circuits of one type included in the digital buffer device, generating one or more detection signals, and correcting one of the plurality of buffer circuits based on the input signal and the one or more detection signals to generate an output signal. Therefore, the signal quality of the output signal of the digital buffer device can be enhanced. In some embodiments, the digital buffer device may further be implemented with a power-saving mechanism.

[0095] Although the invention has been described by way of specific embodiments, those skilled in the art can make various modifications, combinations and variations thereto without departing from the scope and spirit of the invention as disclosed in the claims.

Claims

1. A digital buffer device with self-correction, characterized in that, include: The first buffer circuit has a buffer input terminal for receiving input signals and a buffer output terminal; A detection circuit includes a plurality of second buffer circuits for receiving a plurality of different reference signals and generating a plurality of detection signals for representing variations in the circuit characteristics of the plurality of second buffer circuits, wherein the plurality of second buffer circuits are buffers of the same type as the first buffer circuit. as well as A correction circuit having a correction input for receiving the input signal and a correction output coupled to the output of the buffer, the correction circuit being used to correct the first buffer circuit to generate an output signal based on the input signal and the plurality of detection signals, wherein the buffer output serves as the output of the digital buffer device.

2. The digital buffer device according to claim 1, characterized in that, The correction circuit is used to correct the first buffer circuit to generate the output signal based on the input signal and the plurality of detection signals.

3. The digital buffer device according to claim 2, characterized in that, The multiple different reference signals correspond to multiple voltage values ​​between the maximum input voltage and the minimum input voltage, wherein the maximum input voltage is identified as a low input logic level of the digital buffer device, and the minimum input voltage is identified as a high input logic level of the digital buffer device.

4. The digital buffer device according to claim 2, characterized in that, The correction circuit also has multiple correction terminals for receiving the plurality of detection signals.

5. The digital buffer device according to claim 1, characterized in that, The correction circuit includes a third buffer circuit and a plurality of correction transistors, wherein the third buffer circuit is coupled to the plurality of correction transistors and is used to receive the input signal, the third buffer circuit is coupled to the correction output terminal, and the third buffer circuit and the plurality of correction transistors are used to correct the first buffer circuit according to the input signal and the plurality of detection signals to generate the output signal.

6. The digital buffer device according to claim 5, characterized in that, The third buffer circuit is a buffer of the same type as the first buffer circuit.

7. The digital buffer device according to claim 1, characterized in that, The correction circuit includes a plurality of third buffer circuits and a plurality of correction transistors, wherein each of the plurality of third buffer circuits is coupled to at least one corresponding of the plurality of correction transistors and is used to receive the input signal, each of the plurality of third buffer circuits is coupled to the correction output terminal, and the plurality of third buffer circuits and the plurality of correction transistors are used to correct the first buffer circuit to generate the output signal based on the input signal and the plurality of detection signals.

8. The digital buffer device according to claim 7, characterized in that, The plurality of third buffer circuits are buffers of the same type as the first buffer circuit.

9. The digital buffer device according to claim 1, characterized in that, The detection circuit further includes a storage circuit, wherein the storage circuit is coupled to the plurality of second buffer circuits; the plurality of second buffer circuits are configured to be turned off to save power after the storage circuit stores the plurality of detection signals corresponding to the plurality of second buffer circuits.

10. The digital buffer device according to claim 9, characterized in that, The detection circuit also includes a voltage divider for generating the plurality of different reference signals, wherein the voltage divider is configured to be turned off to save power after the storage circuit stores the plurality of detection signals corresponding to the plurality of second buffer circuits.

11. The digital buffer device according to claim 1, characterized in that, The first buffer circuit includes a logic inverter.

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