Stacked memory device and word line driver

Abstract

The present disclosure provides a stacked memory device and a word line driver thereof. The word line driver includes a first word line signal generation circuit, a second word line signal generation circuit, a first voltage generator, and a second voltage generator. The first word line signal generation circuit generates a first word line signal by selecting one of a first voltage and a second voltage according to a control signal. The second word line signal generation circuit generates a second word line signal by selecting one of a third voltage and a fourth voltage according to the control signal. The first voltage generator provides the second voltage. The second voltage generator provides the fourth voltage. The first voltage generator and the second voltage generator are independent of each other.

Description

Technical Field

[0001] This disclosure relates to a memory device and a word line driver, and more particularly to a stacked memory device and a word line driver capable of performing an erase operation on a selected word line memory cell. Background Technology

[0002] With the increasing prevalence of electronic products today, providing efficient data storage media within these products is an important issue.

[0003] In modern flash memory, updating data requires erasing the memory cell first, followed by reprogramming. Due to architectural limitations, erasing a memory cell in flash memory often requires erasing an entire block of cells, rather than erasing a small number of cells. This causes numerous inconveniences when updating data. For example, in performing calculations using artificial intelligence algorithms, small-scale data updates are frequently required. Therefore, the block-only erasure characteristic significantly reduces the efficiency of flash memory. Summary of the Invention

[0004] This disclosure provides a stacked memory device and its word line driver, which can perform an erase operation on a selected word line memory cell.

[0005] The word line driver disclosed herein includes a first word line signal generation circuit, a second word line signal generation circuit, a first voltage generator, and a second voltage generator. The first word line signal generation circuit drives a first word line and generates a first word line signal by selecting one of a first voltage and a second voltage according to a control signal. The second word line signal generation circuit drives a second word line and generates a second word line signal by selecting one of a third voltage and a fourth voltage according to a control signal. The first voltage generator is coupled to the first word line signal generation circuit to provide a second voltage. The second voltage generator is coupled to the first word line signal generation circuit to provide a fourth voltage. The first and second voltage generators are independent of each other.

[0006] According to one embodiment of this disclosure, the word line driver further includes a third voltage generator and a fourth voltage generator. The third voltage generator is coupled to the first word line signal generation circuit to provide a first voltage. The fourth voltage generator is coupled to the second word line signal generation circuit to provide a third voltage.

[0007] The stacked memory device disclosed herein includes a word line driver, a first memory cell array, and a second memory cell array. The first and second memory cell arrays are respectively coupled to multiple first word lines and multiple second word lines. The word line driver includes multiple first word line signal generation circuits, multiple second word line signal generation circuits, a first voltage generator, and a second voltage generator. The first word line signal generation circuits are used to drive the first word lines respectively, and generate a first word line signal by selecting one of a first voltage and a second voltage according to multiple first control signals. The second word line signal generation circuits are used to drive the second word lines respectively, and generate a second word line signal by selecting one of a third voltage and a fourth voltage according to multiple second control signals. A voltage generator is coupled to the first word line signal generation circuit to provide a second voltage. The second voltage generator is coupled to the first word line signal generation circuit to provide a fourth voltage, wherein the first and second voltage generators are independent of each other.

[0008] Based on the above, the word line driver of this disclosure can provide independent word line voltages for different word lines through different word line signal generation circuits. In this way, memory cells corresponding to different word lines in the memory device can be erased independently. That is, the erasure operation of the memory device in the embodiments of this disclosure does not need to be performed on the entire memory cell array, but can be performed on selected word line memory cells, effectively improving the data access performance of the memory device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a word line driver according to an embodiment of the present disclosure.

[0010] Figure 2 For this disclosure Figure 1 A schematic diagram of the implementation of the word line signal generation circuits 110 and 120 in the embodiment.

[0011] Figure 3 This is a schematic diagram of a stacked memory device according to an embodiment of the present disclosure.

[0012] Figure 4 This is a schematic diagram illustrating the read operation of a stacked memory device according to an embodiment of the present disclosure.

[0013] Figure 5 This is a schematic diagram illustrating the programming operation of a stacked memory device according to an embodiment of the present disclosure.

[0014] Figure 6 This is a schematic diagram of the block erasure operation of a stacked memory device according to an embodiment of the present disclosure.

[0015] Figure 7This is a schematic diagram of a selected word line erasure operation of a stacked memory device according to an embodiment of the present disclosure.

[0016] Figure 8 as well as Figure 9 These are schematic diagrams illustrating the erasure methods of one or more memory cells during the selected word line erasure operation in embodiments of this disclosure.

[0017] Figure 10 This is a schematic diagram illustrating an arbitrary bit-line erasure operation of a memory device according to an embodiment of the present disclosure.

[0018] Explanation of reference numerals in the attached figures

[0019] 100, 310: Word line drivers

[0020] 110, 120, 3111~311M, 3121~312M, 10111~10113: Word line signal generation circuit

[0021] 131~134, 3131~3134, 10131~10134: Voltage generator

[0022] 300: Stacked memory device

[0023] BLT: Bit Line Switch

[0024] CSL: Common Source Line

[0025] GBL: Common Line

[0026] HV, LV: Operating voltage

[0027] S1~S4: Selection signals

[0028] MCS: Select memory cell

[0029] MP1, MN1, MN2: Transistors

[0030] PG, PG[1]~PG[M]: Control signals

[0031] PG[1]B~PG[M]B: Inverted signal

[0032] SBLT: Select bit line switch

[0033] SLT: Source Wire Switch

[0034] SLT1, SLT2: Memory Cell Array

[0035] SSLT: Select source line switch

[0036] V1, V2, V3, V4: Voltage

[0037] WL1, WL2, WL11~WL1M, WL21~WL2M: Word lines

[0038] WLS1, WLS2: Word line signals Detailed Implementation

[0039] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a word line driver according to an embodiment of the present disclosure. The word line driver 100 includes word line signal generation circuits 110 and 120 and voltage generators 131 to 134. The word line signal generation circuit 110 is used to drive word line WL1. The word line signal generation circuit 110 can generate a word line signal WLS1 on word line WL1 according to a control signal PG. The word line signal generation circuit 110 also receives voltages V1 and V2, and generates the word line signal WLS1 according to one of voltages V1 and V2 according to the control signal PG. In addition, the word line signal generation circuit 120 is used to drive word line WL2. The word line signal generation circuit 120 can generate a word line signal WLS2 on word line WL2 according to the control signal PG. The word line signal generation circuit 120 also receives voltages V3 and V4, and generates the word line signal WLS2 according to one of voltages V3 and V4 according to the control signal PG.

[0040] Voltage generators 131 and 132 are coupled to word line signal generation circuit 110. Voltage generators 131 and 132 generate voltages V1 and V2, respectively. Voltage generators 131 and 132 can adjust the voltage values ​​of V1 and V2 according to different types of access operations performed by the memory device. Similarly, voltage generators 133 and 134 are coupled to word line signal generation circuit 120. Voltage generators 134 and 134 generate voltages V3 and V4, respectively, and can adjust the voltage values ​​of V3 and V4 according to different types of access operations performed by the memory device.

[0041] It is worth noting that the voltage value of V1 generated by voltage generator 131 can be independent of the voltage value of V3 generated by voltage generator 133. Similarly, the voltage value of V2 generated by voltage generator 132 can be independent of the voltage value of V4 generated by voltage generator 134.

[0042] In this embodiment, word line WL1 is disposed in memory cell array SLT1, while word line WL2 can be disposed in another memory cell array SLT2. Of course, memory cell arrays SLT1 and SLT2 may also have other word lines. Figure 1This is merely an illustrative example; there is no fixed limit to the number of word lines in a single memory cell array (SLT1, SLT2).

[0043] Please note that the voltage values ​​of the word line signals WLS1 and WLS2 on individual word lines WL1 and WL2 can be set independently. Therefore, in this embodiment of the disclosure, an erase operation can be performed on one or more memory cells on any word line (e.g., word line WL1 or WL2) in the memory cell arrays SLT1 and SLT2. This increases the degree of freedom in writing data to memory cells in the memory device and improves the efficiency of data access.

[0044] Please refer to the following: Figure 2 , Figure 2 For this disclosure Figure 1 A schematic diagram of an embodiment of the word line signal generation circuits 110 and 120. Word line signal generation circuit 110 includes transistors MP1, MN1, and MN2. A first terminal of transistor MP1 receives voltage V1; a control terminal of transistor MP1 receives a control signal PG; a second terminal of transistor MP1 is coupled to word line WL1 and used to provide word line signal WLS1. A first terminal of transistor MN1 is coupled to the second terminal of transistor MP1; a control terminal of transistor MN1 receives the control signal PG; and a second terminal of transistor MN1 receives voltage V2. Additionally, a first terminal of transistor MN2 receives voltage V1; a control terminal of transistor MN2 receives the inverted signal PGB of the control signal PG; and a second terminal of transistor MN2 is coupled to word line WL1.

[0045] The word line signal generation circuit 120 includes transistors MP2, MN3, and MN4. The circuit architecture of the word line signal generation circuit 120 is the same as that of the word line signal generation circuit 110, and will not be described in detail here.

[0046] In this embodiment, transistors MP1 and MP2 are P-type transistors, and transistors MN1 to MN4 are N-type transistors.

[0047] Regarding the operation of word line signal generation circuits 110 and 120, taking word line signal generation circuit 110 as an example, when voltage V1 has a relatively high voltage value, and when the control signal PG is at a low logic level, transistor MP1 can be turned on and transmit voltage V1 to generate word line signal WLS1 (at this time, transistor MN1 is turned off). When voltage V1 has a relatively low voltage value, and when the control signal PG is at a low logic level, transistor MN2 can be turned on and transmit voltage V1 to generate word line signal WLS1. Alternatively, when the control signal PG is at a high logic level, both transistors MP1 and MN2 can be turned off, and transistor MN1 can be turned on and transmit voltage V2 to generate word line signal WLS1. In this embodiment, the voltage value of V2 can be equal to or less than the voltage value of V1.

[0048] On the other hand, transistors MP1, MN1, and MN2 can be formed on a substrate having a triple-well region. In this embodiment, transistor MP1 can be formed on an N-type well region NW, and transistors MN1 and MN2 can be formed on a P-type well region PWI. In this way, word line signal generation circuits 110 and 120 can provide negative voltages V2 and V4 to generate word line signals WLS1 and WLS2, respectively.

[0049] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of a stacked memory device according to an embodiment of the present disclosure. The stacked memory device 300 includes a word line driver 310 and memory cell arrays SLT1 and SLT2. The word line driver 310 includes word line signal generation circuits 3111-311M, 3121-312M, and voltage generators 3131-3134. The word line signal generation circuits 3111-311M are respectively coupled to word lines WL11-WL1M, and the word line signal generation circuits 3121-312M are respectively coupled to word lines WL21-WL2M. Word lines WL11-WL1M are coupled to memory cell array SLT1, and word lines WL21-WL2M are coupled to memory cell array SLT2.

[0050] On the other hand, word line signal generation circuits 3111 to 311M respectively receive control signals PG[1] to PG[M], and respectively receive the inverted signals PG[1]B to PG[M]B of the control signals PG[1] to PG[M]. Word line signal generation circuits 3111 to 311M select one of voltages V1 and V2 based on the control signals PG[1] to PG[M] and their inverted signals PG[1]B to PG[M]B to generate word line signals to drive word lines WL11 to WL1M respectively, so as to perform corresponding data access operations for the memory cell array SLT1. Word line signal generation circuits 3121 to 312M respectively receive control signals PG[1] to PG[M], and respectively receive the inverted signals PG[1]B to PG[M]B of the control signals PG[1] to PG[M]. The word line signal generation circuits 3121 to 312M select one of voltages V3 and V4 based on the control signals PG[1] to PG[M] and their inverse signals PG[1]B to PG[M]B to generate word line signals to drive word lines WL21 to WL2M respectively, so as to perform corresponding data access operations for the memory cell array SLT2.

[0051] Voltage generators 3131 to 3134 can be voltage shifters and receive selection signals S1 to S4 respectively. Taking voltage generator 3131 as an example, voltage generator 3131 can determine the voltage value of the generated voltage V1 based on the logic level of selection signal S1. For example, voltage generator 3131 can receive an operating voltage HV with a relatively high voltage value and an operating voltage LV with a relatively low voltage value. When selection signal S1 is at a high logic level, voltage generator 3131 can generate a voltage V1 with the same voltage value as operating voltage HV (relatively high voltage value), and conversely, when selection signal S1 is at a low logic level, voltage generator 3131 can generate a voltage V1 with the same voltage value as operating voltage LV (relatively low voltage value).

[0052] The following is for reference Figure 4 , Figure 4 This is a schematic diagram illustrating the read operation of a stacked memory device according to an embodiment of the present disclosure. Figure 3 The hardware architecture of the stacked memory device 300 is used as an example. Figure 4 In the reading operation, voltage generators 3131 and 3132 generate voltages V1 and V2 with the same voltage value, for example, 0 volts. Voltage generator 3133 generates voltage V3 with the reading voltage value, for example, 7.5 volts. Voltage generator 3134 generates voltage V4, for example, 0 volts.

[0053] In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, and 1 respectively, and their inverted signals PG[1]B~PG[3]B can be logic levels 1, 0, and 0 respectively. Based on the voltage values ​​of voltages V1~V4, the control signals PG[1]~PG[3] and their inverted signals PG[1]B~PG[3]B, the word line signal generation circuits 3111~3113 can generate word line signals of 0 volts to drive word lines WL11~WL13, and the word line signal generation circuits 3121~3123 can generate word line signals of 7.5, 0, and 0 volts respectively to drive word lines WL21~WL23. In this way, word line WL21 can be the selected word line, and the other word lines WL11~WL13, WL22 and WL23 are unselected word lines.

[0054] Please refer to the following: Figure 5 , Figure 5 This is a schematic diagram illustrating the programming operation of a stacked memory device according to an embodiment of the present disclosure. Similarly, Figure 3 The hardware architecture of the stacked memory device 300 is used as an example. Figure 5 In the programming operation, voltage generators 3131 and 3132 generate voltages V1 and V2 with the same voltage value, for example, 0 volts. Voltage generator 3133 generates voltage V3 with a programmed voltage value, for example, 13 volts. Voltage generator 3134 generates voltage V4, for example, 0 volts.

[0055] In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, and 1 respectively, and their inverted signals PG[1]B~PG[3]B can be logic levels 1, 0, and 0 respectively. Based on the voltage values ​​of voltages V1~V4, the control signals PG[1]~PG[3] and their inverted signals PG[1]B~PG[3]B, the word line signal generation circuits 3111~3113 can generate word line signals of 0 volts to drive word lines WL11~WL13, and the word line signal generation circuits 3121~3123 can generate word line signals of 13, 0, and 0 volts respectively to drive word lines WL21~WL23. In this way, word line WL21 can be the selected word line, and the other word lines WL11~WL13, WL22 and WL23 are unselected word lines.

[0056] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram illustrating the block erasure operation of a stacked memory device according to an embodiment of the present disclosure. Similarly, Figure 3 The hardware architecture of the stacked memory device 300 is used as an example. Figure 6In the block erasure operation, voltage generator 3131 generates a voltage V1 with a value of, for example, 5 volts, and voltage generator 3132 generates a voltage V2 with a value of, for example, -8 volts. Voltage generator 3133 generates a voltage V3 with an erasure voltage value of, for example, -8 volts. Voltage generator 3134 also generates a voltage V4 with an erasure voltage value.

[0057] In addition, the control signals PG[1]~PG[3] can be logic levels 0, 0, 0 respectively, and their inverse signals PG[1]B~PG[3]B can be logic levels 1, 1, 1 respectively. Based on the voltage values ​​of voltages V1~V4, the control signals PG[1]~PG[3] and their inverse signals PG[1]B~PG[3]B, the word line signal generation circuits 3111~3113 can generate word line signals of 5 volts each to drive word lines WL11~WL13, and the word line signal generation circuits 3121~3123 can generate word line signals of -8 volts each to drive word lines WL21~WL23. In this way, word lines WL21~W23 can be selected word lines, and the remaining word lines WL11~WL13 are unselected word lines. In other words, all memory cells in memory cell array SLT2 can be selected for row-based erasure, while all memory cells in memory cell array SLT1 are inhibited and not erased.

[0058] Please refer to the following: Figure 7 , Figure 7 This is a schematic diagram illustrating a selected word line erase operation of a stacked memory device according to an embodiment of the present disclosure. Similarly, Figure 3 The hardware architecture of the stacked memory device 300 is used as an example. Figure 7 In the selected word line erase operation, voltage generator 3131 generates a voltage V1 with a value of, for example, 5 volts, voltage generator 3132 generates a voltage V2 with a value of, for example, 5 volts, voltage generator 3133 generates a voltage V3 with a value of, for example, 5 volts, voltage generator 3134 generates a voltage V4, which is the erase voltage value, for example, -8 volts.

[0059] In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, and 0 respectively, and their inverse signals PG[1]B~PG[3]B can be logic levels 1, 0, and 1 respectively. Based on the voltage values ​​of voltages V1~V4, the control signals PG[1]~PG[3] and their inverse signals PG[1]B~PG[3]B, the word line signal generation circuits 3111~3113 can generate word line signals of 5, 3, and 5 volts respectively to drive word lines WL11~WL13, and the word line signal generation circuits 3121~3123 can generate word line signals of 5, -8, and 5 volts respectively to drive word lines WL21~WL23. In this way, only word line WL22 can be selected, while the other word lines WL11~WL13, W21, and W23 are not selected. In other words, only the memory cell corresponding to a single word line WL22 can be erased, while the remaining memory cells can be masked and not erased.

[0060] In other words, in this embodiment, by setting one of the control signals PG[1] to PG[3] to logic level 1, and using voltage generator 3132 or 3134 to provide an erase voltage value, the word line to be erased can be selected, and the erase operation can be performed on all or part of the memory cells of a single word line.

[0061] It is worth mentioning that in this embodiment, the word line signal generation circuit 3112 generates a word line signal to drive the word line WL22 by transmitting a voltage V2 through the lower N-type transistor. Due to the body effect of the N-type transistor, the word line signal generated by the word line signal generation circuit 3112 can be slightly lower than the voltage V2, but can be equal to 3 volts.

[0062] Please refer to the following: Figure 8 as well as Figure 9 , Figure 8 as well as Figure 9 These are schematic diagrams illustrating the erasure methods of one or more memory cells during a selected word line erasure operation, as described in embodiments of this disclosure. Figure 8 In the middle, corresponding Figure 7 In one embodiment, when word line WL21 is selected, all memory cells on word line WL21 can be erased by turning on both the source line switch SLT and the bit line switch BLT. In this embodiment, the word line signal on word line WL21 is, for example, -8 volts, and the word line signals on the other unselected word lines WL11, WL12, and WL22 are, for example, 5 volts. Furthermore, in this embodiment, the source line switch SLT is coupled between the source terminal of the memory cell and the common source line CSL, and the bit line switch BLT is coupled between the bit line terminal of the memory cell and the common bit line GBL. During the erase operation, the voltage on the common bit line GBL is, for example, 5 to 8 volts.

[0063] In this embodiment, the memory cell arrays corresponding to word lines WL11 and WL12 and the memory cell arrays corresponding to word lines WL21 and WL22 are all three-dimensional stacked AND gate flash memory cell arrays.

[0064] exist Figure 9 In the middle, the corresponding Figure 7 In this embodiment, when word line WL21 is set as the selected word line, and only the selected memory cell MCS needs to be erased, the selected source line switch SSLT of the corresponding selected memory cell MCS can be turned off, while other source line switches SLT are turned on; the selected bit line switch SBLT of the corresponding selected memory cell MCS is turned on, while other bit line switches BLT are turned off. In other words, by adjusting the on / off states of the source line switches and bit line switches, any one or more memory cells of the selected word line can be selected to perform the erase operation.

[0065] In this embodiment, the word line signal on word line WL21 is, for example, -8 volts, and the word line signals on the remaining unselected word lines WL11, WL12, and WL22 are, for example, 5 volts. Furthermore, in this embodiment, the source line switch SLT is coupled between the source terminal of the memory cell and the common source line CSL, and the bit line switch BLT is coupled between the bit line terminal of the memory cell and the common bit line GBL. During the erase operation, the voltage on the common bit line GBL is, for example, 5 to 8 volts.

[0066] Please refer to the following: Figure 10 , Figure 10 This is a schematic diagram illustrating an arbitrary bit-line erasure operation of a memory device according to an embodiment of this disclosure. Figure 10 In the process of erasing any selected word line, voltage generator 10131 generates a voltage V1 with a value of, for example, 5 volts, voltage generator 10132 generates a voltage V2 with a value of, for example, 5 volts, voltage generator 10133 generates a voltage V3 with a value of, for example, 5 volts, and voltage generator 10134 generates a voltage V4, which is the erasure voltage value, for example, -8 volts.

[0067] In addition, the control signals PG[1]~PG[3] can be logic levels 0, 1, and 1 respectively, and their inverse signals PG[1]B~PG[3]B can be logic levels 1, 0, and 0 respectively. Based on the voltage values ​​of voltages V1~V4, the control signals PG[1]~PG[3] and their inverse signals PG[1]B~PG[3]B, the word line signal generation circuits 10111~10113 can generate word line signals of 5, 3, and 3 volts respectively to drive word lines WL11~WL13, and the word line signal generation circuits 10121~10123 can generate word line signals of 5, -8, and -8 volts respectively to drive word lines WL21~WL23. In this way, word lines WL22 and WL23 can both be selected word lines, while the remaining word lines WL11~WL13 and W21 are unselected word lines.

[0068] As can be seen from the above description, in this embodiment, any one or more word lines can be selected so that the corresponding memory cell can be erased, while the remaining memory cells can be masked and not erased.

[0069] In summary, the word line signal generation circuit of this disclosure can generate word line signals for different word lines based on mutually independent voltages. By adjusting the voltage value of each word line signal, an erasure operation can be performed on the memory cell of one or more selected word lines during the erasure operation, effectively improving the freedom of data writing in the memory device and enhancing the data access performance of the memory device.

Claims

1. A word line driver, comprising: A first word line signal generation circuit is used to drive a first word line and generate a first word line signal by selecting one of a first voltage and a second voltage according to a control signal. as well as A second word line signal generation circuit is used to drive a second word line and select one of a third voltage and a fourth voltage to generate a second word line signal according to the control signal. A first voltage generator, coupled to the first word line signal generation circuit, is used to provide the second voltage; A second voltage generator, coupled to the first word line signal generation circuit, is used to provide the fourth voltage, wherein the first voltage generator and the second voltage generator are independent of each other; The first voltage generator adjusts the second voltage individually, and the second voltage generator adjusts the fourth voltage individually; Each of the first word line signal generation circuit and the second word line signal generation circuit includes: a first transistor, a second transistor, and a third transistor, wherein the first transistor is a P-type transistor, and the second and third transistors are N-type transistors, the first transistor being disposed on an N-type well region, and the second and third transistors being disposed on a P-type well region; and Both the first word line signal generation circuit and the second word line signal generation circuit are disposed on the triple-well substrate.

2. The word line driver according to claim 1, further comprising: A third voltage generator, coupled to the first word line signal generation circuit, is used to provide the first voltage; as well as A fourth voltage generator, coupled to the second word line signal generation circuit, is used to provide the third voltage.

3. The word line driver according to claim 2, wherein each of the third voltage generator and the fourth voltage generator is a voltage shifter, the third voltage generator determining the voltage value of the first voltage according to the logic level of a first selection signal, and the fourth voltage generator determining the voltage value of the third voltage according to the logic level of a second selection signal.

4. The word line driver according to claim 1, wherein in a read operation, the first voltage and the second voltage have the same voltage value, and the first word line signal generating circuit generates the first word line signal to make the first word line an unselected word line; the third voltage is a read voltage value, the fourth voltage is the same voltage value as the first voltage, and the second word line signal generating circuit makes the second word line signal equal to the read voltage value to make the second word line a selected word line, or makes the second word line signal equal to the fourth voltage to make the second word line an unselected word line.

5. The word line driver of claim 1, wherein in a programming operation, the first voltage and the second voltage have the same voltage value, the first word line signal generating circuit generates the first word line signal to make the first word line an unselected word line; the third voltage is a programming voltage value, the fourth voltage is the same voltage value as the first voltage, and the second word line signal generating circuit makes the second word line signal equal to the programming voltage value to make the second word line a selected word line, or makes the second word line signal equal to the fourth voltage to make the second word line an unselected word line.

6. The word line driver according to claim 1, wherein during a block erase operation, the first voltage is greater than the second voltage, and the first word line signal generating circuit makes the first word line signal equal to the first voltage to make the first word line an unselected word line; the third voltage is equal to an erase voltage value, and the second word line signal generating circuit makes the second word line signal equal to the erase voltage value to make the second word line a selected word line.

7. The word line driver according to claim 1, wherein in a selected word line erasure operation, the first voltage is equal to the second voltage, the first word line signal generating circuit generates the first word line signal according to the second voltage and makes the first word line a shielded word line; the second word line signal generating circuit makes the second word line signal equal to an erasure voltage value to make the second word line a selected word line.

8. The word line driver of claim 7, wherein the erase voltage value is less than 0.

9. The word line driver according to claim 1, wherein, The first transistor has a first terminal that receives the first voltage or the third voltage, a control terminal that receives the control signal, and a second terminal that is coupled to a corresponding word line. The second transistor has a first terminal coupled to a second terminal of the first transistor, a control terminal of the second transistor receiving the control signal, and a second terminal of the second transistor receiving the second voltage or the fourth voltage. as well as The third transistor has a first terminal coupled to the first terminal of the first transistor, a control terminal of the third transistor receiving the inverse signal of the control signal, and a second terminal coupled to the second terminal of the first transistor.

10. The word line driver of claim 1, wherein each of the first voltage generator and the second voltage generator is a voltage shifter, the first voltage generator determining the voltage value of the second voltage according to the logic level of a first select signal, and the second voltage generator determining the voltage value of the fourth voltage according to the logic level of a second select signal.

11. A stacked memory device, comprising: One-word line driver, including: Multiple first word line signal generation circuits are used to drive multiple first word lines respectively, and to select one of a first voltage and a second voltage according to multiple first control signals to generate these first word line signals; Multiple second word line signal generation circuits are used to drive multiple second word lines respectively, and select one of a third voltage and a fourth voltage to generate these second word line signals according to multiple second control signals. A first voltage generator, coupled to the first word line signal generation circuit, is used to provide the second voltage; a second voltage generator, coupled to the first word line signal generation circuit, is used to provide the fourth voltage, wherein the first voltage generator and the second voltage generator are independent of each other. The first voltage generator adjusts the second voltage individually, and the second voltage generator adjusts the fourth voltage individually; Each of the first word line signal generation circuit and the second word line signal generation circuit includes: a first transistor, a second transistor and a third transistor, wherein the first transistor is a P-type transistor, the second transistor and the third transistor are N-type transistors, the first transistor is disposed on an N-type well region, and the second transistor and the third transistor are disposed on a P-type well region. Both the first word line signal generation circuit and the second word line signal generation circuit are disposed on a triple-well substrate; and A first memory cell array, coupled to these first word lines; and A second memory cell array, coupled to these second word lines.

12. The stacked memory device of claim 11, wherein the first memory cell array and the second memory cell array are three-dimensional AND gate flash memory cell arrays.

13. The stacked memory device of claim 11, further comprising: A third voltage generator, coupled to the first word line signal generation circuit, is used to provide the first voltage; as well as A fourth voltage generator, coupled to the second word line signal generation circuit, is used to provide the third voltage. Each of the first voltage generator and the second voltage generator is a first voltage shifter. The first voltage generator determines the voltage value of the second voltage according to the logic level of a first selection signal, and the second voltage generator determines the voltage value of the fourth voltage according to the logic level of a second selection signal. Each of the third voltage generator and the fourth voltage generator is a second voltage shifter. The third voltage generator determines the voltage value of the first voltage according to the logic level of a third selection signal, and the fourth voltage generator determines the voltage value of the third voltage according to the logic level of a fourth selection signal.

14. The stacked memory device of claim 11, wherein in a read operation, the first voltage and the second voltage have the same voltage value, and each of the first word line signal generating circuits generates each of the first word line signals to make each of the first word lines an unselected word line; the third voltage is a read voltage value, the fourth voltage is the same voltage value as the first voltage, and each of the second word line signal generating circuits makes each of the second word line signals equal to the read voltage value to make each of the second word lines a selected word line, or makes each of the second word line signals equal to the fourth voltage to make each of the second word lines an unselected word line.

15. The stacked memory device of claim 11, wherein in a programming operation, the first voltage and the second voltage have the same voltage value, and each of the first word line signal generating circuits generates the first word line signal to make each of the first word lines an unselected word line; the third voltage is a programming voltage value, the fourth voltage is the same voltage value as the first voltage, and each of the second word line signal generating circuits makes each of the second word line signals equal to the programming voltage value to make each of the second word lines a selected word line, or makes each of the second word line signals equal to the fourth voltage to make each of the second word lines an unselected word line.

16. The stacked memory device of claim 11, wherein during a block erase operation, the first voltage is greater than the second voltage, and each of the first word line signal generating circuits makes the first word line signal equal to the first voltage to make each of the first word lines an unselected word line; the third voltage is equal to an erase voltage value, and each of the second word line signal generating circuits makes each of the second word line signals equal to the erase voltage value to make each of the second word lines a selected word line.

17. The stacked memory device of claim 11, wherein in a selected word line erase operation, the first voltage is equal to the second voltage, each of the first word line signal generating circuits generates each of the first word line signals according to the second voltage and makes each of the first word lines a shielded word line; each of the second word line signal generating circuits makes each of the second word line signals equal to an erase voltage value so that each of the second word lines is a selected word line.

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