Integrated circuits and memory devices

Abstract

The present disclosure provides an integrated circuit and a memory device. In one aspect of the present disclosure, the integrated circuit includes a latch circuit and a compensation circuit. The latch circuit includes a latch and a sense transistor coupled to each other. The compensation circuit is coupled to the sense transistor. The sense transistor includes a gate terminal and a connection terminal, the gate terminal is coupled to a sense node, and the connection terminal is coupled to the compensation circuit. The compensation circuit is configured to provide a control voltage to the connection terminal to compensate for a variation of a threshold voltage of a sense voltage.

Description

Technical Field

[0001] This disclosure relates to techniques for storing data, and in particular to an integrated circuit and a memory device. Background Technology

[0002] Integrated circuit memory devices are developing towards smaller size and higher speed. When reading from a memory device, a sensing transistor turns on or off depending on the state of the memory cell (e.g., 0 or 1), and the state of the sensing transistor can be detected to confirm the state of the memory cell. Summary of the Invention

[0003] This disclosure describes a system and technique for managing integrated circuits (e.g., page buffer circuits) of memory devices (e.g., non-volatile memories such as flash memory), such as compensation for threshold voltage variations in integrated circuits.

[0004] One aspect of this disclosure is an integrated circuit including a latching circuit and a compensation circuit. The latching circuit includes a latch and a sensing transistor coupled to each other. The compensation circuit is coupled to the sensing transistor. The sensing transistor includes a gate terminal and an additional terminal, the gate terminal being coupled to a sensing node and the additional terminal being coupled to the compensation circuit. The compensation circuit provides a control voltage to the additional terminal to compensate for variations in the threshold voltage of the sensing transistor.

[0005] The various integrated circuits described in this disclosure may include one or more of the following features.

[0006] In some embodiments, the control voltage is based on a preset voltage and a matching voltage, and the change in the matching voltage is essentially equivalent to the change in the threshold voltage of the sensing transistor.

[0007] In some embodiments, the matching voltage is substantially equivalent to the threshold voltage of the sensing transistor.

[0008] In some embodiments, the sensing transistor is used to receive a sensing voltage from its gate terminal and to sense memory cells based on a comparison between the sensing voltage and a preset voltage. The comparison result is independent of changes in the threshold voltage of the sensing transistor.

[0009] In some embodiments, the sensing transistor is used to: sense bit value 0 stored in the memory cell when the sensing voltage varies within the range between the pre-charge voltage and the preset voltage; and sense bit value 1 stored in the memory cell when the sensing voltage is lower than the preset voltage.

[0010] In some embodiments, the range between the pre-charge voltage and the preset voltage is fixed and independent of the threshold voltage variation of the sensing transistor.

[0011] In some embodiments, the compensation circuit includes a compensation transistor matched with a sensing transistor.

[0012] In some embodiments, the compensation transistor includes a compensation gate, a first terminal, and a second terminal. The compensation gate is coupled to a preset voltage; the first terminal is coupled to a supply voltage; and the second terminal is coupled to the input of a buffer circuit. The buffer circuit is used to provide a control voltage through its output terminal.

[0013] In some embodiments, the control voltage is based on a preset voltage and the threshold voltage of the compensation transistor.

[0014] In some embodiments, the control voltage is equivalent to the difference between the preset voltage and the threshold voltage of the compensation transistor.

[0015] In some embodiments, the threshold voltage of the sensed voltage varies between a high threshold voltage and a low threshold voltage, and the preset voltage is greater than or equal to the high threshold voltage.

[0016] In some embodiments, the compensation circuit is used to provide a control voltage to the source terminal of the compensation transistor.

[0017] In some embodiments, the control voltage is a function of the threshold voltage of the sensing transistor.

[0018] In some embodiments, the compensation circuit provides a control voltage that decreases as the threshold voltage increases and increases as the threshold voltage decreases.

[0019] In some embodiments, the compensation circuit is used to provide a control voltage that decreases as the temperature decreases and increases as the temperature increases.

[0020] In some embodiments, the connection terminal includes the source terminal of a sensing transistor.

[0021] In some embodiments, a compensation circuit is used to provide a control voltage so that the switching on or off of the sensing crystal is independent of changes in the threshold voltage of the sensing transistor.

[0022] In some embodiments, the change in the threshold voltage of the sensing transistor is based on temperature changes and / or changes in the manufacturing process of the sensing transistor.

[0023] In some embodiments, the control voltage makes the conduction state of the sensing transistor independent of temperature changes within a preset temperature range.

[0024] In some embodiments, the control voltage makes the switching voltage of the sensing voltage independent of process variations of the sensing transistor.

[0025] In some embodiments, the sensing transistor includes a third terminal for receiving current flowing through it during a read operation of the integrated circuit.

[0026] In some embodiments, the integrated circuit includes a pre-charge circuit coupled to the sensing node and used to pre-charge the sensing node to the supply voltage during pre-charging.

[0027] In some embodiments, the integrated circuit further includes bit line control circuitry. The bit line control circuitry includes a first control node and a second control node. The first control node is coupled to a bit line of a memory cell. The second control node is coupled to a sensing node. The bit line control circuitry is configured to: pre-charge the bit line during a pre-charge period; and discharge the sensing voltage on the sensing node by turning on the sensing node to the bit line to provide a sensing current to the memory cell during a discharge period following the pre-charge period.

[0028] In some embodiments, the latching circuit is configured during reading to: turn off the sensing transistor when the bit value stored in the memory cell is 1 and the sensing voltage of the sensing node is not greater than the target voltage, so that the bit value latched by the latcher is maintained at 1; and turn on the sensing transistor when the bit value stored in the memory cell is 0 and the sensing voltage on the sensing node is greater than the target voltage, so that the bit value latched by the latcher is set to 0.

[0029] In some embodiments, a sensing transistor is used to receive a sensed voltage through its gate. The sensing transistor is used to sense a memory cell based on a comparison between the sensed voltage and a preset voltage. A compensation circuit is used to provide a control voltage such that the preset voltage is greater than the common voltage of a common node, which is coupled to the gate via a connection transistor.

[0030] In some embodiments, the integrated circuit includes a capacitor coupled to the sensing node.

[0031] Another aspect of this disclosure is a memory device comprising a memory array, a plurality of memory cell lines, and a page buffer circuit. The memory array comprises a plurality of memory cells. The memory cell lines are connected to a plurality of connection lines of the memory cells in the memory array. The page buffer circuit comprises a plurality of page buffers. Each page buffer is coupled to the memory cell lines and includes a latching circuit and a compensation circuit. The latching circuit includes a latch and a sensing transistor coupled to each other. The compensation circuit is coupled to the sensing transistor. The sensing transistor includes a gate, a first terminal, and a second terminal; the gate is coupled to a sensing node, the first terminal is coupled to the latch, and the second terminal is coupled to the compensation circuit. The compensation circuit provides a control voltage to the second terminal to compensate for variations in the threshold voltage of the sensing transistor.

[0032] The various memory devices described in this disclosure may include one or more of the following features.

[0033] In some embodiments, the sensing transistor is used to receive a sensing voltage through its gate terminal. The sensing transistor is used to sense memory cells based on a comparison between the sensing voltage and a preset voltage. The comparison result is independent of changes in the threshold voltage of the sensing transistor.

[0034] In some embodiments, the compensation circuit includes a compensation transistor matched to the sensing transistor. The threshold voltage of the compensation transistor is substantially equivalent to the threshold voltage of the sensing transistor.

[0035] In some embodiments, the compensation transistor includes a compensation gate, a third terminal, and a fourth terminal. The compensation gate is coupled to a preset voltage. The third terminal is coupled to a supply voltage, and the fourth terminal is coupled to the input of a buffer circuit. The buffer circuit is used to provide a control voltage through its output.

[0036] Another aspect of this disclosure is an integrated circuit including a latch and a sensing transistor. The latch is used to latch data. The sensing transistor includes a gate, a first terminal, and a second terminal. The gate is coupled to a sensing node, the first terminal is coupled to the latch, and the second terminal is used to receive a control voltage. The sensing transistor is used to be turned on or off to update the data in the latch based on a sensed voltage at the sensing node and a target voltage. The target voltage is based on the control voltage and a threshold voltage of the sensing transistor. The control voltage is used to compensate for changes in the threshold voltage of the sensing transistor, making the target voltage independent of changes in the threshold voltage of the sensing transistor.

[0037] Another aspect of this disclosure includes a method for managing an integrated circuit, comprising the following steps: providing a control voltage to a sensing transistor of the integrated circuit, wherein the sensing transistor includes a gate terminal coupled to a sensing node and a connection terminal for receiving the control voltage; discharging the sensing voltage on the sensing node through a bit line coupled to a memory cell; and determining the state in the memory cell based on the discharged sensing voltage and a target voltage, wherein the target voltage is based on the control voltage and a threshold voltage of the sensing transistor. The control voltage is used to compensate for changes in the threshold voltage of the sensing transistor, making the target voltage independent of changes in the threshold voltage of the sensing transistor.

[0038] The various methods disclosed herein may include one or more of the following features.

[0039] In some embodiments, the method of providing a control voltage includes: providing a low threshold voltage based on an increase in the threshold voltage; and providing a high threshold voltage based on a decrease in the threshold voltage.

[0040] In some embodiments, the method of providing a control voltage includes: providing a low control voltage as the temperature decreases, such that the control voltage can be increased as the temperature rises.

[0041] In some embodiments, the other end includes the source terminal of the sensing transistor.

[0042] In some embodiments, the method of providing a control voltage includes providing a control voltage using a compensation circuit, wherein the compensation circuit includes a compensation transistor matched to the sensing transistor.

[0043] The aforementioned techniques and circuits can be implemented using any type of circuit or device that includes a sensing transistor, which has an on or off state to indicate the readout result. In some embodiments, the on or off state can be less dependent on or independent of changes in the threshold voltage of the sensing transistor. In some embodiments, temperature-induced threshold voltage variations can be compensated for. In some embodiments, threshold voltage variations caused by process variations can also be compensated for. In some embodiments, a large and stable sensing swing improves the tolerance to circuit variations. Based on the compensation of the threshold voltage, the readout results of the memory cell can be more accurate under temperature and process variations.

[0044] The aforementioned technology can be implemented using any type of memory transistor (or memory cell), any type of metal-oxide-semiconductor field-effect transistor (MOSFET) (N-channel or P-channel transistor), any type of bipolar junction transistor (BJT), or any type of operational amplifier. The aforementioned technology can also be applied to different types of memory systems, such as two-dimensional or three-dimensional memory systems. The aforementioned technology can be applied to different types of memory, such as single-level cell (SLC) devices, multi-level cell (MLC) devices (like two-level cell devices), or triple-level cell (TLC) devices. The aforementioned technology can be applied to various non-volatile memory devices, such as static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (such as NOR and / or NAND), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), phase-change random access memory (PCRAM), etc. In addition, the aforementioned technologies can also be applied to different types of devices or systems, such as secure digital cards, embedded multimedia cards (eMMC), solid-state drives, or embedded systems.

[0045] The accompanying drawings and subsequent embodiments of this disclosure illustrate details of one or more embodiments to clearly present the features, aspects, and advantages within the scope of the embodiments, drawings, and claims. Attached Figure Description

[0046] Figure 1A This is a schematic diagram of a system including a memory according to some embodiments of the present disclosure.

[0047] Figure 1B This is a schematic diagram of a block of a two-dimensional memory according to a partial embodiment of the present disclosure.

[0048] Figure 1C This is a schematic diagram of a block of a three-dimensional memory according to a partial embodiment of the present disclosure.

[0049] Figure 2 This is a schematic diagram of a memory device including a page buffer circuit with multiple page buffers, according to some embodiments of the present disclosure.

[0050] Figure 3 This is a schematic diagram of a page buffer circuit according to a portion of the embodiments of this disclosure.

[0051] Figures 4A-4C Schematic diagrams illustrating the various operation periods of the page buffer circuitry in some embodiments of this disclosure.

[0052] Figure 5 This document describes a timing diagram illustrating the control signals of the page buffer during each operation in some embodiments of the present disclosure.

[0053] Figure 6A A schematic diagram illustrating the sensed voltage of the page buffer circuit relative to the strobe voltage in some embodiments of this disclosure.

[0054] Figure 6B A voltage diagram illustrating the sensing voltage of the page buffer circuit in some embodiments of this disclosure.

[0055] Figure 7 This is a flowchart of a method for managing an integrated circuit in a memory device according to some embodiments of the present disclosure.

[0056] Explanation of reference numerals in the attached figures

[0057] 100: System

[0058] 110: Device

[0059] 112: Device controller

[0060] 113: Processor

[0061] 114: Internal Memory

[0062] 116: Memory

[0063] 120: Host

[0064] 140: Two-dimensional storage block

[0065] 141: Memory Unit

[0066] 142-150: Transistor

[0067] 152: Storage paging

[0068] 154: Storage Serial

[0069] 156: Serial Select Line

[0070] 157: Memory Unit

[0071] 158: Grounding Selection Line

[0072] 159: Common source pole line

[0073] 200: Memory device

[0074] 202: Memory Interface

[0075] 204: Control Logic Circuit

[0076] 206: X Decoder

[0077] 208: Data Buffer

[0078] 210: Memory Array

[0079] 215: Bit Line

[0080] 220: Page buffer circuit

[0081] 222: Page Buffer

[0082] 230: Cache data latch circuit

[0083] 300: Page Buffer Circuit

[0084] 302: Pre-charge circuit

[0085] 304: Bit line control circuit

[0086] 306: Latch circuit

[0087] 308: Compensation Circuit

[0088] 310: Sensing transistor

[0089] 330: Transistor

[0090] 350: Transistor

[0091] 322: Transistor

[0092] 324: Transistor

[0093] 326: Transistor

[0094] 334: Transistor

[0095] 336: Transistor

[0096] 338: Transistor

[0097] 318: Node

[0098] 348: Node

[0099] 328: Node

[0100] 344: Node

[0101] 340: Inverter

[0102] 342: Inverter

[0103] 346: Latch unit

[0104] 352: Operational amplifier

[0105] 354: Node

[0106] 406: Current

[0107] 600: Sensing swing amplitude

[0108] 602a: Sensing Voltage Curve

[0109] 602b: Sensing Voltage Curve

[0110] 602c: Sensing Voltage Curve

[0111] 604: Margin

[0112] 702-706: Steps

[0113] BL0-BL n Bit line

[0114] WL0-WL n : Word line

[0115] V Th Threshold voltage

[0116] VDDI: Supply voltage

[0117] PSEN: Signal

[0118] BLC1-BLC3: Signals

[0119] ΔV1: Sensing swing amplitude

[0120] ΔV2: Sensing swing amplitude

[0121] V strobe : gate voltage

[0122] V target Target voltage

[0123] V GS :Voltage

[0124] V SEN Sensing voltage

[0125] V SEN.1 Sensing voltage

[0126] V SEN.2 Sensing voltage

[0127] t SEN Sensing time

[0128] t SEN.1 Sensing time

[0129] t SEN.2 Sensing time

[0130] STB: Signal

[0131] DPOS: Signal

[0132] DL: Signal

[0133] IDL: Signal

[0134] PDL: Signal

[0135] PIDL: Signal Detailed Implementation

[0136] Figure 1A This diagram illustrates one embodiment of system 100. System 100 includes a device 110 and a host 120. Device 110 includes a device controller 112 and a memory 116. Device controller 112 includes a processor 113 and internal memory 114. In some embodiments, device 110 includes a plurality of memories 116 coupled to device controller 112.

[0137] In some embodiments, device 110 is a storage device. For example, device 110 may be an embedded Multi Media Card (eMMC), a secure digital card (SD), a solid-state drive (SSD), or other suitable storage device. In some embodiments, device 110 may be a smartwatch, a digital camera, or a media player. In some embodiments, device 110 is a client device coupled to host 120. For example, device 110 may be a memory card located in host 120, such as a digital camera or media player.

[0138] Device controller 112 may be a general-purpose microprocessor or a special-purpose microprocessor. In some embodiments, device controller 112 is the memory controller of device 110. Various variations of device controller 112 as a memory controller in different embodiments are described in the following paragraphs. However, device controller 112 described in the following paragraphs may also be applied to other embodiments that are different from memory controllers.

[0139] Processor 113 is used to execute instructions and process data. The instructions include code stored in firmware and / or programs in secondary memory. The data includes program data corresponding to the firmware and / or programs executed by the processor, or other applicable data. In some embodiments, processor 113 is a general-purpose microprocessor or a special-purpose microprocessor. Processor 113 may also be a central processing unit (CPU).

[0140] Processor 113 retrieves instructions and data from internal memory 114. In some embodiments, internal memory 114 is a static random access memory (SRAM) or dynamic random access memory (DRAM). For example, in some embodiments, when device 110 is an embedded multimedia card, memory card, or smartwatch, internal memory 114 is SRAM. In some embodiments, when device 110 is a digital camera or media player, internal memory 114 is DRAM.

[0141] In some embodiments, such as Figure 1A As shown, the internal memory is the cache memory included in the device controller 112. The internal memory 114 stores instruction codes corresponding to the instructions executed by the processor 113, and / or data required by the processor 113 during operation.

[0142] Device controller 112 transfers instruction codes and / or data from memory 116 to internal memory 114. Memory 116 may be a semiconductor device. In some embodiments, memory 116 is a non-volatile memory for long-term storage of instructions and / or data, such as NAND flash memory or other suitable non-volatile memory. In embodiments where memory 116 is NAND flash memory, device 110 is a flash memory device, such as a flash memory card, and device controller 112 is a NAND flash controller. For example, in some embodiments, when device 110 is an embedded multimedia card or memory card, memory 116 is NAND flash memory. In some embodiments, when device 110 is a digital camera, memory 116 is a memory card. In some embodiments, when device 110 is a media player, memory 116 is a hard disk. In some embodiments, memory 116 is included in a personal electronic device, such as a notebook computer, personal computer, smartphone, smartwatch, digital camera, wearable electronic device, or media playback device.

[0143] The memory 116 contains multiple memory blocks. The memory 116 may be a two-dimensional memory containing two-dimensional memory blocks. The memory 116 may also be a three-dimensional memory containing three-dimensional memory blocks.

[0144] Figure 1B An exemplary configuration for illustrating a two-dimensional memory block 140 of a memory (e.g., memory 116). Memory block 140 includes a plurality of memory cells 141. These memory cells 141 are connected in series to columns of bit lines BL0, BL1…BL2. n-1 BL n This forms multiple memory rows 144. These memory cells 141 are also connected in series to rows of word lines WL0, WL1 to WL2. n-1 WL n This is to form multiple storage pages 142 (cellpage).

[0145] Each memory cell in the memory block includes a transistor structure. The transistor structure includes a gate, a drain, a source, and a transistor channel, with the transistor channel located between the drain and source. Each memory cell is positioned at the intersection of a word line and a bit line, such that the gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line and thus to a common ground. In some embodiments, the flash memory cell has a dual-gate structure at its gate, including a control gate and a floating gate. The floating gate suspends between two oxide layers to trap electrons that program the memory cell.

[0146] The memory array 144 comprises, in series with each other, multiple memory cells 141, a string select transistor 143 (SST), and a ground select transistor 145 (GST). The gate of the string select transistor 143 is connected to a string select line 146 (SSL). The gates of the string select transistors 143 from different arrays are connected to the same string select line 146. The multiple gates of these memory cells 141 are respectively connected to word lines WL0, WL1 to WL2. n-1 WL n The memory strings 144 or these memory cells 141 are connected to a common source line 149 (CSL) via a ground select transistor 145. The common source line 149 may be coupled to ground. The gate of the ground select transistor 145 is connected to a ground select line 148 (GSL). The gates of the ground select transistors 145 located in different memory strings 144 are connected to the same ground select line 148.

[0147] Memory page 142 includes multiple memory cells 141. The gate terminals of each of these memory cells 141 in memory page 142 are each connected in series with a word line. When an input voltage is input from the word line, the input voltage is simultaneously applied to the gate terminals of these memory cells 141 in memory page 142. To read a specific memory page 142 within two-dimensional memory block 140 during a read operation, a low voltage is applied to the word line corresponding to that specific memory page 142. Simultaneously, a high voltage is applied to the other memory pages within two-dimensional memory block 140.

[0148] Figure 1C This describes an exemplary three-dimensional storage block 150 for implementing a three-dimensional memory. The three-dimensional storage block 150 may be... Figure 1BThe diagram shows a stack of two-dimensional memory blocks 140. Memory cells 157 are arranged in a three-dimensional form (e.g., an XYZ coordinate system) and coupled to multiple word lines to form multiple memory pages 152 (conductive layers or word line layers). Memory cells 157 are also connected to multiple bit lines to form multiple memory strings 154. A memory page 152 can be a layer, for example, on the XY plane. Memory cells 157 in the same layer can be coupled to a word line and have the same voltage. Each memory page 152 can be connected to a contact pad of a driving circuit. The driving circuit can be an X decoder (or a scan driver).

[0149] The memory string 154 includes a plurality of memory cells 157 connected in series vertically along the Z direction. One memory cell can be used as a serial select transistor (SST) coupled to a serial select line 156 (SSL), and another memory cell can be used as a ground select transistor (GST) coupled to a ground select line 158 (GSL). The memory string 154 is connected to one or more drivers, such as a data driver. The memory cells 157 are connected to a common source line 159 via the plurality of ground select transistors (GSTs). The common source line 159 may be a conductive layer (or a plurality of wires) formed on the substrate of the three-dimensional memory. The common source line 159 may be coupled to a ground terminal.

[0150] Figure 2 An exemplary configuration of the memory device 200 is described. The memory device 200 can be implemented as follows: Figure 1A The memory 116 is shown. The memory device 200 includes a memory array 210. The memory array 210 includes a plurality of memory cells, for example... Figure 1B The memory cell 141 shown or Figure 1C The memory cell 157 shown is connected in series to multiple word lines arranged in columns and multiple bit lines arranged in rows.

[0151] A memory cell contains a memory transistor for use as a storage element. The memory transistor includes a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating-gate transistor, a nitride read-only memory (NROM) transistor, or any suitable non-volatile memory metal-oxide-semiconductor (MOS) transistor device capable of storing charge.

[0152] The memory device 200 includes a memory interface 202, which includes multiple input / output ports for receiving data (e.g., from a memory controller, such as a device controller) or outputting data from the memory array 210. The memory device 200 includes a data buffer 208 for buffering data received from and output from the memory interface 202.

[0153] Memory device 200 also includes an X decoder (or column decoder) 206 and a Y decoder (not shown). Each memory cell is coupled to the X decoder 206 via a word line and to a bit line 215 (BL1, BL2, BL3…BL…). n The X decoder 206 and the Y decoder are coupled together. Therefore, each memory cell can be selected by the X decoder 206 and the Y decoder via its respective word line and bit line 215 for reading or writing.

[0154] Memory device 200 includes page buffer circuitry 220, which includes a plurality of page buffers 222. Each page buffer 222 (PB1, PB2, PB3…PBn) is connected via its respective bit lines (BL1, BL2, BL3…BLn). n The page buffer 222 is connected to the memory array 210. In some embodiments, the page buffer 222 is connected to the Y decoder via a data line associated with a corresponding bit line 215, which is connected to a corresponding memory cell in the memory array 210 arranged in a linear fashion. The page buffer is used to control the voltage of the corresponding bit line to execute a program, such as reading, programming (writing), or erasing, for the memory cell coupled to the corresponding bit line.

[0155] In some embodiments, the memory device 200 further includes a cache data latch circuit 230. The cache data latch circuit 230 is coupled between the page buffer circuit 220 and the data buffer 208. During a programming or erasing procedure, the cache data latch circuit 230 is used to store data from the data buffer 208 and / or output data to one or more page buffers 222 in the page buffer circuit 220. During a reading procedure, the cache data latch circuit 230 is used to store data from one or more page buffers 222 in the page buffer circuit 220 and / or output data to the data buffer 208.

[0156] The memory device 200 also includes control logic circuitry 204 coupled to multiple elements of the memory device 200, including an X decoder 206, a Y decoder, a data buffer 208, a page buffer circuitry 220, and a cache data latch circuitry 230. The control logic circuitry 204 is used to receive instructions, address information, and / or data, such as data from a memory controller via a memory interface 202. The control logic circuitry 204 can also process instructions, address information, and / or data, for example, generating physical address information (e.g., physical address information of blocks or pages) in the memory array 210.

[0157] In some embodiments, the control logic circuit 204 includes a data register, a static random access memory (SRAM) buffer, an address generator, state logic circuitry, and a state machine. The state logic circuitry can be used to confirm whether there is a read or write operation and to provide the confirmation result to the state machine.

[0158] During the write process, the data register of control logic circuit 204 temporarily stores input data from memory interface 202. The address generator of control logic circuit 204 generates the corresponding physical address to store the input data in a specific memory cell in memory array 210. The address generator is connected to X decoder 206 and Y decoder, which are controlled to select a specific memory cell via corresponding word lines and bit lines. A static random access memory (SRAM) buffer is used to maintain the input data from the data register when power is available. A state machine can process write information from the SRAM buffer and provide control signals to a voltage generator. The voltage generator provides a write voltage to X decoder 206 and / or Y decoder. The Y decoder outputs the write voltage to the bit lines to store the input data in a specific memory cell.

[0159] In the read procedure, a state machine provides control signals to a voltage generator and page buffer circuit 220. The voltage generator provides a read voltage to X decoder 206 and Y decoder to select a memory cell. Page buffer 222 senses a small power signal (e.g., a current signal) representing a data bit (e.g., 1 or 0) stored in the selected memory cell via a bit line 215 coupled to page buffer 222 and the selected memory cell. A sense amplifier amplifies the swings of the aforementioned small power signal to a identifiable logic level, allowing the data bit to be correctly identified by logic circuitry inside or outside the memory device 200. In some embodiments, page buffer circuit 220 and / or cache data latch circuit 230 are included in the sense amplifier. Data buffer 208 receives the amplified voltage from the sense amplifier and outputs the amplified power signal to logic circuitry outside the memory device 200 via memory interface 202.

[0160] To sense the data stored in a memory cell, during a discharge phase in the program, the charge stored on a sensing node is discharged, causing current to flow through the bit line of the memory cell. The amount of charge discharged on the sensing node depends on the state of the memory cell (e.g., bit 0 or bit 1), and the amount of discharged charge sets the sensing voltage V of the sensing node. SEN During the subsequent sensing time (or strobing phase), if the bit value stored in the memory cell is 0, the sensing voltage V on the sensing node... SEN It can be greater than a threshold voltage, for example: a gating voltage V of a latch associated with the page buffer. strobe In some embodiments, the gate voltage V strobe Equivalent to the threshold voltage V of the sensing transistor coupled to the sensing node TH Therefore, the page buffer is used to update the bit value of one or more latch latches from 1 to the sensed value 0, or to strobe the sensed value 0 to one or more latches. Conversely, if the bit value stored in the memory cell is 1, the discharge sensed voltage V on the sense node... SEN Less than or equal to the gate voltage V strobe Therefore, the page buffer is used to maintain (or hold) the bit value of 1 latched by one or more latches. Discharge sensing voltage V SEN This can be tested by detecting whether the sensing transistor is on or off, so that the gate voltage V is present even without compensation (e.g., the source terminal of the sensing transistor is grounded). strobe Equivalent to the threshold voltage V of the sensing transistor TH .

[0161] If the threshold voltage V of the sensing transistor THThe gate voltage V is different from the expected value. strobe This can change, and the sensing results may also be inaccurate. For example, the sensing voltage V corresponding to the stored bit value 1... SEN It is less than the threshold voltage V TH The expected or ideal value, but may be greater than the threshold voltage V. TH The actual or non-ideal value of the value causes the stored bit value to be incorrectly sensed as 0. Alternatively, the sensed voltage V corresponding to the stored bit value of 0... SEN It is greater than the threshold voltage V TH The expected or ideal value, but may be less than the threshold voltage V. TH The actual or non-ideal value of the stored bit can cause it to be incorrectly sensed as 1.

[0162] Threshold voltage V of the sensing transistor TH Variation can be caused by factors such as temperature changes, process variations in the sensing transistor, or a combination of these factors. Process, voltage, and temperature variation (hereinafter referred to as PVT variation) refers to variations in process, voltage (e.g., operating voltage or supply voltage), or temperature that can collectively affect the threshold voltage V. TH The threshold voltage of a complementary metal-oxide-semiconductor transistor can vary between -4mV / K and -2mV / K, thus the threshold voltage V varies over a typical target operating temperature range of 150 degrees Celsius. TH The threshold voltage can vary significantly, ranging from 300mV to 600mV. It can be affected by factors such as gate length, doping levels / profiles, or other parameters that cannot be predicted due to process variations.

[0163] Several embodiments of this disclosure provide an integrated circuit with processing power and temperature compensation capabilities, such as a page buffer circuit. In an embodiment with an N-channel sensing transistor, the source voltage of the sensing transistor is adjusted to compensate for the threshold voltage V. TH The change in voltage is compensated for, ensuring the gate voltage of the sensing transistor remains constant and enabling a large, fixed sensing swing. The memory cell state can then be accurately sensed during the sensing time.

[0164] Figure 3The page buffer circuit 300 (e.g., implementing page buffer 222) includes compensation circuitry. In some embodiments, the page buffer circuit 300 includes a precharge circuit 302, a bit line control circuit 304, a latch circuit 306, and a compensation circuit 308. The page buffer circuit 300 is coupled to a bit line 312, which is coupled to a bit line transistor 313 and a memory cell 314, wherein the state of the memory cell 314 can be detected by the page buffer circuit 300. The bit line 312 may be included in a memory string, such as memory string 144 or 154. As detailed below, the latch circuit 306 includes a sensing transistor 310, and changes in the threshold voltage of the sensing transistor 310 can be compensated by the compensation circuit 308.

[0165] In some embodiments, the pre-charge circuit 302 includes an N-channel transistor 316 (e.g., an NMOS transistor) coupled between a supply voltage VDDI and a sensing node 318. The transistor 316 has a drain, a gate, and a source, where the drain receives the supply voltage VDDI, the gate receives a pre-charge enable signal PSEN, and the source is coupled to the sensing node 318. The pre-charge circuit 302 also includes a capacitor 320 coupled between the sensing node 318 and ground. The capacitor 320 can be implemented in various ways, such as a metal-oxide-metal capacitor or a metal-oxide-semiconductor capacitor, like a capacitor integrated into the transistor. The transistor 316 can be turned on or off according to the pre-charge enable signal PSEN to allow the capacitor 320 to discharge or charge.

[0166] In some embodiments, the bit line control circuit 304 includes three N-channel transistors 322, 324, and 326 for receiving bit line control signals BLC1, BLC2, and BLC3, respectively. Transistor 326 has a drain and a source terminal; the drain terminal is coupled to a sensing node 318, and the source terminal is coupled to a common node 328. Therefore, transistor 326 can be turned on or off to couple or decouple bit line 312 and other parts of the bit line control circuit 304 from other parts of the page buffer circuit 300. Transistor 324 has a drain and a source terminal; the drain terminal receives the supply voltage VDDI, and the source terminal is coupled to the common node 328, allowing transistor 324 to be turned on or off to allow memory cells on bit line 312 to charge or discharge. Transistor 322 has a drain terminal and a source terminal. The drain terminal is coupled to a common node 328, and the source terminal is coupled to a bit line 312, so that transistor 322 can be turned on or off to couple or disconnect the page buffer circuit 300 and the bit line 312.

[0167] In some embodiments, latch circuit 306 includes three N-channel transistors 330, 332, and 324, and two P-channel transistors 336 and 338 (e.g., PMOS) and two inverters 340 and 342. Inverter 340 is used to receive the corresponding signal DPOS, and inverter 342 is used to receive the corresponding standby signal STBD. P-channel transistors 336 and 338 and inverters 340 and 342 together form a tri-state latch unit 346 (sometimes called a latch), which can have a 0 or 1 state based on reading a memory cell on bit line 312. In some embodiments, latch circuit 306 includes sensing latch circuitry, storage latch circuitry, and / or other types of latch circuitry. In some variations, different types of latch units may be included in the latch circuitry, such as fighting latches or other suitable latches. Furthermore, each latch circuit may have a different number of latch units in the page buffers of different types of memory cells. For example, if the memory cell type is Single-Level Cell (SLC), the page buffer of the memory cell can contain two latch units. If the memory cell type is Multi-Level Cell (MLC), the page buffer of the memory cell can contain three latch units. If the memory cell type is Three-Level Cell (TLC), the page buffer of the memory cell can contain five latch units. If the memory cell type is Penta-Level Cell (PLC), the page buffer of the memory cell can contain six latch units.

[0168] Transistor 330 includes a source terminal, a gate terminal, and a drain terminal, wherein the source terminal is coupled to the drain terminal of sensing transistor 310, the gate terminal is used to receive a gating control signal STB, and the drain terminal is coupled to an internal storage node 344 (e.g., a node associated with the initial storage of data, where the signal is IDL). Therefore, transistor 330 can be turned on or off to couple or disconnect sensing transistor 310 from other parts of latch-up circuit 306. Transistor 332 includes a drain terminal, a gate terminal, and a source terminal, wherein its drain terminal is used to receive a supply voltage VDDI, its gate terminal is used to receive a control signal PIDL, and its source terminal is coupled to internal storage node 344. Therefore, transistor 332 can be turned on or off to charge or discharge internal storage node 344, for example, charging / discharging is associated with the junction capacitance and / or metal capacitance of internal storage node 344. Transistor 334 includes a drain terminal, a gate terminal, and a source terminal. Its drain terminal is coupled to node 348 (where the signal is DL), its gate terminal is used to receive the data latch control signal PDL, and its source terminal is coupled to internal storage node 344. Therefore, transistor 334 can be turned on or off to couple or disconnect latch unit 346 from other parts of page buffer circuit 300.

[0169] In some embodiments, the compensation circuit 308 includes an N-channel compensation transistor 350 and an operational amplifier 352. The characteristics of the N-channel compensation transistor 350 are substantially the same as those of the sensing transistor 310. The compensation transistor 350 has a drain terminal, a gate terminal, and a source terminal, with its drain terminal used to receive the supply voltage VDDI and its gate terminal used to receive the target voltage V. target (Details will be provided in subsequent paragraphs), its source terminal is coupled to the positive input of operational amplifier 352 via compensation node 354. Target voltage V target The target voltage is a fixed voltage (e.g., a preset value) and is independent of temperature and / or process variations or PVT-related effects. target This can be provided by bandgap voltage circuitry, such as memory devices (e.g., Figure 2 The bandgap voltage circuit in the memory device 200. When compensating the N-channel compensation transistor 350, the target voltage Vtarget will be greater than the threshold voltage VTH of the compensation transistor 350, so that V is present on the compensation node 354. target -V TH The operational amplifier 352 is used as a voltage follower (buffer circuit) to make the voltage V... target -V TH It is used as a control voltage and supplied to the source terminal of the sensing transistor 310. Specifically, the voltage V target -V TH It can compensate for changes in the threshold voltage of the sensing transistor 310.

[0170] The compensation transistor 350 is matched to the sensing transistor 310 in that the change in the threshold voltage of the compensation transistor 350 is matched (substantially equal to) the change in the threshold voltage of the sensing transistor 310. For example, in some embodiments, the temperature dependence of the threshold voltage of the compensation transistor 350 is matched to the temperature dependence of the threshold voltage of the sensing transistor 310. In some embodiments, the compensation transistor 350 and the sensing transistor have matched transistor designs (e.g., gate length, oxide material and thickness, doping level, channel type and / or other materials and / or dimensions), and therefore have matched threshold voltages. In some embodiments, the compensation transistor 350 and the sensing transistor 310 are fabricated under the same process conditions, such as the same temperature and / or the same process (e.g., the same lithography process), such that a process variation in one transistor (and the resulting threshold voltage variation) will be reflected in the other transistor. In some embodiments, using a matched compensation transistor 350 can provide a better threshold voltage tracking scheme than other methods, for example, implemented with fewer devices and / or less complex circuitry.

[0171] Figures 4A-4CThe control voltages for each operating phase of the page buffer circuit 300 are illustrated in the diagram. Figure 5 .

[0172] like Figure 4A As shown, during pre-charging, transistors 322 and 324 are turned on via signals BLC1 and BLC to charge bit line 32 using a current of 400. This process boosts the voltage value of common node 328 to V. COM Transistor 326 is turned off via signal BLC3 to isolate bit line 312 from latch circuit 306. Transistor 316 is turned on via signal PSEN to charge capacitor 320 through current 402, thereby increasing the sensing voltage on sensing node 318 to V. SEN,1 In some embodiments, V SEN,1 This is equivalent to the supply voltage VDDI. Transistor 332 is turned on according to signal PIDL to charge internal storage node 344 through current 404. Transistors 330 and 334 are turned off according to signals STB and PDL to isolate internal storage node 344 from sensing transistor 310 and from latching unit 346.

[0173] like Figure 4B As shown, during discharge, transistor 326 is turned on according to signal BLC3, and transistor 316 is turned off according to signal PSEN. This electrically couples sensing node 318 to bit line 312, allowing current 406 to flow from sensing node 318 (e.g., from the charged capacitor 320) to bit line 312 and memory cell 314. This causes the sensed voltage of sensing node 318 to change from V... SEN,1 Discharge to a lower V SEN,2 Transistors 330, 332, and 334 are turned off according to signals STB, PIDL, and DL to maintain the charge (voltage) on the internal storage node 344.

[0174] The amount of charge flowing to form current 406 depends on the state of memory cell 314. Specifically, in some embodiments, when the bit value stored in memory cell 314 is 1, a larger amount of charge flows to form current 406. When the bit value stored in memory cell 314 is 0, a smaller amount of charge flows to form current 406 (the operation may be reversed in other embodiments). The larger amount of current corresponds to the sensing voltage V. SEN From V SEN,1 Change to V SEN,2 The reduction is relatively large. Therefore, V when the bit value stored in memory cell 314 is 1. SEN,2 This will be lower than V when the bit value stored in memory cell 314 is 0. SEN,2 .

[0175] Voltage value V SEN,2The state of sensing transistor 310 is specified. When sensing transistor 310 is an N-channel transistor, sensing transistor 310 will operate at voltage V. GS The difference between the gate voltage and the source voltage of the transistor is greater than the threshold voltage V. TH It is turned on at this time. At the end of the discharge period, the gate voltage will be V. SEN,2 Therefore, when the bit value stored in memory cell 314 is 1, the sensing transistor 310 can be turned off at the end of the discharge period, for example, V. SEN,2 It can be a sufficiently low value so that the voltage V GS Less than or equal to V TH Conversely, when the bit value stored in memory cell 314 is 0, sensing transistor 310 will turn on at the end of the discharge period. SEN,2 It can be a sufficiently high value, so that the voltage V GS Greater than V TH .like Figure 5 As shown, in this embodiment, at the end of the discharge period, V SEN,2 Greater than V strobe (In the absence of compensation, V) strobe It can be equated to V TH The on or off state of the sensing transistor 310 can be read (confirmed) during a subsequent read and transmitted to the latch unit 346. However, without compensation (in this embodiment, compensation is provided by the compensation circuit 308, which will be described in a later paragraph), the reliable correspondence between the I / O state of the memory cell 314 and the off / on state of the sensing transistor 310 depends on a stable V. TH .

[0176] like Figure 4C As shown, during the read operation, transistors 322, 324, and 326 are turned off according to signals BLC1, BLC2, and BLC3 to isolate sensing node 318 from coupling except for the gate of sensing transistor 310 and capacitor 320. Transistor 332 is turned off according to signal PIDL, and transistors 330 and 334 are turned on according to signals STB and PDL. Therefore, if sensing transistor 310 is turned on, current 408 will flow from node 348 to sensing transistor 310, and the high voltage at node 348 corresponding to bit value 1 will be charged to the low voltage corresponding to bit value 0 to store / sensor bit value 0 in latch unit 346. If sensing transistor 310 is turned off, current 408 will not flow, and the high voltage at node 348 will be maintained to store / sensor bit value 1 in latch unit 346.

[0177] As previously stated, by providing a control voltage to the source terminal of the sensing transistor 310, the compensation circuit 308 will compensate for the threshold voltage V of the sensing transistor 310.TH The change in [the voltage / voltage]. Understanding the conduction state of the sensing transistor 310 in the following two cases will help to understand this operation: without the compensation circuit 308 (the source terminal of the sensing transistor 310 is grounded), and when the compensation circuit 308 provides a control voltage V to the source terminal. control equals V target –V TH In this case.

[0178] Without compensation circuit 308 (e.g., source terminal of sensing transistor 310 is grounded), the gate voltage V strobe It will be equivalent to the threshold voltage V TH And the sensing transistor 310 will be at the gate voltage V SEN,2 Greater than the threshold voltage V TH It is turned on at any time. The on state directly depends on the threshold voltage V. TH The critical voltage V TH Changes in V may cause the sensing transistor 310 to erroneously turn on / off. For example, in V SEN,2 V at the first temperature TH In the +0.05 V embodiment, the transistor will be turned on at the first temperature (e.g., directly turned on, thus reflecting the bit value of memory cell 314). However, if the temperature change causes the threshold voltage to become V at the second temperature... TH =V TH -0.10V, then at the second temperature, V SEN,2 For V TH At -0.05V, sensing transistor 310 will incorrectly turn off.

[0179] However, in one embodiment of the page buffer circuit 300, the control voltage V related to the threshold voltage... target -V TH When applied to the source terminal of sensing transistor 310, sensing transistor 310 will... GS >V TH Time conduction. This situation is equivalent to V. SEN,2 -V source >V TH or equivalent to V SEN,2 -V target +V TH >V TH And can be organized into V SEN,2 >V target Therefore, the gate voltage V strobe It is not equivalent to the threshold voltage V of the sensing transistor. TH (threshold voltage V) TH (This may vary due to temperature, process variations, or other factors), gate voltage V strobeThe target voltage V target And the target voltage V target This is a fixed value independent of temperature variations and / or process variations or PVT-related effects. The threshold voltage V for conduction conditions. TH The correlation is removed, and due to the correlation with the target voltage V target The stability condition is replaced by V targe t can be directly selected and applied to the gate of the compensation transistor 350 in the compensation circuit 308. Therefore, by coupling one end (e.g., the source terminal) of the sensing transistor 310 to the control voltage instead of ground, the state of the memory cell 314 can be correctly predicted by the sensing transistor 310, even if the threshold voltage V TH This varies with process or temperature changes. In some embodiments, within a desired / set temperature range (e.g., -40°C to 125°C, or other temperature ranges), the conduction condition is independent of or only slightly related to changes in the threshold voltage. Target voltage V target It is called the target voltage because it represents the compensation target voltage of the sensing transistor when it switches on / off.

[0180] Target voltage V target It can be configured based on one or more different conditions (e.g., selected and applied to the gate of compensation transistor 350). In some embodiments, the target voltage V varies within a desired range of process and temperature variations. target It is set to always be greater than (or substantially, almost always greater than) the threshold voltage V. TH For example, target voltage V target This can be determined based on experience. For example, when determining the target voltage V... target At that time, the threshold voltage V of many sensing transistors (responding to process variations) within the desired temperature range can be determined by measurement. TH Next, the target voltage V target It can be selected as a threshold voltage V greater than these measurements. TH Any one of them, or the threshold voltage V based on these measurements. TH The selection is based on statistical analysis, for example, a threshold voltage V greater than the 99th percentile. TH In some embodiments, the measured threshold voltage V TH At high threshold voltage V TH-H and low voltage V TH-L It varies within the range between [a certain range]. Target voltage V target It can be set to match the high threshold voltage V TH-H The same. Therefore, in implementation, the target voltage V target It can almost always be greater than the threshold voltage V THThis is to ensure the correct operation of the compensation circuit 308 as described in this disclosure.

[0181] In some embodiments, the target voltage V target The target voltage V can be met alternatively or additionally. target Greater than or equal to V COM (That is, the voltage at common node 328 at the end of the pre-charge period) condition. When this condition is met, the sensed voltage at sensed node 318 can swing to the target voltage V. target Simultaneously, the sensing voltage is maintained in discharge to generate current flowing from sensing node 318 to common node 328 during discharge, consistent with the intended operation of page buffer circuit 300. For example, in some embodiments, VDDI is approximately 1.4V, V COM Approximately 0.7V. In this embodiment, V SEN The capacitor is pre-charged to 1.4V and discharged to 0.8V if the memory cell current is high, thereby causing the sensing transistor 310 to turn off. In some embodiments, V COM It is equal to or approximately equal to 0.7V.

[0182] Another advantage of this compensation method is the relatively large and stable sensing swing, which represents the voltage swing necessary to turn off the sensing transistor 310 at the sensing node 318. (Refer to...) Figure 6A As shown, generally speaking, the sensing swing of 600 is equal to the first sensing voltage V. SEN,1 With the gate voltage V strobe The difference between them: higher than the gate voltage V strobe The final voltage V SEN,2 This causes the sensing transistor to turn on, and the voltage is below the gate voltage V. strobe The final voltage V SEN,2 This will cause the sensing transistor to turn off. During the sensing time t... SEN The sensing node 318 will discharge through the discharge current IDIS. Figure 6A The figures shown are three sensing voltage curves 602a, 602b, and 602c corresponding to three embodiments with discharge current values ​​of 19nA, 20nA, and 21nA, respectively. The selected turn-on voltage V... strobe have Figure 6A The values ​​shown (i.e., corresponding to the sensing amplitude ΔV2 and approximate sensing time t) SEN,2 At different current values, the final voltage V SEN,2 The margin of 604 is relatively large. A margin of 604 indicates the amount of voltage required to generate a voltage related to the gate voltage V. strobeThe margin 604 represents the allowable variation in electrical characteristics when the sensing result is accurate. Therefore, a larger margin of 604 indicates a higher tolerance of the circuit for different types of variations, such as process variations, temperature variations, and operational variations (e.g., variations in supply voltage). These variations can (but are not necessary) differ from the threshold voltage variation of the sensing transistor. For example, these variations may cause other circuit parameters to differ.

[0183] Compared to the relatively large margin of 604 associated with the sensing swing ΔV2, when the sensing swing is small (in Figure 6A The sensing swing ΔV1 and approximate sensing time t are shown. SEN,1 The margins between the final voltages of the sensing voltage curves 602a, 602b, and 602c are even smaller. These margins are smaller over the sensing time t. SEN,1 This can be viewed as the spacing between the sensing voltage curves 602a, 602b, and 602c, and corresponds to a lower tolerance for changes in electrical characteristics. For example, when the sensing swing is small, small changes in electrical characteristics (such as the discharge current IDIS) will affect V. SEN,2 Incorrectly higher or lower than the gate voltage V strobe This can lead to erroneous sensing results. Therefore, in some cases, a larger sensing swing is better than a smaller sensing swing, for reasons different from those for which a stable sensing swing is required.

[0184] like Figure 6B As shown, in an embodiment of the page buffer circuit 300 including compensation circuit 308, the sensing swing 610 is the pre-charge voltage (e.g., supply voltage VDDI) and target voltage V of the sensing transistor. target (e.g., VDDI-V) target The range between ) and ). During the sensing time t SEN In the process, the sensed voltage discharges from VDDI to another value V. SEN,2 .exist Figure 6B In the diagram, the discharge is shown by curve 612, and V SEN,2 Equal to target voltage V target It meets the aforementioned V COM Condition, i.e., V target >V COM In some embodiments, because the target voltage V target Subject only to the aforementioned V COM Due to limitations, the sensing amplitude may be relatively large, for example, up to VDDI-V. COM This improves the tolerance of the page buffer circuit 300 to changes in electrical characteristics. Furthermore, due to the supply voltage VDDI and the target voltage V... target Both are fixed voltages, independent of the threshold voltage V. THTherefore, the sensing swing 610 itself is stable and independent of the threshold voltage V. TH The change. Compared to a circuit that does not apply a compensation control voltage to the sensing transistor 310, a large and stable sensing swing allows the page buffer circuit 300 to withstand threshold voltage V. TH Changes in threshold voltage V TH It operates more reliably when there are changes other than those that occur.

[0185] Figure 6B The diagram shows the control voltage V applied by the compensation circuit 308 to the source terminal of the sensing transistor 310. control The change in target voltage V. In some embodiments, the change in target voltage V. target Selected as threshold voltage V TH The upper limit of change (high end) V TH-H Therefore, when V TH =V TH-H At this time, the control voltage is set to its minimum value, approximately 0V or higher, to maintain the intended operation of the page buffer circuit 300 (e.g., keeping the source terminal of the sensing transistor 310 at or above 0V). When V TH =V TH-L At that time, the control voltage is set to the higher value V of the control voltage. target –V TH-L This is to maintain the intended operation of the page buffer circuit 300 (e.g., in some embodiments, to maintain the V of the sensing transistor 310). GS (Positive).

[0186] Compared to other circuits that do not apply a control voltage to the sensing transistor, the advantages of this disclosure can also be applied to adjusting the pre-charge sensing voltage V at the sensing node. SEN,1 In an attempt to compensate for the threshold voltage V TH The circuit changes. Compared to one with adjustable V... SEN,1 The circuit described in this disclosure, which does not apply a control voltage to the sensing transistor, can have improved characteristics, such as more stable switching conditions (e.g., a more stable gate voltage V). strobe ), and a larger, more stable voltage swing to provide a greater voltage margin at the end of the discharge period.

[0187] The control voltage V provided in the page buffer circuit 300 target – V TH These are non-limiting examples. In some embodiments, the control voltage is a threshold voltage V. TH A function, but different from V target –V TH For example, in some embodiments, the control voltage is a threshold voltage V. THThe function of V makes a higher threshold voltage V TH This results in a lower control voltage, and a lower threshold voltage VTH leads to a higher control voltage. In some embodiments, the control voltage is a function of temperature, and thus depends on the MOS threshold voltage VTH. TH The control voltage exhibits a negative temperature dependence, meaning higher temperatures result in higher control voltages, while lower temperatures result in lower control voltages. In some embodiments, the control voltage compensates for changes in the threshold voltage VTH, such that the threshold voltage Vth of the sensing transistor's switching condition is adjusted. TH The dependency is reduced. In the aforementioned embodiments, the threshold voltage V was eliminated. TH Dependency. In other partial embodiments, the threshold voltage V TH Dependency can be reduced rather than eliminated; for example, reducing the threshold voltage V in the threshold condition compared to removing the compensation circuit (e.g., changing to a ground connection). TH The coefficient of the term. In some embodiments, the control voltage causes the threshold voltage V to... TH The change can be made at a preset threshold voltage V TH The threshold voltage V is compensated within a certain range (e.g., for a specific gate voltage, without changing the on / off state of the sensing transistor). TH The range can be greater than 0.01V, greater than 0.02V, greater than 0.05V, greater than 0.1V, or greater than 0.2V.

[0188] Furthermore, this disclosure does not limit the type of compensation circuit 308, which is used to provide a compensation threshold voltage V. TH Other compensation circuitry for varying control voltages is also within the scope of this disclosure. Compensation circuitry may include other or additional circuit elements, such as capacitors, transistors, resistors, diodes, amplifiers, operational / processing elements, and other types of circuit elements. For example, in some embodiments, the compensation circuitry is used to directly monitor a threshold voltage of a sensing transistor and, in response to confirming the threshold voltage, apply a control voltage. For example, the compensation circuitry may include a processing element, such as a microprocessor, that executes an algorithm to confirm the control voltage to be provided based on the monitored threshold voltage. In some embodiments, the compensation element includes a processing element that processes a storage module or other algorithm to confirm and provide the control voltage based on one or more parameters. For example, the processing element may be used to process an algorithm that instructs the control voltage as a function of temperature to determine the temperature (e.g., using a thermistor or other temperature sensor with the compensation circuitry). The control voltage is determined using the temperature-based algorithm and provided to the sensing transistor.

[0189] Furthermore, specific forms of other parts of the page buffer circuit 300, such as the precharge circuit 302, the bit line control circuit 304, and the latch circuit 306, are merely illustrative examples. Other circuits that can be configured to provide the aforementioned functions during precharge, discharge, and read operations are also within the scope of this disclosure. Additionally, although the compensation circuit 308 has been described in the page buffer circuit 300, the aforementioned threshold voltage compensation method can be combined with other types of circuits, the on / off state of the sensing transistor can be sensed to indicate the result, and / or the on / off state of the transistor can otherwise indicate circuit operation.

[0190] Figure 7 The diagram shown is a schematic representation of a process 700 for managing an integrated circuit in some embodiments of this disclosure. For example, the integrated circuit may include a page buffer circuit, such as page buffer circuit 300, within the memory device. The memory device may be... Figure 1A The memory 116 shown or Figure 2 The memory device 200 shown. The memory device may include a memory array having multiple memory cells, for example... Figure 1B The memory cell 141 shown or Figure 1C The memory cell 157 is shown. Memory cell lines are connected to multiple connection lines of memory cells in the memory array; in other words, memory cells are connected in series and coupled to multiple columns of memory cell lines (e.g., bit lines). The page buffer circuit can be a page buffer, for example... Figure 2 The page buffer 222 shown is coupled to the corresponding memory cell via corresponding bit lines. The page buffer circuitry can be managed or controlled by control logic circuitry within the memory device, for example... Figure 2 The control logic circuit 204 is shown. Process 700 can be executed by the control logic circuit that manages the page buffer.

[0191] Integrated circuits may include latch-up circuits (e.g.: Figure 3 The latching circuit 306 shown) and the compensation circuit (e.g.: Figure 3 The compensation circuit 308 shown is included. The latching circuit includes a latch (e.g., a latching device). Figure 3 The latch unit 346 shown) and the sensing transistor (e.g.: Figure 3 The sensing transistor 310 shown includes a gate terminal and an additional terminal, wherein the gate terminal is coupled to a sensing node (e.g., a sensing transistor 310). Figure 3 The sensing node 318 shown), the connection end (such as Figure 3 The source terminal of the sensing transistor 310 shown is coupled to a compensation circuit. The compensation circuit can be used to apply a control voltage to the connection terminal to compensate for changes in the threshold voltage of the sensing transistor.

[0192] In some embodiments, the control voltage is based on a preset voltage (e.g., V). target ) and matching voltage (e.g.: Figure 3 The threshold voltage V of the compensation transistor 350 TH The change in the matching voltage is substantially the same as the change in the threshold voltage of the sensing transistor. The matching voltage may be the same as the threshold voltage of the sensing transistor. The sensing transistor can be used to receive a sensing result at its gate (e.g., the voltage of sensing node 318). The sensing transistor can sense a memory cell (e.g., memory cell 314) based on a comparison between the sensed voltage and a preset voltage, where the comparison result is independent of the change in the threshold voltage of the sensing transistor. For example, the sensing transistor can be used when the sensed voltage is at a pre-charge voltage (e.g., ...). Figure 3 When the sensing voltage (VDDI) varies within the range between the supply voltage shown and the preset voltage (e.g., when the sensing transistor 310 is turned on), the bit value in the sensing memory cell is 0; and when the sensing voltage is less than the preset voltage (e.g., when the sensing transistor 310 is turned off), the bit value stored in the sensing memory cell is 1. The range between the pre-charge voltage and the preset voltage can be fixed and independent of changes in the threshold voltage of the sensing transistor (e.g., a fixed sensing swing VDDI-V). target ).

[0193] In some embodiments, the compensation circuit includes a compensation transistor matched with the sensing transistor (e.g., : Figure 3 The compensation transistor 350 is shown. The threshold voltage of the compensation transistor is substantially the same as the threshold voltage of the sensing transistor. The compensation transistor includes a gate terminal, a first terminal, and a second terminal, with its gate terminal coupled to a preset voltage (e.g., ...). Figure 3 The V shown target Its first terminal is coupled to the supply voltage (e.g., coupled to the supply voltage). Figure 3 The drain terminal of the compensation transistor 350 (supply voltage VDDI) is coupled to the second terminal of a buffer circuit (e.g., the drain terminal of the compensation transistor 350). Figure 3 The input terminal of the operational amplifier 352 shown is used. A buffer circuit is used to provide a control voltage at the output terminal (e.g., the source terminal of the sensing transistor 310). The control voltage can be based on a preset voltage and the threshold voltage of the compensation transistor. For example, it is equal to the difference between the preset voltage and the threshold voltage of the sensing transistor (e.g., V). target -V TH The control voltage can be supplied to the source terminal of the compensation transistor. The control voltage can be a function of the threshold voltage of the sensing transistor.

[0194] In some embodiments, the compensation circuit is used to apply a control voltage that decreases in response to an increase in the threshold voltage and increases in response to a decrease in the threshold voltage. In some embodiments, the compensation circuit is used to apply a control voltage that decreases in response to a decrease in temperature and increases in response to an increase in temperature.

[0195] In some embodiments, the compensation circuit is used to apply a control voltage so that the switching on or off of the sensing transistor is independent of changes in the threshold voltage of the sensing transistor (e.g., the sensing transistor is based on a threshold voltage equal to V). target Fixed V strobe (And turn on or off). The threshold voltage of the sensing transistor can be changed based on at least one of the temperature changes of the sensing transistor or the process variations in its manufacturing. The control voltage can make the turn-on condition of the sensing transistor independent of temperature changes within a set temperature range. The control voltage can make the switching voltage of the sensing transistor independent of the process variations in its manufacturing. In some embodiments, the sensing transistor includes a third terminal (e.g., ...). Figure 3 The drain terminal of the sensing transistor 310 shown is used for reading during integrated circuit operation (e.g., during the readout of the integrated circuit). Figure 4C (As shown) Received current (e.g.: Figure 4C The current shown is 408. The integrated circuit may also include a pre-charge circuit (e.g., 408). Figure 3 The pre-charging circuit 302 shown is coupled to the sensing node (e.g., the pre-charging circuit 302). Figure 3 The sensing node 318 shown is used to precharge the sensing node to the supply voltage (e.g., during precharging) during precharging. Figure 3 The power supply voltage VDDI is shown. Integrated circuits may also include bit line control circuitry (e.g., ...). Figure 3 The bit line control circuit 304 shown includes a first control node and a second control node. The first control node is coupled to the bit line of the memory cell (e.g., ...). Figure 3 The control node shown is coupled to the bit line 312 of memory cell 314. The second control node is coupled to the sensing node. The bit line control circuitry is used to precharge the bit line during precharge (e.g., during precharge). Figure 4A As shown), the sensing voltage of the sensing node is released by conductively connecting the sensing node to the bit line (e.g., by turning on the signal). Figure 4B Transistor 326 shown), to discharge during the pre-charge period (as shown) Figure 4BAs shown), in some embodiments, the latching circuit provides a sensing current to the memory cell. During a read operation, when the bit value stored in the memory cell is 1 and the sensing voltage of the sensing node is not greater than the target voltage, the sensing transistor is turned off to maintain the bit value latched by the latch at 1; and when the bit value stored in the memory cell is 0 and the sensing voltage of the sensing node is greater than the target voltage, the sensing transistor is turned on to set the bit value latched by the latch to 0 (e.g., ...). Figure 4C (As shown) In some embodiments, the integrated circuit includes a capacitor coupled to the sensing node (such as...) Figure 3 The capacitor shown is 320.

[0196] The integrated circuit at the core of process 700 includes latches (such as...) Figure 3 The latch unit 346 shown) and sensing transistor (such as Figure 3 The sensing transistor 310 is shown. A latch is used to latch data. The sensing transistor includes a gate, a first terminal, and a second terminal, wherein the gate is coupled to a sensing node (e.g., a sensing transistor 310). Figure 3 The sensing node 318 is shown. A first terminal is coupled to a latch (e.g., the drain terminal of sensing transistor 310). A second terminal is used to receive a control voltage (e.g., the source terminal of sensing transistor 310). The sensing transistor is used to turn on or off to update the data in the latch according to the following (1) and (2): (1) the sensing voltage of the sensing node; (2) the target voltage (e.g., V) based on the control voltage and the threshold voltage of the sensing transistor. target =V control +V TH The control voltage is used to compensate for changes in the threshold voltage of the sensing transistor, so that the target voltage (e.g., V) is maintained. target It is independent of the change in the threshold voltage of the sensing transistor.

[0197] In step 702 of process 700, a control voltage is provided to the sensing transistor of the integrated circuit. The sensing transistor includes a gate terminal coupled to the sensing node and another terminal for receiving the control voltage. For example, as Figure 3 and Figures 4A-4C As shown, a control voltage is provided to the source terminal of the sensing transistor 310, and the gate terminal of the sensing transistor 310 is coupled to the sensing node 318. The control voltage is provided by the compensation circuit 308.

[0198] During discharge, the sensed voltage of the discharge sense node is sensed via the bit line coupled to the memory cell (step 704). For example, as Figure 4B As shown, the sensing voltage of sensing node 318 is discharged to memory cell 314 through bit line 312. For example... Figure 5 As shown, the sensed voltage changes from the charging value V SEN,1 Change to discharge value V SEN,2.

[0199] As shown in step 706, the state of the memory cell is determined based on the following (1) and (2): (1) the discharge sensing voltage; (2) the target voltage based on the control voltage and the threshold voltage of the sensing transistor. For example, as Figure 4C As shown, when V SEN,2 Greater than V target Time (where V) target =V TH +V control The bit value stored in memory cell 314 is confirmed as 0. When V SEN,2 Not greater than V target At that time, the bit value stored in memory cell 314 is confirmed as 1. The control voltage is used to compensate for changes in the threshold voltage of the sensing transistor, so that the target voltage is independent of changes in the threshold voltage of the sensing transistor.

[0200] In some embodiments, the method of providing a control voltage includes providing a lower control voltage in response to an increase in a threshold voltage, and providing a higher control voltage in response to a decrease in the threshold voltage. In some embodiments, the method of providing a control voltage includes providing a lower control voltage in response to a decrease in temperature, and increasing the control voltage in response to an increase in temperature.

[0201] This disclosure can be varied, modified, and enhanced based on the foregoing embodiments. For example, while this disclosure describes a page buffer circuit 300 including an N-channel transistor sensing transistor 310, in other embodiments, the sensing transistor may also be a P-channel transistor. In this case, the aforementioned operation and circuit coupling (e.g., on / off state, source terminal coupling, and opposite drain terminal coupling) will be reversed. Since this variation is understood by those skilled in the art, it will not be described further here. In another embodiment, although a control voltage is applied to the source terminal of the sensing transistor 310, in some embodiments, the control voltage may be applied to the other end of the sensing transistor and / or other locations in the page buffer circuit 300 to compensate for the threshold voltage V. TH The changes.

[0202] The disclosure and embodiments, as well as various aspects thereof, such as providing V targetThe method of controlling voltage can be implemented by one or more computer software. For example, one or more computer program modules installed on a computer-readable medium are used to execute or control various operations via a data processing device. The computer-readable medium can be a machine-readable memory, a machine-readable storage substrate, a memory device, or a combination thereof. The aforementioned data processing device encompasses all devices, apparatuses, and machines for processing data, such as a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the aforementioned device can also be computer program code. For example, processor firmware, a protocol stack, a database management system, an operating system, composite code, or a combination thereof.

[0203] The system may include all means, devices, and machines for processing data, such as programmable processors, computers, or multiple processors or computers. In addition to hardware, the system may also include the aforementioned computer program code, such as processor firmware, protocol stack, database management system, operating system, assembly code, or a combination of one or more of the above.

[0204] Computer programs (also known as programs, software, software application files, scripts, or code) can be written in any programming language, including compiled or interpreted languages. They can be set up in any form, including as standalone programs or as modules, components, subroutines, or other units suited to a computing environment. A computer program is not limited to a file corresponding to a file system. A program can be stored in a file containing other programs or data (e.g., one or more scripts stored in a markup language document), a single file dedicated to the program in question, or multiple coordinated files (e.g., files stored in one or more modules, subroutines, or portions of code). A computer program can be set up on one or more computers located at a site or distributed across multiple sites via a communication network.

[0205] The processes and logic described in this disclosure can be executed by one or more programmable processors that execute one or more computer programs to perform the aforementioned functions. The processes and logic can also be executed by dedicated logic circuitry, and the devices are implemented as dedicated logic circuitry, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs).

[0206] Processors suitable for executing computer programs include general-purpose and special-purpose microprocessors, as well as any one or more processors in any type of digital computer. Generally, a processor receives instructions and data from read-only memory or random access memory, or both. The basic elements of a computer include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes, or is operatively coupled to, receiving data from one or more mass storage devices for storage, such as magnetic disks, magneto-optical disks, or optical disks. However, a computer is not limited to having all of these features. Computer-readable media suitable for storing the instructions and data of a computer program can be any form of non-volatile memory, media, and storage device, such as semiconductor memory, like EPROM, EEPROM, and flash memory. The processor and memory can be attached to or integrated into dedicated logic circuitry.

[0207] While numerous details are described in this disclosure, these details are merely feature descriptions for specific embodiments and should not be construed as limiting the scope of the claims or the content of the protection asserted. The features described in the context of each embodiment may also be implemented in combination in the various embodiments. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0208] Furthermore, although features may be described as functioning in certain combinations, or even claimed as such, in some cases one or more claimed features may still be removed from that combination. The combinations claimed in this disclosure can be applied to various sub-combinations or variations thereof. Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as meaning that these operations must be performed in the specific order shown, or that all operations will yield the same expected result.

[0209] Some embodiments and implementation methods are disclosed herein, and the embodiments and implementation methods described herein may be changed, modified and enhanced based on the content of this disclosure.

Claims

1. An integrated circuit, comprising: A latching circuit includes a latch and a sensing transistor, wherein the sensing transistor is coupled to the latch; and A compensation circuit is coupled to the sensing transistor; The sensing transistor includes a gate terminal and a connection terminal. The gate terminal is coupled to a sensing node, and the connection terminal is coupled to the compensation circuit. The compensation circuit is used to provide a control voltage to the connection terminal to compensate for changes in a threshold voltage of the sensing transistor. The compensation circuit includes a compensation transistor that is matched with the sensing transistor.

2. The integrated circuit according to claim 1, wherein the control voltage is based on a preset voltage and a matching voltage, the change of the matching voltage being substantially equivalent to the change of the threshold voltage of the sensing transistor.

3. The integrated circuit of claim 2, wherein the sensing transistor is configured to receive a sensing voltage from the gate terminal; The sensing transistor is used to sense a memory cell based on a comparison result between the sensed voltage and the preset voltage; and The comparison result is independent of the change in the threshold voltage of the sensing transistor.

4. The integrated circuit of claim 3, wherein the sensing transistor is used for: When the sensing voltage varies within a range between a pre-charge voltage and the preset voltage, a bit value of 0 stored in the memory cell is sensed; and When the sensing voltage is lower than the preset voltage, a bit value of 1 stored in the memory cell is sensed.

5. The integrated circuit of claim 4, wherein the range between the pre-charge voltage and the preset voltage is fixed and independent of the change in the threshold voltage of the sensing transistor.

6. The integrated circuit of claim 1, wherein the compensation transistor comprises: A compensation gate terminal is coupled to a preset voltage; A first terminal is coupled to a supply voltage; and A second terminal is coupled to an input terminal of a buffer circuit, wherein the buffer circuit is used to provide the control voltage through an output terminal.

7. The integrated circuit of claim 6, wherein the control voltage is equivalent to a difference between the preset voltage and a threshold voltage of the compensation transistor.

8. The integrated circuit of claim 6, wherein the threshold voltage of the sensing transistor varies between a high threshold voltage and a low threshold voltage; and The preset voltage is greater than or equal to the high threshold voltage.

9. The integrated circuit of claim 6, wherein the compensation circuit is used to provide the control voltage to one source terminal of the compensation transistor.

10. The integrated circuit of claim 1, wherein the compensation circuit is used to provide the control voltage such that the on or off state of the sensing transistor is independent of the change in the threshold voltage of the sensing transistor.

11. The integrated circuit according to claim 1, further comprising: A pre-charge circuit is coupled to the sensing node and is used to pre-charge the sensing node to a supply voltage during a pre-charge period.

12. The integrated circuit of claim 11, further comprising: A bit line control circuit includes a first control node and a second control node, wherein the first control node is coupled to a bit line of a memory cell, and the second control node is coupled to the sensing node, wherein the bit line control circuit is used for: During this precharge period, the bit line is precharged; and During a discharge period following the pre-charge period, a sensing voltage on the sensing node is discharged by conductively connecting the sensing node to the bit line to provide a sensing current to the memory cell.

13. The integrated circuit of claim 12, wherein the latching circuit is used during a read operation to: When a bit stored in the memory cell is 1, and the sensing voltage at the sensing node is not greater than a target voltage, the sensing transistor is turned off, thus maintaining the bit value latched by the latch at 1; and When the bit value stored in the memory cell is 0 and the sensing voltage on the sensing node is greater than the target voltage, the sensing transistor is turned on to set the bit value to be latched by the latch to 0.

14. The integrated circuit of claim 1, wherein the sensing transistor is configured to receive a sensing voltage through the gate terminal, wherein the sensing transistor is configured to sense a memory cell based on a comparison result between the sensing voltage and a preset voltage; and The compensation circuit is used to provide the control voltage so that the preset voltage is greater than a common voltage of a common node, which is coupled to the gate terminal through a connecting transistor.

15. A memory device comprising: A memory array containing multiple memory cells; Multiple memory cell lines, and multiple connection lines connecting these memory cells in the memory array; and A page buffer circuit includes multiple page buffers coupled to memory cell lines, each of which includes: A latching circuit includes a latch and a sensing transistor coupled to each other; and A compensation circuit is coupled to the sensing transistor; The sensing transistor includes a gate terminal, a first terminal, and a second terminal. The gate terminal is coupled to a sensing node, the first terminal is coupled to the latch, and the second terminal is coupled to the compensation circuit. The compensation circuit is used to provide a control voltage to the second terminal to compensate for a change in a threshold voltage of the sensing transistor. The compensation circuit includes a compensation transistor that is matched with the sensing transistor.

16. The memory device of claim 15, wherein the sensing transistor is configured to receive a sensing voltage through the gate terminal, wherein the sensing transistor is configured to sense a memory cell based on a comparison result of the sensing voltage and a preset voltage; and The comparison result is independent of the change in the threshold voltage of the sensing transistor.

17. The memory device of claim 15, wherein a threshold voltage of the compensation transistor is substantially equivalent to the threshold voltage of the sensing transistor.

18. The memory device of claim 17, wherein the compensation transistor comprises: A compensation gate terminal is coupled to a preset voltage; A third terminal is coupled to a supply voltage; and A fourth terminal is coupled to an input terminal of a buffer circuit, wherein the buffer circuit is used to provide the control voltage through an output terminal.

19. An integrated circuit, comprising: A latch for latching data; and A sensing transistor includes a gate terminal, a first terminal and a second terminal, wherein the gate terminal is coupled to a sensing node, the first terminal is coupled to the latch, and the second terminal is used to receive a control voltage. The sensing transistor is used to be turned on or off to update the data in the latch according to a sensing voltage on the sensing node and a target voltage that varies according to the control voltage and a threshold voltage of the sensing transistor. The control voltage is used to compensate for a change in a threshold voltage of the sensing transistor, so that the target voltage is independent of the change in the threshold voltage of the sensing transistor.

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