High electron mobility transistor based on dual-potential-well composite channel and its fabrication method

Abstract

This invention relates to a high electron mobility transistor based on a dual-potential-well composite channel and its fabrication method, comprising: a substrate layer, a buffer layer, a composite channel layer, an isolation layer, a delta-doping planar doped layer, and a barrier layer stacked sequentially from bottom to top; a source cap layer and a drain cap layer disposed at both ends of the barrier layer; a source electrode disposed on the source cap layer; a drain electrode disposed on the drain cap layer; a gate electrode disposed on the barrier layer; and passivation layers continuously disposed on the source electrode, source cap layer, barrier layer, part of the drain cap layer, and part of the source electrode. This invention utilizes a dual-electron potential well to increase the device's output current, further improve the device's frequency characteristics, and also enhance its breakdown characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a high electron mobility transistor based on a dual-potential-well composite channel and its fabrication method. Background Technology

[0002] High electron mobility transistors (HEMTs) based on InP materials have the advantages of high frequency, high mobility, and high gain. Compared with GaAs and GaN materials, they also have the advantage of low noise figure. These advantages make InP-based HEMTs highly competitive in applications such as radio astronomy, communication systems, atmospheric imaging and sensing, automotive radar, and ground receivers in deep space networks.

[0003] The high-frequency characteristics of InP-based HEMTs benefit from the heterojunction formed by using different materials for the barrier layer and the channel layer, thereby obtaining a two-dimensional electron gas with high electron mobility in the channel layer and achieving high output current. Currently, many studies are dedicated to further improving the frequency characteristics. One approach is to increase the In content in the channel layer material, thereby giving the channel material higher electron mobility.

[0004] However, materials with high In content have narrower band gaps and higher impact ionization rates, making them highly susceptible to breakdown under high gate leakage fields. Limited by the low breakdown voltage of the device, the output power of InP-based HEMTs is difficult to improve. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a high electron mobility transistor based on a dual-potential-well composite channel and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] A high electron mobility transistor based on a dual-well composite channel, the high electron mobility transistor comprising:

[0007] The substrate layer, buffer layer, composite channel layer, isolation layer, delta-doping planar doped layer, and barrier layer are stacked sequentially from bottom to top.

[0008] The source cap layer and the drain cap layer are respectively disposed at both ends of the upper surface of the barrier layer;

[0009] A source electrode is disposed on a portion of the upper surface of the source cap layer;

[0010] A drain electrode is disposed on a portion of the upper surface of the drain cap layer;

[0011] A gate electrode is disposed on a portion of the upper surface of the barrier layer and located between the source electrode and the drain electrode;

[0012] A passivation layer is continuously disposed on the upper surface of a portion of the source electrode, a portion of the source cap layer, a barrier layer, a portion of the drain cap layer, and a portion of the source electrode.

[0013] The composite channel layer includes a first sub-channel layer, a first main channel layer, an intermediate barrier layer, a second main channel layer, and a second sub-channel layer stacked sequentially from bottom to top. The first sub-channel layer, the first main channel layer, the second main channel layer, and the second sub-channel layer are symmetrically arranged along the intermediate barrier layer. The first sub-channel layer and the second sub-channel layer have the same bandgap width, which is greater than the bandgap width of the intermediate barrier layer. The first main channel layer and the second main channel layer have the same bandgap width, which is less than the bandgap width of the intermediate barrier layer.

[0014] In one embodiment of the present invention, the materials of the first sub-channel layer and the second sub-channel layer both include undoped InP, and the materials of the first main channel layer and the second main channel layer both include undoped InGaAs.

[0015] In one embodiment of the present invention, the first sub-channel layer and the second sub-channel layer have the same thickness, the first main channel layer and the second main channel layer have the same thickness, the thickness of the intermediate barrier layer is greater than or equal to the thickness of the first main channel layer and the second main channel layer, and the thickness of the first main channel layer and the second main channel layer is greater than or equal to the thickness of the first sub-channel layer and the second sub-channel layer.

[0016] In one embodiment of the present invention, the composite channel layer further includes:

[0017] The first channel transition layer is disposed between the first secondary channel layer and the first main channel layer;

[0018] The second channel transition layer is disposed between the second secondary channel layer and the second main channel layer.

[0019] In one embodiment of the present invention, the first channel transition layer and the second channel transition layer are symmetrically arranged along the intermediate barrier layer, and the bandgap width of the first channel transition layer and the second channel transition layer is smaller than the bandgap width of the intermediate barrier layer. The bandgap widths of the first sub-channel layer, the first channel transition layer and the first main channel layer decrease sequentially, and the bandgap widths of the second sub-channel layer, the second channel transition layer and the second main channel layer decrease sequentially.

[0020] In one embodiment of the present invention, the first channel transition layer and the second channel transition layer have the same thickness, and the thickness of the first channel transition layer and the second channel transition layer is less than the thickness of the first sub-channel layer and the second sub-channel layer.

[0021] In one embodiment of the present invention, the materials of the first channel transition layer, the second channel transition layer and the intermediate barrier layer all comprise undoped InPSb.

[0022] In one embodiment of the present invention, the substrate layer is made of semi-insulating InP, the buffer layer is made of undoped InAlAs, the isolation layer is made of undoped InAlAs, the delta-doping planar doped layer is made of Si, the barrier layer is made of undoped InAlAs, and the source cap layer and the drain cap layer are both made of heavily doped InGaAs.

[0023] In one embodiment of the present invention, the high electron mobility transistor further includes:

[0024] A source metal interconnect is disposed on a portion of the upper surface of the source electrode;

[0025] A drain metal interconnect is disposed on a portion of the upper surface of the drain electrode;

[0026] A gate metal interconnect is disposed on the upper surface and part of the side surface of the gate electrode.

[0027] An embodiment of the present invention also provides a method for fabricating a high electron mobility transistor based on a dual-potential-well composite channel. The fabrication method is used to fabricate a high electron mobility transistor as described in any of the above embodiments, and the fabrication method includes:

[0028] Select a substrate layer;

[0029] A buffer layer is grown on the substrate layer;

[0030] A first sub-channel layer, a first main channel layer, an intermediate barrier layer, a second main channel layer, and a second sub-channel layer are sequentially grown on the buffer layer from bottom to top to obtain a composite channel layer.

[0031] An isolation layer is grown on the composite channel layer;

[0032] A delta-doping planar doped layer is grown on the isolation layer;

[0033] A barrier layer is grown on the delta-doping planar doped layer;

[0034] Cap layer material is grown at both ends of the upper surface of the barrier layer;

[0035] Metal evaporation is performed on the capping material to fabricate the source electrode and the drain electrode;

[0036] The capping material is etched to form a gate groove, a source cap, and a drain cap;

[0037] A gate electrode is fabricated by evaporating gate metal on a portion of the barrier layer of the gate recess.

[0038] A passivation layer is formed on the upper surface of the source electrode, the source cap layer, the barrier layer, the drain cap layer, and the drain electrode.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] In this invention, the first sub-channel layer, the first main channel layer, the second main channel layer, and the second sub-channel layer of the composite channel layer are symmetrically arranged along the intermediate barrier layer. Furthermore, the band gaps of the first and second sub-channel layers are the same and larger than the band gap of the intermediate barrier layer, while the band gaps of the first and second main channel layers are the same and smaller than the band gap of the intermediate barrier layer. This difference in material band gaps forms a dual-electron potential well band structure, thus creating a dual-channel structure. Compared to the traditional InGaAs single-potential-well band structure, this dual-electron potential well confines more electrons to the channel layer, thereby increasing the concentration of the two-dimensional electron gas within the channel layer. This composite channel layer structure, utilizing the dual-electron potential well, improves the device's output current, further enhances the device's frequency characteristics, and also improves its breakdown characteristics.

[0041] In the composite channel layer provided by this invention, because the band gap widths of the first sub-channel layer and the second sub-channel layer are larger than the band gap width of the intermediate barrier layer, and the band gap widths of the first main channel layer and the second main channel layer are smaller than the band gap width of the intermediate barrier layer, electrons move in the first main channel layer and the second main channel layer under low electric field. Utilizing the high electron mobility and high two-dimensional electron gas concentration of the material, a larger output current is provided. Under high electric field, electrons enter the first sub-channel layer and the second sub-channel layer from the first main channel layer and the second main channel layer, allowing electrons to move in the first sub-channel layer and the second sub-channel layer. Utilizing the high breakdown characteristics of the first sub-channel layer and the second sub-channel layer, with a high electron saturation velocity, the breakdown voltage of the device is increased while ensuring the output current.

[0042] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0043] Figure 1This is a schematic diagram of a high electron mobility transistor based on a dual-well composite channel provided in an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of another high electron mobility transistor based on a dual-well composite channel provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic flowchart of a method for fabricating a high electron mobility transistor based on a dual-potential-well composite channel, provided in an embodiment of the present invention.

[0046] Figures 4a-4k This is a schematic diagram of the fabrication process of a high electron mobility transistor based on a dual-well composite channel provided in an embodiment of the present invention. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0048] Example 1

[0049] Please see Figure 1 , Figure 1 This is a schematic diagram of a high electron mobility transistor based on a dual-well composite channel according to an embodiment of the present invention. The present invention provides a high electron mobility transistor based on a dual-well composite channel, which includes:

[0050] The following layers are stacked sequentially from bottom to top: substrate layer 1, buffer layer 2, composite channel layer 3, isolation layer 4, delta-doping planar doped layer (i.e., δ-doped layer) 5, and barrier layer 6.

[0051] The source cap layer 7 and the drain cap layer 8 are respectively disposed at both ends of the upper surface of the barrier layer 6;

[0052] Source electrode 9 is disposed on a portion of the upper surface of source cap layer 7;

[0053] Drain electrode 10 is disposed on a portion of the upper surface of drain cap layer 8;

[0054] The gate electrode 11 is disposed on a portion of the upper surface of the barrier layer 6 and is located between the source electrode 9 and the drain electrode 10.

[0055] A passivation layer 12 is continuously disposed on the upper surface of a portion of the source electrode 9, a portion of the source cap layer 7, a barrier layer 6, a portion of the drain cap layer 8, and a portion of the source electrode 9.

[0056] Source metal interconnect 91 is disposed on a portion of the upper surface of source electrode 9;

[0057] A drain metal interconnect 101 is disposed on a portion of the upper surface of the drain electrode 10;

[0058] Gate metal interconnect 111 is disposed on the upper surface and part of the side surface of gate electrode 11.

[0059] The composite channel layer 3 includes a first sub-channel layer 31, a first main channel layer 33, an intermediate barrier layer 34, a second main channel layer 35, and a second sub-channel layer 37, which are stacked sequentially from bottom to top. The first sub-channel layer 31, the first main channel layer 33, the second main channel layer 35, and the second sub-channel layer 37 are symmetrically arranged along the intermediate barrier layer 34. The bandgap widths of the first sub-channel layer 31 and the second sub-channel layer 37 are the same and greater than the bandgap width of the intermediate barrier layer 34. The bandgap widths of the first main channel layer 33 and the second main channel layer 35 are the same and smaller than the bandgap width of the intermediate barrier layer 34.

[0060] In the composite channel layer 3 of the present invention, the first sub-channel layer 31, the first main channel layer 33, the second main channel layer 35, and the second sub-channel layer 37 are symmetrically arranged along the intermediate barrier layer 34. The first sub-channel layer 31 and the second sub-channel layer 37 have the same bandgap width, the first main channel layer 33 and the second main channel layer 35 have the same bandgap width, and the bandgap width of the first sub-channel layer 31 and the second sub-channel layer 37 is greater than the bandgap width of the first main channel layer 33 and the second main channel layer 35, presenting a stepped shape. The bandgap width of the intermediate barrier layer is higher than that of the main channel, thereby forming a potential well structure. This invention utilizes the different band gaps of materials to form a dual-electron potential well band structure. Compared with the traditional InGaAs single-potential-well band structure, this dual-electron potential well has a stronger binding capacity, enabling it to bind more electrons to the channel layer (electrons tend to converge in the main channel layer at low electric fields and in the secondary channel layer at high electric fields), thereby increasing the concentration of two-dimensional electron gas within the channel layer. This composite channel layer structure, utilizing the dual-electron potential well, improves the output current of the device and further enhances its frequency characteristics.

[0061] In the composite channel layer provided by this invention, because the bandgap widths of the first sub-channel layer 31 and the second sub-channel layer 37 are greater than the bandgap width of the intermediate barrier layer 34, and the bandgap widths of the first main channel layer 33 and the second main channel layer 35 are smaller than the bandgap width of the intermediate barrier layer 34, electrons move in the first main channel layer 33 and the second main channel layer 35 under low electric field. Utilizing the high electron mobility and high two-dimensional electron gas concentration of the main channel layer, a larger output current is provided. Under high electric field, electrons enter the first sub-channel layer 31 from the first main channel layer 33 and enter the second sub-channel layer 37 from the second main channel layer 35, allowing electrons to move in the first sub-channel layer 31 and the second sub-channel layer 37. Utilizing the high breakdown characteristics of the first sub-channel layer 31 and the second sub-channel layer 37, with a high electron saturation velocity, the breakdown voltage of the device is increased while ensuring the output current.

[0062] Optionally, the materials of the first sub-channel layer 31 and the second sub-channel layer 37 both include undoped InP, and the materials of the first main channel layer 33 and the second main channel layer 35 both include undoped InGaAs.

[0063] This invention utilizes the advantages of a dual-electron potential well and the high electron mobility of the high In composition of the main channel layer to improve the output current of the device and further enhance the frequency characteristics of the device.

[0064] The high electron mobility transistor provided by this invention utilizes the difference in bandgap width of the materials to form a double-well band structure, thereby forming a dual-channel structure. This allows more electrons to remain in the channel layer while increasing the concentration of In component in the main channel layer. Under low electric field conditions, electrons move in the undoped InGaAs main channel layer, utilizing the high electron mobility and high two-dimensional electron gas concentration of the main channel layer to provide a larger output current. Under high electric field conditions, electrons transfer from the InGaAs main channel layer to the InP secondary channel layer. Utilizing the wide bandgap, high breakdown characteristics, and high electron saturation velocity of InP material, the breakdown voltage of the device is increased while ensuring the output current. Furthermore, the use of undoped InP material in the secondary channel layer, due to its lower ionization collision coefficient, can alleviate the problem of high ionization collision rate under high electric field conditions.

[0065] Furthermore, the first sub-channel layer 31 and the second sub-channel layer 37 have the same thickness, the first main channel layer 33 and the second main channel layer 35 have the same thickness, the thickness of the intermediate barrier layer 34 is greater than or equal to the thickness of the first main channel layer 33 and the second main channel layer 35, and the thickness of the first main channel layer 33 and the second main channel layer 35 is greater than or equal to the thickness of the first sub-channel layer 31 and the second sub-channel layer 37. This is because the intermediate barrier layer 34 separates the symmetrically arranged channels, and therefore the intermediate barrier layer 34 is the thickest; for the high electron mobility transistor of the present invention, it is preferred that electrons remain in the main channel layer and only need to enter the sub-channel layer under a high electric field, therefore the main channel layer is set to be greater than or equal to the sub-channel layer.

[0066] Optionally, the thickness of the first sub-channel layer 31 and the second sub-channel layer 37 is 3-5 nm, the thickness of the first main channel layer 33 and the second main channel layer 35 is 3-5 nm, and the thickness of the intermediate barrier layer 34 is 3-6 nm.

[0067] Optionally, the In composition of both the first main channel layer 33 and the second main channel layer 35 is 60-80%.

[0068] In one specific embodiment, please refer to Figure 2 The composite channel layer 3 also includes:

[0069] The first channel transition layer 32 is disposed between the first secondary channel layer 31 and the first main channel layer 33;

[0070] The second channel transition layer 36 is disposed between the second secondary channel layer 37 and the second main channel layer 35.

[0071] Furthermore, the first channel transition layer 32 and the second channel transition layer 36 are symmetrically arranged along the intermediate barrier layer 34, and the bandgap width of the first channel transition layer 32 and the second channel transition layer 36 is smaller than the bandgap width of the intermediate barrier layer 34. The bandgap widths of the first sub-channel layer 31, the first channel transition layer 32 and the first main channel layer 33 decrease sequentially, and the bandgap widths of the second sub-channel layer 31, the second channel transition layer 36 and the second main channel layer 33 decrease sequentially.

[0072] This invention incorporates a channel transition layer between the secondary channel layer and the primary channel layer. This results in a progressively decreasing bandgap between the secondary channel layer, the channel transition layer, and the primary channel layer, forming a stepped structure. Furthermore, the bandgap of the intermediate barrier layer is higher than that of the primary channel, creating a potential well structure. The bandgap of the first and second channel transition layers is smaller than that of the intermediate barrier layer. This allows electrons to more readily transition to the channel transition layer and then to the secondary channel layer under a high electric field. The channel transition layer acts as a transition layer, forming a stepped structure. Electrons can then transition twice (from the primary channel layer to the channel transition layer, and then from the channel transition layer to the secondary channel layer), facilitating smoother entry into the secondary channel layer. As the electric field gradually increases, the function of the secondary channel layer is better realized.

[0073] Optionally, the thickness of the first channel transition layer 32 and the second channel transition layer 36 is the same, and the thickness of the first channel transition layer 32 and the second channel transition layer 36 is less than the thickness of the first sub-channel layer 31 and the second sub-channel layer 37. The intermediate barrier layer 34 serves as a separator between the two channels. The channel transition layer serves as a transition structure for electron transition. If the thickness of the channel transition layer is greater than that of the main channel layer and the sub-channel layer, it will be unfavorable for electrons to enter the sub-channel layer. Therefore, the thickness of the channel transition layer is the thinnest.

[0074] Optionally, the materials of the first channel transition layer 32, the second channel transition layer 36, and the intermediate barrier layer 34 all include undoped InPSb.

[0075] Optionally, the P composition in the first channel transition layer 32 and the second channel transition layer 36 is 80%, and the P composition in the intermediate barrier layer 34 is 90%.

[0076] This invention adds an undoped InPSb channel transition layer between the undoped InGaAs main channel layer and the undoped InP secondary channel layer. The purpose is to allow electrons to undergo two transitions, making it easier for electrons to enter the InP secondary channel. Therefore, the composite channel structure provided by this invention not only ensures the device's cutoff frequency and maximum oscillation frequency but also improves the device's breakdown characteristics.

[0077] The high electron mobility transistor provided by this invention is based on InP material. It takes into account the material properties of lattice matching, electron mobility, electron saturation velocity, bandgap width, and collisional ionization coefficient. Therefore, the composite channel structure adopts InP / InPSb / InGaAs / InPSb / InGaAs / InPSb / InP.

[0078] Furthermore, the thickness of the first channel transition layer and the second channel transition layer is 2-3 nm.

[0079] Optionally, the substrate layer 1 is made of semi-insulating InP, the buffer layer 2 is made of undoped InAlAs, the isolation layer 4 is made of undoped InAlAs, and the delta-doping planar doped layer 5 is made of Si with a doping concentration of 5 × 10⁻⁶. 12 cm -2 The barrier layer 6 is made of undoped InAlAs, while the source cap layer 7 and drain cap layer 8 are both made of heavily doped InGaAs. The InGaAs cap layer is heavily doped using SiH4 as the doping source, with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -3×10 19 cm -3 .

[0080] Optionally, the thickness of the buffer layer 2 is 500-550nm, the thickness of the isolation layer 4 is 2-3nm, the thickness of the barrier layer 6 is 10-12nm, and the thickness of the source cap layer 7 and the drain cap layer 8 is 30-35nm.

[0081] Optionally, the first channel transition layer 32, the first main channel layer 33, the intermediate barrier layer 34, the second main channel layer 35, and the second channel transition layer 36 are InP 0.8 Sb 0.2 / In 0.75 Ga 0.25 As / InP 0.8 Sb 0.2 / In 0.75 Ga 0.25 As / InP 0.8 Sb 0.2 .

[0082] Currently, existing composite channel structures consist of a first sub-channel layer, a second sub-channel layer, a main channel layer, and a third sub-channel layer arranged sequentially from bottom to top. Compared to this composite channel structure, this invention incorporates InPSb material as an intermediate barrier layer and employs a symmetrical epitaxial structure to form a dual-electron potential well. Compared to the aforementioned composite channel structure, the dual-potential-well channel structure used in this invention has a stronger electron-binding ability, thereby achieving higher transconductance characteristics and improving the device's cutoff frequency. Furthermore, this invention adds an InPSb channel transition layer between the main channel layer and the sub-channel layer. Under high electric fields, the InPSb channel transition layer can act as a stepping stone for electron transitions, allowing more electrons to enter the sub-channel layer, an effect that existing composite channel structures cannot achieve.

[0083] In addition, compared with InGaAs material, the advantages of using InPSb channel transition layer are: InPSb has a higher breakdown electric field; under high electric field, it has a higher electron saturation velocity; InGaAs material has a higher collisional ionization coefficient, which leads to a high collisional ionization rate in its channel, which is the main factor for breakdown of InP HEMT devices.

[0084] Example 2

[0085] Please see Figure 3 , Figures 4a-4k , Figure 3 This is a schematic flowchart of a method for fabricating a high electron mobility transistor based on a dual-potential-well composite channel according to an embodiment of the present invention. Figures 4a-4k This is a schematic diagram of the fabrication process of a high electron mobility transistor based on a dual-well composite channel according to an embodiment of the present invention. Based on Embodiment 1, the present invention also provides a method for fabricating a high electron mobility transistor based on a dual-well composite channel, the method comprising:

[0086] Step 1: Select substrate layer 1.

[0087] Optionally, the material of the substrate layer 1 includes semi-insulating InP.

[0088] Step 2, as follows Figure 4a As shown, a buffer layer 2 is grown on substrate layer 1.

[0089] Optionally, the material of buffer layer 2 includes undoped InAlAs, and the thickness of buffer layer 2 is 500-550 nm.

[0090] Step 3: On the buffer layer 2, the first sub-channel layer 31, the first main channel layer 33, the intermediate barrier layer 34, the second main channel layer 35, and the second sub-channel layer 37 are sequentially grown from bottom to top to obtain the composite channel layer 3.

[0091] Furthermore, a first channel transition layer 32 is grown between the first sub-channel layer 31 and the first main channel layer 33, and a second channel transition layer 36 is grown between the second main channel layer 35 and the second sub-channel layer 37.

[0092] In other words, such as Figure 4b As shown, firstly, a first sub-channel layer 31 is grown on the buffer layer 2; a first channel transition layer 32 is grown on the first sub-channel layer 31; a first main channel layer 33 is grown on the first channel transition layer 32; an intermediate barrier layer 34 is grown on the first main channel layer 33; a second main channel layer 35 is grown on the intermediate barrier layer 34; a second channel transition layer 36 is grown on the second main channel layer 35; and a second sub-channel layer 37 is grown on the second channel transition layer 36.

[0093] Optionally, the materials of the first sub-channel layer 31 and the second sub-channel layer 37 both include undoped InP, the materials of the first main channel layer 33 and the second main channel layer 35 both include undoped InGaAs, and the materials of the first channel transition layer 32, the second channel transition layer 36 and the intermediate barrier layer 34 all include undoped InPSb.

[0094] Optionally, the thickness of the first main channel layer 33 and the second main channel layer 35 is 3-5 nm, the In composition of the first main channel layer 33 and the second main channel layer 35 is 60-80%, the thickness of the first channel transition layer and the second channel transition layer is 2-3 nm, the P composition of the first channel transition layer and the second channel transition layer is 80%, and the thickness of the intermediate barrier layer is 3-6 nm.

[0095] Step 4, as follows Figure 4c As shown, an isolation layer 4 is grown on the composite channel layer 3.

[0096] Optionally, the material of the isolation layer 4 includes undoped InAlAs, and the thickness of the isolation layer 4 is 2-3 nm.

[0097] Step 5, as follows Figure 4d As shown, a delta-doping planar doped layer 5 is grown on the isolation layer 4.

[0098] Optionally, the delta-doping planar doped layer 5 is made of Si with a doping concentration of 5 × 10⁻⁶. 12 cm -2 .

[0099] Step 6, as follows Figure 4e As shown, a barrier layer 6 is grown on the delta-doping planar doped layer 5.

[0100] Optionally, the material of barrier layer 6 includes undoped InAlAs, and the thickness of barrier layer 6 is 10-12 nm.

[0101] Step 7, as follows Figure 4f As shown, capping material 13 is grown at both ends of the upper surface of barrier layer 6.

[0102] Step 8, as follows Figure 4g As shown, metal evaporation is performed on the capping material 13 to fabricate the source electrode 9 and the drain electrode 10.

[0103] Step 10, as follows Figure 4h As shown, the cap material 13 is etched to form a gate groove, a source cap layer 7, and a drain cap layer 8.

[0104] Optionally, both the source cap layer 7 and the drain cap layer 8 are made of heavily doped InGaAs. The InGaAs cap layer is heavily doped using SiH4 as the doping source, with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -3×10 19 cm -3 The source cap layer 7 and drain cap layer 8 have a thickness of 30-35 nm.

[0105] Step 11, as follows Figure 4i As shown, gate metal is evaporated on a portion of the barrier layer 6 in the gate groove to fabricate the gate electrode 11.

[0106] Step 12, as follows Figure 4j As shown, a passivation layer 12 is fabricated on the upper surface of the source electrode 9, the source cap layer 7, the barrier layer 6, the drain cap layer 8, and the drain electrode 10.

[0107] Step 13, as follows Figure 4k As shown, an opening is made in the passivation layer 12, and a source metal interconnect 91 is fabricated on the source electrode 9, a drain metal interconnect 101 is fabricated on the drain electrode 10, and a gate metal interconnect 111 is fabricated on the gate electrode 11.

[0108] Specifically, step 13 includes two steps: passivation layer opening and interconnect metal evaporation. The passivation layer opening is performed using plasma etching with CF4 gas as the etchant.

[0109] In the above examples of the present invention, MOCVD method is used to epitaxially grow material layers with different functions.

[0110] This invention provides a high electron mobility transistor comprising a composite channel layer. This composite channel layer utilizes the difference in bandgap widths of the materials to form a double-well band structure, thereby creating a dual-channel structure. This allows more electrons to remain within the channel layer while simultaneously increasing the In concentration in the main channel. Under low electric field conditions, the high electron mobility and high two-dimensional electron gas concentration of the materials provide a larger output current. Under high electric field conditions, electrons transfer from the InGaAs main channel layer to the InP secondary channel layer. Utilizing the high breakdown characteristics of InP material, a high electron saturation velocity is achieved, ensuring the output current while increasing the device's breakdown voltage. In the composite channel layer of this invention, an InPSb transition layer is provided between the InGaAs main channel layer and the InP secondary channel layer to facilitate two electron transitions, making it easier for electrons to enter the InP secondary channel layer. Therefore, the high electron mobility transistor with a composite channel layer provided by this invention ensures both the device's cutoff frequency and maximum oscillation frequency while improving its breakdown characteristics.

[0111] Example 3

[0112] This embodiment, based on Embodiment 2, also provides a specific method for fabricating a high electron mobility transistor based on a dual-potential-well composite channel. The fabrication method includes:

[0113] Step 1: Using MOCVD process, grow an undoped InAlAs buffer layer 2 on a semi-insulating InP substrate layer 1.

[0114] Specifically, using TMIn as the indium source, TMAl as the aluminum source, and AsH3 as the arsenic source, a 500 nm undoped InAlAs material buffer layer 2 was grown under process conditions of 650℃.

[0115] Step 2: Grow the composite channel layer 3 on the undoped InAlAs buffer layer 2. Specifically, this includes:

[0116] Step 2.1: Using MOCVD process, grow the first sub-channel layer 31 of undoped InP material on the buffer layer 2 of undoped InAlAs material.

[0117] Specifically, using TMIn as the indium source and PH3 as the phosphorus source, a 3 nm undoped InP material first sub-channel layer 31 was grown at a temperature of 650℃.

[0118] Step 2.2: Using MOCVD process, grow the first channel transition layer 32 of undoped InPSb material on the first sub-channel layer 31 of undoped InP material.

[0119] Specifically, using TMI as the indium source, PH3 as the phosphorus source, and TMSb as the antimony source, a 2 nm undoped InPSb material first channel transition layer 32 was grown at a temperature of 500°C.

[0120] Step 2.3: Using MOCVD process, grow the first main channel layer 33 of undoped InGaAs material on the first channel transition layer 32 of undoped InPSb material.

[0121] Specifically, using TMI as the indium source, TMI as the gallium source, and TMI as the arsenic source, a 3 nm undoped InGaAs material first main channel layer 33 was grown at a temperature of 650 °C.

[0122] Step 2.4: Using MOCVD process, grow an undoped InPSb intermediate barrier layer 34 on the first main channel layer 33 of undoped InGaAs material.

[0123] Specifically, using TMI as the indium source, PH3 as the phosphorus source, and TMSb as the antimony source, a 3 nm undoped InPSb intermediate barrier layer 34 was grown at a temperature of 500 °C.

[0124] Step 2.5: Using MOCVD process, an undoped InGaAs second main channel layer 35 is formed on an undoped InPSb intermediate barrier layer 34.

[0125] Specifically, using TMI as the indium source, TMI as the gallium source, and TMI as the arsenic source, a 3 nm undoped InGaAs material second main channel layer 35 was grown at a temperature of 650 °C.

[0126] Step 2.6: Using MOCVD process, grow an undoped InPSb second channel transition layer 36 on the undoped InGaAs second main channel layer 35.

[0127] Specifically, using TMI as the indium source, PH3 as the phosphorus source, and TMSb as the antimony source, a 2 nm undoped InPSb material second channel transition layer 36 was grown at a temperature of 500°C.

[0128] Step 2.7: Using MOCVD process, grow a second sub-channel layer 37 of undoped InP material on the second channel transition layer 36 of undoped InPSb material.

[0129] Specifically, using PH3 as the phosphorus source, a second sub-channel layer 37 of 3 nm undoped InP material was grown at a temperature of 650℃.

[0130] Step 3: Using MOCVD process, grow an undoped InAlAs isolation layer 4 on the composite channel layer 3.

[0131] Specifically, using TMIn as the indium source, TMAl as the aluminum source, and AsH3 as the arsenic source, a 3 nm undoped InAlAs material isolation layer 4 was grown at a temperature of 650℃.

[0132] Step 4: Using MOCVD technology, a delta-doped planar doped layer 5 is grown on the undoped InAlAs material isolation layer 4.

[0133] Specifically, it is grown at 650℃, using SiH4 as the doping source, with a doping concentration of 5×10⁻⁶. 12 cm -2 .

[0134] Step 5: Using MOCVD process, grow an undoped InAlAs barrier layer 6 on the delta-doping planar doped layer 5.

[0135] Specifically, using TMIn as the indium source, TMAl as the aluminum source, and AsH3 as the arsenic source, a 12nm undoped InAlAs barrier layer 6 was grown at a temperature of 650℃.

[0136] Step 6: Growing n on the undoped InAlAs barrier layer 6 + The capping material of InGaAs specifically includes:

[0137] Using MOCVD technology, with TMIn as the indium source, TMGa as the gallium source, AsH3 as the arsenic source, and SiH4 as the n-type dopant source, a thickness of 30 nm was grown at 650℃. + The capping material of InGaAs, with a doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0138] Step 7: Fabricate the source electrode 9 and drain electrode 10 on the cap layer material.

[0139] Specifically, the photoresist is first spun at 5000 rpm to obtain 0.8 μm photoresist, then baked in a high-temperature oven at 80℃ for 10 min. The photoresist is then exposed to form source and drain region mask patterns. The source and drain electrodes are then fabricated using an electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The source and drain metals are Ti / Al / Ni / Au, with Ti having a thickness of 20 nm, Al having a thickness of 120 nm, Ni having a thickness of 45 nm, and Au having a thickness of 55 nm. After the source and drain ohmic contact metals are evaporated, the metals are stripped to complete the fabrication of source electrode 9 and drain electrode 10.

[0140] Step 8: Etch the gate trench to separate the capping material into source capping layer 7 and drain capping layer 8.

[0141] Specifically, the photoresist is first spun at 5000 rpm to obtain a 0.8 μm photoresist layer. Then, it is baked in a high-temperature oven at 80°C for 10 minutes, followed by exposure using a photolithography machine to form the gate recess mask pattern. A wet etching process is then employed, using a mixed solution of saturated succinic acid and hydrogen peroxide to etch away the capping material in the middle section, ultimately leaving the source capping layer 7 and the drain capping layer 8.

[0142] Step 9: Evaporate the gate metal in the center of the gate groove to fabricate the gate electrode 11.

[0143] Specifically, the photoresist is first spun at 5000 rpm to obtain 0.8 μm of photoresist, then baked in a high-temperature oven at 80°C for 10 min, and exposed using a photolithography machine to obtain the gate mask pattern. Then, the gate metal is evaporated at a rate of 0.1 nm / s using an electron beam evaporation stage to cover the top of the barrier layer. The metals selected are Ni and Au, with Ni having a thickness of 20 nm and Au having a thickness of 200 nm. After evaporation, the metal is stripped to obtain the gate electrode 11.

[0144] Step 10: Deposit the surface passivation layer.

[0145] Specifically, a passivation layer 12 of SiN material was deposited using the PECVD method, with NH3 as the N source and SiH4 as the Si source, and a passivation layer of SiN material with a thickness of 60 nm was deposited on the surface at a deposition temperature of 250℃.

[0146] Step 11: Create holes on the surface and fabricate metal interconnect leads.

[0147] Specifically, positive resist is first spun at 5000 rpm using a spin coater, followed by exposure using a photolithography machine to form the electrode lead mask pattern. A plasma etching machine is then used to etch away the passivation layer in the lead area at a rate of 0.5 nm / s in CF4 plasma. After obtaining the electrode lead mask pattern using the same photolithography method, the lead electrode metal is evaporated from the substrate with the mask fabricated using an electron beam evaporation stage at an evaporation rate of 0.3 nm / s. The metal used is Ti with a thickness of 20 nm and Au with a thickness of 200 nm. Finally, after the lead electrode metal evaporation is complete, the substrate is stripped to obtain the complete lead electrode.

[0148] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0149] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0150] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0151] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. A high electron mobility transistor based on a dual-potential-well composite channel, characterized in that, The high electron mobility transistor includes: The substrate layer, buffer layer, composite channel layer, isolation layer, delta-doping planar doped layer, and barrier layer are stacked sequentially from bottom to top. The source cap layer and the drain cap layer are respectively disposed at both ends of the upper surface of the barrier layer; A source electrode is disposed on a portion of the upper surface of the source cap layer; A drain electrode is disposed on a portion of the upper surface of the drain cap layer; A gate electrode is disposed on a portion of the upper surface of the barrier layer and located between the source electrode and the drain electrode; A passivation layer is continuously disposed on the upper surface of a portion of the source electrode, a portion of the source cap layer, a barrier layer, a portion of the drain cap layer, and a portion of the source electrode. The composite channel layer includes a first sub-channel layer, a first main channel layer, an intermediate barrier layer, a second main channel layer, and a second sub-channel layer stacked sequentially from bottom to top. The first sub-channel layer, the first main channel layer, the second main channel layer, and the second sub-channel layer are symmetrically arranged along the intermediate barrier layer. The first sub-channel layer and the second sub-channel layer have the same bandgap width, which is greater than the bandgap width of the intermediate barrier layer. The first main channel layer and the second main channel layer have the same bandgap width, which is less than the bandgap width of the intermediate barrier layer.

2. The high electron mobility transistor based on a dual-well composite channel according to claim 1, characterized in that, The materials of the first sub-channel layer and the second sub-channel layer both include undoped InP, and the materials of the first main channel layer and the second main channel layer both include undoped InGaAs.

3. The high electron mobility transistor based on a dual-potential-well composite channel according to claim 1, characterized in that, The first sub-channel layer and the second sub-channel layer have the same thickness, the first main channel layer and the second main channel layer have the same thickness, the thickness of the intermediate barrier layer is greater than or equal to the thickness of the first main channel layer and the second main channel layer, and the thickness of the first main channel layer and the second main channel layer is greater than or equal to the thickness of the first sub-channel layer and the second sub-channel layer.

4. The high electron mobility transistor based on a dual-potential-well composite channel according to claim 3, characterized in that, The composite channel layer further includes: The first channel transition layer is disposed between the first secondary channel layer and the first main channel layer; The second channel transition layer is disposed between the second secondary channel layer and the second main channel layer.

5. The high electron mobility transistor based on a dual-potential-well composite channel according to claim 4, characterized in that, The first channel transition layer and the second channel transition layer are symmetrically arranged along the intermediate barrier layer, and the bandgap width of the first channel transition layer and the second channel transition layer is smaller than the bandgap width of the intermediate barrier layer. The bandgap widths of the first sub-channel layer, the first channel transition layer and the first main channel layer decrease sequentially, and the bandgap widths of the second sub-channel layer, the second channel transition layer and the second main channel layer decrease sequentially.

6. The high electron mobility transistor based on a dual-potential-well composite channel according to claim 4, characterized in that, The first channel transition layer and the second channel transition layer have the same thickness, and the thickness of the first channel transition layer and the second channel transition layer is less than the thickness of the first sub-channel layer and the second sub-channel layer.

7. The high electron mobility transistor based on a dual-well composite channel according to claim 6, characterized in that, The materials of the first channel transition layer, the second channel transition layer, and the intermediate barrier layer all include undoped InPSb.

8. The high electron mobility transistor based on a dual-well composite channel according to claim 1, characterized in that, The substrate layer is made of semi-insulating InP, the buffer layer is made of undoped InAlAs, the isolation layer is made of undoped InAlAs, the delta-doping planar doped layer is made of Si, the barrier layer is made of undoped InAlAs, and the source cap layer and the drain cap layer are both made of heavily doped InGaAs.

9. The high electron mobility transistor based on a dual-well composite channel according to claim 1, characterized in that, The high electron mobility transistor also includes: A source metal interconnect is disposed on a portion of the upper surface of the source electrode; A drain metal interconnect is disposed on a portion of the upper surface of the drain electrode; A gate metal interconnect is disposed on the upper surface and part of the side surface of the gate electrode.

10. A method for fabricating a high electron mobility transistor based on a dual-potential-well composite channel, characterized in that, The fabrication method is used to fabricate a high electron mobility transistor as described in any one of claims 1 to 9, the fabrication method comprising: Select a substrate layer; A buffer layer is grown on the substrate layer; A first sub-channel layer, a first main channel layer, an intermediate barrier layer, a second main channel layer, and a second sub-channel layer are sequentially grown on the buffer layer from bottom to top to obtain a composite channel layer. An isolation layer is grown on the composite channel layer; A delta-doping planar doped layer is grown on the isolation layer; A barrier layer is grown on the delta-doping planar doped layer; Cap layer material is grown at both ends of the upper surface of the barrier layer; Metal evaporation is performed on the capping material to fabricate the source electrode and the drain electrode; The capping material is etched to form a gate groove, a source cap, and a drain cap; A gate electrode is fabricated by evaporating gate metal on a portion of the barrier layer of the gate recess. A passivation layer is formed on the upper surface of the source electrode, the source cap layer, the barrier layer, the drain cap layer, and the drain electrode.

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