All-ferroelectric transistor, manufacturing method and electronic device

Abstract

The application provides a ferroelectric transistor, a manufacturing method and an electronic device, relates to the technical field of integrated circuits, and is used for improving the domain flipping speed in the transistor and the on speed of the transistor. The ferroelectric transistor comprises a ferroelectric base, a ferroelectric bump, a source electrode, a drain electrode and a gate electrode on the ferroelectric base; wherein the source electrode and the drain electrode are located on a first side surface of the ferroelectric bump, and the gate electrode is located on a second side surface of the ferroelectric bump and opposite to the first side surface; the ferroelectric bump comprises a first interface layer with the first side surface, a second interface layer with the second side surface and a third interface layer between the first interface layer and the second interface layer, the first interface layer and the second interface layer both have a first domain which is volatile, and the third interface layer has a second domain which is non-volatile.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an all-ferroelectric transistor, its fabrication method, and an electronic device. Background Technology

[0002] A domain is a small region with the same spontaneous polarization direction (hereinafter referred to as polarization direction). A single ferroelectric material may contain multiple domains. The boundary between domains is called a domain wall (dw). A domain wall will be generated between two domains with different polarization directions, and the domain wall can conduct electricity. Figure 1 This is a schematic diagram of electric domains and domain walls in a ferroelectric material. Figure 1 Only the domain wall between two domains with polarization directions differing by 180 degrees is shown in the image. Figure 1 It includes six domains, which can be represented as D1 to D6. The polarization direction of domain D1 is upward, that of domain D2 is downward, that of domain D3 is to the left, that of domain D4 is to the right, that of domain D5 is forward, and that of domain D6 is backward. Domain walls W1, W2, and W3 are formed between domains D1 and D2, respectively. Domain walls W1, W2, and W3 can conduct electricity in insulating ferroelectric materials, and their surface currents can reach the microampere level.

[0003] In existing technologies, field-effect transistors are formed based on the ferroelectric domain walls of lithium niobate. For example... Figure 2 As shown, the field-effect transistor includes a ferroelectric substrate 10, and a source electrode 20, a drain electrode 30, a gate electrode 40, and a ferroelectric bump 50 located on the ferroelectric substrate 10. The ferroelectric bump 50 is located between the source electrode 20 and the drain electrode 30, and the gate electrode 40 is disposed on the side of the ferroelectric bump 50 away from the ferroelectric substrate 10. The conduction and shutdown of the conductive channel of the field-effect transistor are controlled by the voltage on the gate electrode 40. Specifically, in the initial state, the domains in the ferroelectric bump 50 and the domains in the ferroelectric substrate 10 have the same polarization direction, such as... Figure 3 As shown in (a), at this time, there are no domain walls in the field-effect transistor, and the field-effect transistor is in the off state; when a voltage less than the threshold voltage (the voltage that generates the conductive channel) is applied to the gate electrode 40, some of the domains of the ferroelectric bump 50 reverse direction, as shown in (a). Figure 3 As shown in (b), at this time, a conductive domain wall is established between the drain electrode 30 and the gate electrode 40, but there is no conductive domain wall between the source electrode 20 and the drain electrode 30; when the voltage on the gate electrode 40 is continuously increased, such that the voltage on the gate electrode 40 is greater than the threshold voltage, the non-reversed domains in the ferroelectric bump 50 reverse, as shown in (b). Figure 3As shown in (c), at this time, a conductive domain wall is established between the source electrode 20 and the drain electrode 30, and the field-effect transistor is in a conducting state; the voltage on the gate electrode 40 is reduced, and when the voltage on the gate electrode 40 is less than the threshold voltage, some of the domains in the ferroelectric bump 50 reverse direction, as shown in (c). Figure 3 As shown in (d), if the voltage on the gate electrode 40 is continuously decreased, the electric domains of the ferroelectric bump 50 will... Figure 3 The state shown in (a) in the figure is used to achieve the cyclic switching of the switching state of the field-effect transistor.

[0004] However, because the field-effect transistor has a top-gate structure, meaning the gate electrode is located on the side of the ferroelectric bump away from the ferroelectric substrate, and the contact between the gate electrode and the ferroelectric bump is planar, the area below the contact surface between the gate electrode and the ferroelectric bump is distributed as an equipotential body. That is, the electric field below the contact surface is almost zero. When a high voltage is applied to the gate electrode, the effective electric field applied to the domains in the ferroelectric bump is still very weak, resulting in a slow reversal speed of the domains in the ferroelectric bump. Furthermore, this results in a slow turn-on and turn-off speed for the field-effect transistor. Summary of the Invention

[0005] This application provides an all-ferroelectric transistor, a manufacturing method, and an electronic device for improving the domain switching speed and conduction speed of the transistor.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, a fully ferroelectric transistor is provided, comprising: a ferroelectric substrate, and ferroelectric bumps, a source electrode, a drain electrode, and a gate electrode located on the ferroelectric substrate; wherein the source electrode and the drain electrode are located on a first side of the ferroelectric bump, and the gate electrode is located on a second side of the ferroelectric bump opposite to the first side; the ferroelectric bump includes a first interface layer having the first side, a second interface layer having the second side, and a third interface layer located between the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer each have volatile first domains, and the third interface layer has non-volatile second domains.

[0008] In the above technical solution, the structure of the all-ferroelectric transistor is a side-gate electrode structure, that is, the gate electrode is located on the first side of the ferroelectric bump perpendicular to the ferroelectric substrate, the source electrode and the drain electrode are respectively located on the opposite side of the first side, there is no equipotential distribution in the ferroelectric substrate or ferroelectric bump, and the all-ferroelectric transistor has a non-volatile second domain, that is, the second domain can remain stable after flipping. Therefore, applying a small voltage to the gate electrode can cause the first domain to flip, thereby causing the all-ferroelectric transistor to be turned on or off. Compared with the top-gate structure transistor in the prior art, the speed of the first domain flipping is improved, and further, the speed of the transistor being turned on and off is improved.

[0009] In one possible implementation of the first aspect, the thickness of the ferroelectric bump is greater than or equal to 1 nm and less than or equal to 500 nm. In the above possible implementations, the transistor's size is reduced and integration density is improved while ensuring its normal operation.

[0010] In one possible implementation of the first aspect, a channel is provided between the source electrode and the drain electrode, the width of which is greater than or equal to 1 nm and less than or equal to 500 nm. In the above possible implementations, while ensuring the normal operation of the transistor, the size of the transistor is reduced, and the integration density is improved.

[0011] In one possible implementation of the first aspect, the sum of the width of the source electrode, the width of the drain electrode, and the width of the channel is less than or equal to the width of the gate electrode. In the above possible implementations, the transistor's size is reduced and integration density is improved while ensuring normal operation.

[0012] In one possible implementation of the first aspect, the thicknesses of the source electrode, drain electrode, gate electrode, and ferroelectric bump are the same. In the above possible implementations, the transistor's size is reduced and integration density is improved while ensuring normal operation.

[0013] In one possible implementation of the first aspect, when a first voltage is applied to the gate electrode, the direction of the first domain is the same as the direction of the second domain and opposite to the direction of the third domain, and the all-ferroelectric transistor is in a conducting state. In the above possible implementation, the direction of the first domain is the same as the direction of the second domain and opposite to the direction of the third domain, thereby creating a conductive domain wall between the first and second domains and the third domain, thus creating a conductive channel in the all-ferroelectric transistor and ensuring the normal turn-on of the transistor.

[0014] In one possible implementation of the first aspect, when the first voltage is stopped being applied to the gate electrode, the direction of the first domain is the same as the direction of the third domain and opposite to the direction of the second domain, and the all-ferroelectric transistor is in a turn-off state. In the above possible implementation, the direction of the first domain is the same as the direction of the third domain and opposite to the direction of the second domain, such that a conductive domain wall is formed between the second domain and the third domain, while no conductive domain wall is formed between the first domain and the third domain. That is, no conductive path is formed in the all-ferroelectric transistor, ensuring the normal turn-off of the transistor.

[0015] In one possible implementation of the first aspect, the ferroelectric substrate or the ferroelectric bump comprises at least one of the following materials: lithium tantalate LiTaO3, lithium niobate LiNbO3, lithium tantalate LiTaO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, lithium niobate LiNbO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, blackened lithium tantalate LiTaO3, or blackened lithium niobate LiNbO3. The above possible implementations improve selectivity.

[0016] In one possible implementation of the first aspect, the source electrode, the drain electrode, or the gate electrode comprises at least one of the following materials: tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, or tantalum silicide. The above possible implementations improve selectivity.

[0017] In a second aspect, a method for fabricating an all-ferroelectric transistor is provided. The method includes: forming a ferroelectric substrate; forming ferroelectric bumps on the ferroelectric substrate to obtain a target substrate; forming a source electrode, a drain electrode, and a gate electrode on the target substrate, wherein the source electrode and the drain electrode are located on a first side of the ferroelectric bump, and the gate electrode is located on a second side of the ferroelectric bump opposite to the first side; wherein the ferroelectric bump includes a first interface layer having the first side, a second interface layer having the second side, and a third interface layer located between the first interface layer and the second interface layer, wherein the first interface layer and the second interface layer both have volatile first domains, and the third interface layer has non-volatile second domains.

[0018] In one possible implementation of the second aspect, forming a ferroelectric bump on the ferroelectric substrate includes: depositing a masking layer at a first designated location on a first surface of the ferroelectric substrate; etching other areas of the first surface except for the first designated location; and removing the masking layer to obtain the ferroelectric bump.

[0019] In one possible implementation of the second aspect, forming a source electrode, a drain electrode, and a gate electrode on the target substrate includes: depositing a metal layer on a second surface of the target substrate, the second surface being the surface of the target substrate having the ferroelectric bump; depositing masking layers at a second, third, and fourth designated location on the metal layer, the second and third designated locations being located on a first side of the ferroelectric bump, and the fourth designated location being located on a second side of the ferroelectric bump opposite to the first side; and removing the metal layer from other areas of the second surface except at the second, third, and fourth designated locations to form the source electrode, the drain electrode, and the gate electrode.

[0020] In one possible implementation of the second aspect, the thickness of the ferroelectric bump is greater than or equal to 1 nm and less than or equal to 500 nm.

[0021] In one possible implementation of the second aspect, a channel is provided between the source electrode and the drain electrode, the width of which is greater than or equal to 1 nm and less than or equal to 500 nm.

[0022] In one possible implementation of the second aspect, the sum of the width of the source electrode, the width of the drain electrode, and the width of the channel is less than or equal to the width of the gate electrode.

[0023] In one possible implementation of the second aspect, the thickness of the source electrode, the thickness of the drain electrode, the thickness of the gate electrode, and the thickness of the ferroelectric bump are the same.

[0024] Thirdly, a chip is provided that includes a fully ferroelectric transistor, which can be the fully ferroelectric transistor provided in the first aspect or any possible implementation thereof.

[0025] Fourthly, an electronic device is provided, the electronic device including a processor and / or a memory, the processor and / or memory including a fully ferroelectric transistor, the fully ferroelectric transistor being the fully ferroelectric transistor provided in the first aspect or any possible implementation thereof.

[0026] Understandably, any of the above-described methods for manufacturing all-ferroelectric transistors, chips, and electronic devices contain the same or corresponding features as the all-ferroelectric transistors described above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding integrated circuits described above, and will not be repeated here. Attached Figure Description

[0027] Figure 1 A schematic diagram of an electric domain and domain walls;

[0028] Figure 2This is a schematic diagram of the structure of a field-effect transistor;

[0029] Figure 3 This is a schematic diagram of electric domains and domain walls in a field-effect transistor;

[0030] Figure 4 This is a schematic diagram of a planar transistor structure;

[0031] Figure 5 This is a schematic diagram of a complementary metal-oxide-semiconductor transistor.

[0032] Figure 6 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application;

[0033] Figure 7 This is a schematic diagram of the structure of an all-ferroelectric transistor provided in an embodiment of this application;

[0034] Figure 8 This is a schematic diagram of the structure of a ferroelectric bump provided in an embodiment of this application;

[0035] Figure 9 A partial schematic diagram of an all-ferroelectric crystal provided for an embodiment of this application;

[0036] Figure 10 A schematic diagram of the first and second domains of an all-ferroelectric crystal provided for an embodiment of this application;

[0037] Figure 11 A schematic flowchart illustrating a method for fabricating an all-ferroelectric transistor, provided for an embodiment of this application;

[0038] Figure 12 A cross-sectional schematic diagram of an all-ferroelectric transistor structure provided in an embodiment of this application;

[0039] Figure 13 A schematic diagram of another all-ferroelectric transistor structure provided in this application embodiment;

[0040] Figure 14 A schematic diagram of voltage and current provided for an embodiment of this application;

[0041] Figure 15 A schematic diagram of a transfer characteristic curve provided in an embodiment of this application;

[0042] Figure 16 This is a schematic diagram illustrating the change of current over time, provided as an embodiment of this application. Detailed Implementation

[0043] In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple. Furthermore, embodiments of this application use terms such as "first" and "second" to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the words “first” and “second” do not limit the quantity or the order of execution.

[0044] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] In this application embodiment, an electric domain can refer to a small region with the same spontaneous polarization direction (hereinafter referred to as polarization direction). A single ferroelectric material can include multiple electric domains. The boundary between electric domains is called a domain wall (dw). A domain wall is generated between two electric domains with different polarization directions, and this domain wall can conduct electricity. In this application embodiment, the domain wall is the domain wall generated between two electric domains with polarization directions differing by 180 degrees.

[0046] Before introducing the embodiments of this application, the structures of a planar transistor and a complementary metal-oxide-semiconductor transistor will be described first.

[0047] Figure 4 This is a schematic diagram of a planar transistor, which may include: a silicon substrate 10, and a source electrode 20, a drain electrode 30, a gate electrode 40, and a high-dielectric-constant layer located on the silicon substrate 10. Figure 4(A high-dielectric-constant layer is not shown in the diagram) and an isolation layer 50 are also shown. The high-dielectric-constant layer is located between the source electrode 20 and the drain electrode 30, and the gate electrode 40 is located on the side of the high-dielectric-constant layer away from the silicon substrate 10. The thicknesses of the source electrode 20, drain electrode 30, high-dielectric-constant layer, and isolation layer 50 are the same, as are the widths of the source electrode 20, drain electrode 30, and high-dielectric-constant layer. Specifically, the conduction and turn-off of the channel between the source electrode 20 and drain electrode 30 can be controlled according to the voltage between the gate electrode 40 and the source electrode 20, thereby realizing a simple switching function. However, as the size of the planar transistor decreases, the control capability of the gate electrode of the planar transistor over the channel weakens; in addition, many effects inside the planar transistor cause leakage current, increasing the static power consumption of the planar transistor.

[0048] Figure 5 This is a complementary metal-oxide-semiconductor transistor (FinFET). Figure 5 As shown, the FinFET includes: a silicon substrate 10, and a source electrode 20, a drain electrode 30, a gate electrode 40, and a high dielectric constant layer located on the silicon substrate 10. Figure 5 The high-dielectric-constant layer (not shown) and isolation layer 50 are located between the source electrode 20 and the drain electrode 30. The gate electrode 40 is located on the side of the high-dielectric-constant layer away from the silicon substrate 10. The high-dielectric-constant layer and isolation layer 50 have the same thickness. The source electrode 20 and drain electrode 30 have the same thickness and are both greater than the thickness of isolation layer 50. Specifically, the conduction and turn-off of the channel between the source electrode 20 and drain electrode 30 can be controlled according to the voltage between the gate electrode 40 and the source electrode 20, thereby realizing a simple switching function. However, the transistor with this structure is relatively large, and the transistor fabrication process is complex and costly.

[0049] because Figure 4 Provided planar transistors and Figure 5 The provided complementary metal-oxide-semiconductor transistor has the aforementioned defects; therefore, an all-ferroelectric transistor cannot be implemented using a similar structure.

[0050] Based on this, embodiments of this application provide a fully ferroelectric transistor, a manufacturing method, and an electronic device. This fully ferroelectric transistor can serve as a basic unit of integrated circuits and can be applied in electronic devices. For example, it can be used in processors and / or memory within electronic devices. The electronic device may include: a server, a memory, or a terminal device. The terminal device may include, but is not limited to, personal computers, server computers, mobile devices (such as mobile phones, tablets, media players, etc.), wearable devices, in-vehicle devices, consumer terminal devices, mobile robots, and drones.

[0051] The structure of the terminal device will be described below, taking the electronic device, including the terminal device, as an example.

[0052] Figure 6 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application, using a mobile phone as an example for illustration. Figure 6 As shown, the terminal device may include: a memory 101, a processor 102, a sensor assembly 103, a multimedia assembly 104, a power supply 105, and an input / output interface 106.

[0053] The memory 101 can be used to store data, software programs, and software modules; it mainly includes a program storage area and a data storage area. The program storage area can store the operating system and application programs required for at least one function, such as sound playback or image playback. The data storage area can store data created according to the use of the terminal device, such as audio data, image data, or spreadsheet data. In addition, the terminal device may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0054] The processor 102 is the control center of the terminal device. It connects various parts of the device via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or software modules stored in the memory 101, and by calling data stored in the memory 101, thereby providing overall monitoring of the terminal device. Optionally, the processor 102 may include one or more processing units. For example, the processor 102 may include a central processing unit (CPU), an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0055] Sensor assembly 103 includes one or more sensors for providing various aspects of the terminal device's status assessment. Sensor assembly 103 may include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor assembly 103 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the terminal device. Furthermore, sensor assembly 103 may also include a light sensor for detecting ambient light.

[0056] Multimedia component 104 provides a screen that serves as an output interface between the terminal device and the user. This screen can be a touch panel, and when it is a touch panel, it can be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. Furthermore, multimedia component 104 includes at least one camera, for example, a front-facing camera and / or a rear-facing camera. When the terminal device is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera can receive external multimedia data. Each front-facing and rear-facing camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0057] Power supply 105 is used to provide power to the various components of the terminal device. Power supply 105 may include a power management system, one or more power supplies, or other components associated with the generation, management and distribution of power by the terminal device.

[0058] Input / output interface 106 provides an interface between processor 102 and peripheral interface modules, such as keyboards, mice, or universal serial bus (USB) devices.

[0059] Although not shown, the terminal device may also include audio components and communication components, such as a microphone for the audio component and a wireless fidelity (WiFi) module or a Bluetooth module for the communication component. These will not be elaborated further in the embodiments of this application. Those skilled in the art will understand that... Figure 6 The terminal device structure shown does not constitute a limitation on the terminal device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0060] In the embodiments of this application, the above Figure 6The memory 101 and processor 102 in the terminal device shown may each include the all-ferroelectric transistors provided in the embodiments of this application.

[0061] Figure 7 This is a schematic diagram of a fully ferroelectric transistor provided in an embodiment of this application. The fully ferroelectric transistor includes: a ferroelectric substrate 201, and ferroelectric bumps 202, a source electrode 203, a drain electrode 204, and a gate electrode 205 located on the ferroelectric substrate 201. The source electrode 203 and the drain electrode 204 are located on a first side of the ferroelectric bump 202, and the gate electrode 205 is located on a second side of the ferroelectric bump 202 opposite to the first side. The ferroelectric bump 202 includes a first interface layer 01 having the first side, a second interface layer 02 having the second side, and a third interface layer 03 located between the first interface layer 01 and the second interface layer 02. The first interface layer 01 and the second interface layer 02 both have volatile first domains, and the third interface layer 03 has non-volatile second domains. Figure 7 The second side is not shown in the image.

[0062] The first side surface can be any one of the surfaces of the ferroelectric bump 202 that is perpendicular to the ferroelectric substrate 201. For example, Figure 8 This is a schematic diagram of the structure of a ferroelectric bump provided in an embodiment of this application. The first side can be a first vertical surface, and the second side can be a surface of the ferroelectric bump 202 that is opposite to the first vertical surface. For example, the second side can be a second vertical surface that is opposite to the first vertical surface. Figure 8 Only the first vertical plane is shown in the image.

[0063] Figure 9 This is a partial schematic diagram of a fully ferroelectric crystal provided in an embodiment of this application. Figure 9 (a) in the middle is Figure 7 The top view of the fully ferroelectric transistor shown is along the opposite direction of the Z-axis. Figure 9 (b) in the middle is Figure 7 The left view of the all-ferroelectric transistor shown below, along the X-axis, is combined with... Figure 7 and Figure 9 The structure of the all-ferroelectric transistor provided in the embodiments of this application will be described and explained. Figure 9 The source electrode 203 is designated as (source, S), the drain electrode 204 as (drain, D), and the gate electrode 205 as (gate, G).

[0064] Furthermore, during the etching process of the ferroelectric bump 202, ions in the first and second sides of the ferroelectric bump 202 are lost, and the metal material of the electrode diffuses locally into the ferroelectric bump through the first and second sides, thereby forming a first interface layer 01 and a second interface layer 02 on the ferroelectric bump 202. The lengths of both the first interface layer 01 and the second interface layer 02 can be 3-7 nm.

[0065] Secondly, the domains in the first interface layer 01 and the second interface layer 02 are both first domains, which can also be called interface domains. The domains in the third interface layer 03 are second domains, which can also be called bulk domains. Both the first and second domains have a spontaneous polarization direction (hereinafter referred to as direction).

[0066] Furthermore, the first domain is volatile, while the second domain is non-volatile. For example, when no voltage is applied to the gate electrode 205, the directions of the first domain and the second domain are the same and both are in the first direction; after a voltage is applied to the gate electrode 205, both the first domain and the second domain undergo a 180-degree flip, the directions of the first domain and the second domain are the same and both are in the second direction, and the first direction and the second direction differ by 180 degrees; after the voltage is stopped applied to the gate electrode 205, the first domain flips, the second domain does not flip, the direction of the first domain remains in the first direction, and the direction of the second domain remains in the second direction.

[0067] Furthermore, the thickness of the ferroelectric bump 202 can be greater than or equal to 1 nm and less than or equal to 500 nm.

[0068] Furthermore, such as Figure 9 As shown in (a), a channel is provided between the source electrode 203 and the drain electrode 204. The width of the channel can be greater than or equal to 1 nm and less than or equal to 500 nm. Furthermore, the sum of the width of the source electrode 203, the width of the drain electrode 204, and the width of the channel is less than or equal to the width of the gate electrode 205. Figure 9 Example (a) is that the sum of the width of the source electrode 203, the width of the drain electrode 204, and the width of the channel is equal to the width of the gate electrode 205.

[0069] Furthermore, the source electrode 203, the drain electrode 204, the gate electrode 205, and the ferroelectric bump 202 have the same thickness. Thus, the surfaces of the source electrode 203, the drain electrode 204, the gate electrode 205, and the ferroelectric bump 202 that are away from the ferroelectric substrate 201 are flush with each other. Figure 9 As shown in (b) of the diagram.

[0070] Optionally, the ferroelectric substrate 201 has a third domain, which is a non-flipping domain, that is, the direction of the third domain always remains unchanged, and the direction is the initial polarization direction of the third domain.

[0071] In one possible embodiment, in the initial state, i.e., when no voltage is applied to the source electrode 203, the drain electrode 204, and the gate electrode 205, the directions of the first domain, the second domain, and the third domain are the same, and can be any one of the directions. For example, as Figure 9 As shown in (b) above, the direction can be along the X-axis, or it can be any direction that forms a certain angle with the X-axis. This application does not specifically limit this. For ease of understanding, in the initial state, the direction of the first domain, the direction of the second domain, and the direction of the third domain are taken as being along the X-axis.

[0072] Optionally, when the directions of the first domain, the second domain, and the third domain are different, the conductive domain walls generated in the all-ferroelectric transistor are also different. This will be explained in detail below.

[0073] In a first possible embodiment, the directions of the first domain, the second domain, and the third domain are the same, and no conductive domain walls are generated between the first domain, the second domain, and the third domain.

[0074] In a second possible embodiment, when the direction of the first domain is the same as the direction of the second domain and opposite to the direction of the third domain, conductive domain walls are generated between the first domain and the second domain and the third domain, that is, conductive domain walls are generated between the first domain and the third domain, and between the second domain and the third domain.

[0075] In a third possible embodiment, when the direction of the first domain is opposite to that of the second domain and the direction of the third domain is the same, no conductive domain wall is generated between the first domain and the third domain, but a conductive domain wall is generated between the second domain and the third domain.

[0076] In a fourth possible embodiment, when the direction of the second domain is opposite to that of the first domain and the same as that of the third domain, a conductive domain wall is formed between the first domain and the third domain, but no conductive domain wall is formed between the second domain and the third domain.

[0077] In this embodiment, the generation of the conductive channel in the all-ferroelectric transistor is caused by the formation of conductive domain walls (hereinafter referred to as conductive domain walls) between the first and second domains that can flip and the third domain that cannot flip. The conduction and shutdown of the channel are controlled by applying a gate voltage to the gate electrode 205. The following is in conjunction with... Figure 10 The process of turning on and off this all-ferroelectric transistor is explained.

[0078] In the initial state, the directions of the first domain, the second domain, and the third domain are the same. No conductive domain walls are generated between the first domain, the second domain, and the third domain. No conductive channels are generated in the all-ferroelectric transistor, and the all-ferroelectric transistor is in the off state.

[0079] A: During the initialization process, a first voltage greater than its coercive voltage (a voltage that causes both the first and second domains to flip by 180 degrees) is applied to the gate electrode 205. The first and second domains then flip, as shown below. Figure 10 As shown in (a), conductive domain walls are generated between the first domain and the second domain and the third domain, as... Figure 10 As shown in (b), a conductive channel is generated in the all-ferroelectric transistor, and the all-ferroelectric transistor is in the on state.

[0080] B: During the turn-off process, when the first voltage is stopped being applied to the gate electrode 205, the first domain flips, while the second domain does not flip. Figure 10 As shown in (c), the direction of the first domain is the same as the direction of the third domain and opposite to the direction of the second domain. No conductive domain wall is formed between the first domain and the third domain, but a conductive domain wall is formed between the second domain and the third domain. Figure 10 As shown in (d) in the figure, a conductive channel is generated in the all-ferroelectric transistor, and the all-ferroelectric transistor is in the off state.

[0081] When the first voltage is stopped being applied to the gate electrode 205, since the second and third domains are stable domains with directions 180 degrees apart, the second domain does not flip. However, after the voltage is applied, an internal bias field exists in the metal electrode, which causes the first domain to flip, thereby making the direction of the first domain the same as that of the third domain.

[0082] C: During the conduction process, a second voltage is applied to the gate electrode 205, causing the first domain to flip, such as... Figure 10 As shown in (e), the direction of the first domain is the same as that of the second domain and opposite to that of the third domain. Conductive domain walls are generated between the first domain and the third domain, as shown in Figure (e). Figure 10As shown in (f), a conductive channel is generated in the all-ferroelectric transistor, and the all-ferroelectric transistor is in the on state.

[0083] Wherein, the second voltage is less than the first voltage, and the second voltage is the voltage that causes the first domain to flip.

[0084] In addition, the ferroelectric substrate 201 or the ferroelectric bump 202 includes at least one of the following materials: lithium tantalate LiTaO3, lithium niobate LiNbO3, lithium tantalate LiTaO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, lithium niobate LiNbO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, blackened lithium tantalate LiTaO3, and blackened lithium niobate LiNbO3.

[0085] In addition, the source electrode 203, the drain electrode 204, or the gate electrode 205 comprises at least one of the following materials: tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0086] The all-ferroelectric transistor provided in this application has a side-gate electrode structure, that is, the gate electrode is located on a first side of the ferroelectric bump perpendicular to the ferroelectric substrate, and the source electrode and the drain electrode are respectively located on the opposite side of the first side. There is no equipotential distribution in the ferroelectric substrate or ferroelectric bump, and the all-ferroelectric transistor has a non-volatile second domain. Therefore, applying a small voltage to the gate electrode can cause the first domain to flip, thereby turning the all-ferroelectric transistor on or off. Compared with the field-effect transistor with a top-gate electrode structure in the prior art, the speed of the first domain flipping is improved, and further, the speed of the all-ferroelectric transistor turning on and off is improved.

[0087] The following is combined with Figure 11 and Figure 12 The fabrication method of the all-ferroelectric transistor provided in the embodiments of this application will be described and explained.

[0088] Figure 11 This is a flowchart illustrating a method for fabricating a fully ferroelectric transistor according to an embodiment of this application. The fully ferroelectric transistor can be the one described above, and the method may include the following steps. Figure 12 A cross-sectional schematic diagram of the all-ferroelectric transistor structure during the fabrication process.

[0089] S101: Forming the ferroelectric substrate 201. The cross-sectional structure of this all-ferroelectric transistor is as follows. Figure 12 (a) in the middle.

[0090] Following step S101, the method further includes: forming a photoresist layer on the first surface of the ferroelectric substrate. For example, a photoresist layer can be coated on the first surface of the ferroelectric substrate, and the cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 As shown in (b); a first pattern is determined on the surface of the photoresist layer away from the ferroelectric substrate using a photolithography machine. For example, the first pattern can be written on the surface of the photoresist layer away from the ferroelectric substrate using a photolithography machine. The position of the first pattern is the first designated position in step S102. The cross-sectional structure of the all-ferroelectric transistor is as follows. Figure 12 (c) The first pattern is developed using a developing technique to obtain a first substrate, which includes a photoresist layer a and a photoresist layer b. The cross-sectional structure of the all-ferroelectric transistor is shown in Figure 1. Figure 12 (d) in the middle.

[0091] S102: Ferroelectric bumps 202 are formed on the ferroelectric substrate 201 to obtain the target substrate.

[0092] In step S102, forming a ferroelectric bump on the ferroelectric substrate includes: depositing a masking layer at a first designated location on the first surface of the ferroelectric substrate 201; etching other areas of the first surface except for the first designated location; and removing the masking layer to obtain the ferroelectric bump 202.

[0093] Specifically, a masking layer is deposited at a first designated location on the first surface of the ferroelectric substrate 201, and on the surfaces of photoresist layers a and b in the first substrate that are away from the ferroelectric substrate. The cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (e) In the figure; by removing photoresist layers a and b, as well as the masking layers on photoresist layers a and b, through a lift-off process, the cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (f) In the first part, the area of ​​the first surface other than the first designated location is etched using a reactive ion etching machine to form a ferroelectric bump 202 with a masking layer. The cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (g) In the process of removing the masking layer on the ferroelectric bump 202 by removing the metal solution, the ferroelectric bump 202 is obtained, and the cross-sectional structure of the all-ferroelectric transistor is as follows. Figure 12 (h) in the middle.

[0094] S103: A source electrode 203, a drain electrode 204, and a gate electrode 205 are formed on the target substrate. The source electrode 203 and the drain electrode 204 are located on a first side of the ferroelectric bump 202, and the gate electrode 205 is located on a second side of the ferroelectric bump 202 opposite to the first side. The ferroelectric bump 202 includes a first interface layer having the first side, a second interface layer having the second side, and a third interface layer located between the first interface layer and the second interface layer. Both the first interface layer and the second interface layer have volatile first domains, and the third interface layer has non-volatile second domains.

[0095] The formation of a source electrode 203, a drain electrode 204, and a gate electrode 205 on the target substrate includes: depositing a metal layer on a second surface of the target substrate, wherein the second surface is the surface of the target substrate having the ferroelectric bump 202, and the cross-sectional structure of the all-ferroelectric transistor is as follows. Figure 12 (i) in; in Figure 12 A photoresist layer is formed on the metal layer shown in (i), and the cross-sectional structure of the all-ferroelectric transistor is as follows. Figure 12 (j) in; using a photolithography machine in Figure 12 The second, third, and fourth patterns are defined on the surface of the photoresist layer away from the target substrate, as shown in (j). The positions of the second, third, and fourth patterns are respectively the second, third, and fourth designated positions below. The cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (k) The second pattern, third image, and fourth pattern are developed using a developing technique to obtain a second substrate, which includes photoresist layer c, photoresist layer d, and photoresist layer e. The cross-sectional structure of this all-ferroelectric transistor is shown below. Figure 12 In (l); masking layers are deposited at the second, third, and fourth designated positions of the metal layer, and on the surfaces of the photoresist layers c, d, and e away from the target substrate, respectively. The second and third designated positions are located on the first side of the ferroelectric bump, and the fourth designated position is located on the second side of the ferroelectric bump opposite to the first side. The cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (m); The photoresist layer and the masking layer on the photoresist layer are removed from the target substrate by a lift-off process, that is, photoresist layer c, photoresist layer d, and photoresist layer e, as well as the masking layer on photoresist layer c, photoresist layer d, and photoresist layer e, are removed by a lift-off process. The cross-sectional structure of the all-ferroelectric transistor is as follows. Figure 12(n); The metal layer on the second surface, excluding the second, third, and fourth designated locations, is etched using a reactive ion etching machine to form a source electrode 203, a drain electrode 204, and a gate electrode 205 with a masking layer. The cross-sectional structure of the all-ferroelectric transistor is as follows: Figure 12 (p); Remove the masking layer on the source electrode 203, drain electrode 204, and gate electrode 205 to obtain the source electrode 203, drain electrode 204, and gate electrode 205. The cross-sectional structure of this all-ferroelectric transistor is as follows. Figure 12 In the process (q), the target substrate can be tilted at a certain angle to etch the metal layer. During the etching process, the metal layer can slide off smoothly and is less prone to accumulation. The cross-sectional structure of this all-ferroelectric transistor is as follows: Figure 12 (o) in the middle. Figure 12 The drain electrode 204 is not shown in the figure, and the thickness of the source electrode 203, the drain electrode 204, and the gate electrode 205 are all less than the thickness of the ferroelectric bump 202, as an example.

[0096] It should be noted that if the target substrate is not tilted during the etching process of the metal layer, the residual metal generated during the etching process will accumulate between the electrodes, resulting in leakage.

[0097] During the etching process of the ferroelectric bump 202, ions in the first and second sides of the ferroelectric bump 202 are lost, and the metal material of the electrode diffuses locally into the ferroelectric bump 202 through the first and second sides, thereby forming a first interface layer and a second interface layer on the ferroelectric bump 202. The length of both the first and second interface layers can be 3-7 nm.

[0098] The domains in the first and second interface layers are both first domains, which can also be referred to as interface domains. The domains in the third interface layer located between the first and second interface layers are second domains, which can also be referred to as bulk domains. Both the first and second domains have a spontaneous polarization direction (hereinafter referred to as direction).

[0099] Furthermore, the first domain is volatile, while the second domain is non-volatile. For example, when no voltage is applied, the directions of the first and second domains are the same and both are in the first direction. After voltage is applied, both the first and second domains flip by 180 degrees. The directions of the first and second domains are the same and both are in the second direction, with a 180-degree difference between the first and second directions. After the voltage is stopped, the first domain flips, but the second domain does not flip. The direction of the first domain remains the first direction, and the direction of the second domain remains the second direction.

[0100] Furthermore, the thickness of the ferroelectric bump 202 can be greater than or equal to 1 nm and less than or equal to 500 nm.

[0101] Furthermore, a channel is provided between the source electrode and the drain electrode, and the width of the channel can be greater than or equal to 1 nm and less than or equal to 500 nm. The sum of the width of the source electrode 203, the width of the drain electrode 204, and the width of the channel is less than or equal to the width of the gate electrode.

[0102] Furthermore, the source electrode 203, the drain electrode 204, the gate electrode 205, and the ferroelectric bump 202 have the same thickness. That is, the surfaces of the source electrode, the drain electrode, the gate electrode, and the ferroelectric bump 202 that are away from the ferroelectric substrate 201 are flush with each other.

[0103] Figure 13 This is a schematic diagram of an all-ferroelectric transistor under a scanning electron microscope (SEM) provided for an embodiment of this application.

[0104] Figure 14 This is a schematic diagram of voltage and current in an all-ferroelectric transistor provided in an embodiment of this application. Figure 14 Taking the coercivity voltage of the all-ferroelectric transistor as 6.5V and the source electrode and drain electrode as grounded simultaneously as an example. Figure 14 In the figure (a), the variation trend of the source electrode current Is and voltage Vg in the all-ferroelectric transistor is shown. Figure 14 (b) shows the trend of the drain current Id versus voltage Vg in an all-ferroelectric transistor. Figure 14 (c) shows the variation trend of the gate electrode current Ig and voltage Vg in the all-ferroelectric transistor. Figure 14 In the figure, (d) represents the trend of the current I and voltage Vg in the channel of the all-ferroelectric transistor. Figure 14 As shown in (a), curve S1 indicates that when the gate voltage Vg reaches approximately 6.5V, the current Is increases from 0 to approximately -650nA. When the gate voltage Vg is removed, the current Is gradually decreases from -650nA to 0. Curve S2 indicates that when a turn-on voltage Von of approximately 2.2V is applied to the gate electrode, the current Is increases from 0 to approximately -650nA. When the turn-on voltage Von is removed, the current Is gradually decreases from -650nA to 0. Figure 14As shown in (b), curve S3 indicates that when the gate voltage Vg reaches approximately 6.5V, the current Id increases from 0 to approximately -650nA. When the gate voltage Vg is removed, the current Id gradually decreases from -650nA to 0. Curve S4 indicates that when a turn-on voltage Von of approximately 2.2V is applied to the gate electrode, the current Id increases from 0 to approximately -650nA. When the turn-on voltage Von is removed, the current Id gradually decreases from -650nA to 0. Figure 14 As shown in (c), curve S5 indicates that when the gate voltage Vg reaches approximately 6.5V, the current Ig increases from 0 to about 1000nA. When the gate voltage Vg is removed, the current Ig gradually decreases from 1000nA to 0. Curve S6 indicates that when a turn-on voltage of approximately 2.2V is applied to the gate electrode, the current Igd increases from 0 to about 1000nA. When the turn-on voltage Von is removed, the current Ig gradually decreases from 1000nA to 0. Figure 14 As shown in (d), curve S7 indicates that when the gate voltage Vg reaches approximately 6.5V, the current I increases from 0 to about 1000nA. When the gate voltage Vg is removed, the current I gradually decreases from 1000nA to 0. Curve S8 shows that when a turn-on voltage of approximately 2.2V is applied to the gate electrode, the current I increases from 0 to about 1000nA. When the turn-on voltage Von is removed, the current I gradually decreases from 1000nA to 0. Figure 14 It can be seen that when a voltage greater than the coercive voltage is applied to the gate electrode, the all-ferroelectric transistor turns on. When the coercive voltage is removed, the all-ferroelectric transistor turns off. When a small voltage greater than the turn-on voltage is applied to the gate electrode again, the transistor turns on again. At this time, the voltage is much smaller than the coercive voltage.

[0105] Figure 15 This is a schematic diagram of the transfer characteristic curve of an all-ferroelectric transistor provided in an embodiment of this application. Figure 15 As shown, curve S1 represents the trend of the current Isd between the source and drain electrodes of the all-ferroelectric transistor when a voltage of -2.7V is applied to the gate electrode; curve S2 represents the trend of the current Isd between the source and drain electrodes of the all-ferroelectric transistor when a voltage of -1.6V is applied to the gate electrode; and curve S3 represents the trend of the current Isd between the source and drain electrodes of the all-ferroelectric transistor when a voltage of -0.4V is applied to the gate electrode. Figure 15 As can be seen from curves S1, S2 and S3, after applying different voltages to the gate electrode, the current Isd between the source electrode and the drain electrode of the all-ferroelectric transistor can easily stabilize when the target current is reached, that is, the oscillation amplitude of the current Isd is small and can be ignored.

[0106] Figure 16 This is a schematic diagram illustrating the change of current over time, provided as an embodiment of this application. Figure 16Taking a fully ferroelectric transistor with a coercivity voltage of 3.5V and a source terminal current Is as an example. Figure 16 As shown, the conduction time of the all-ferroelectric transistor varies when different voltages are applied to the gate electrode. Curve S1 represents the trend of the current Is at the source terminal of the all-ferroelectric transistor when a voltage of 4.5V is applied to the gate electrode, at which point the conduction time is 2ns; curve S2 represents the trend of the current Is at the source terminal of the all-ferroelectric transistor when a voltage of 4V is applied to the gate electrode, at which point the conduction time is 50ns; and curve S3 represents the trend of the current Is at the source terminal of the all-ferroelectric transistor when a voltage of 3.5V is applied to the gate electrode, at which point the conduction time is 1000ns. Figure 16 It can be seen that the conduction speed of the all-ferroelectric transistor is proportional to the voltage applied to the gate electrode; that is, the greater the voltage applied to the gate electrode, the shorter the conduction time of the transistor.

[0107] In another aspect of this application, a chip is also provided, which may include a fully ferroelectric transistor, the fully ferroelectric transistor being... Figure 7 , Figure 9 or Figure 13 The all-ferroelectric transistor shown.

[0108] In another aspect of this application, an electronic device is also provided, comprising a processor and / or a memory, wherein the processor and / or the memory comprises a fully ferroelectric transistor, which can be used for... Figure 7 , Figure 9 and Figure 13 The all-ferroelectric transistor shown.

[0109] It should be noted that the above descriptions of the all-ferroelectric transistor can be applied to the chips and electronic devices provided in this application. For further details, please refer to the corresponding descriptions above. The embodiments of this application will not be repeated here.

[0110] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A fully ferroelectric transistor, characterized in that, include: A ferroelectric substrate, and ferroelectric bumps, a source electrode, a drain electrode, and a gate electrode located on the ferroelectric substrate; The source electrode and the drain electrode are located on the first side of the ferroelectric bump, and the gate electrode is located on the second side of the ferroelectric bump opposite to the first side. The ferroelectric bump includes a first interface layer having the first side, a second interface layer having the second side, and a third interface layer located between the first interface layer and the second interface layer. The first interface layer and the second interface layer both have volatile first domains, and the third interface layer has non-volatile second domains.

2. The all-ferroelectric transistor according to claim 1, characterized in that, The thickness of the ferroelectric bump is greater than or equal to 1 nm and less than or equal to 500 nm.

3. The all-ferroelectric transistor according to claim 1, characterized in that, A channel is provided between the source electrode and the drain electrode, and the width of the channel is greater than or equal to 1 nm and less than or equal to 500 nm.

4. The all-ferroelectric transistor according to claim 3, characterized in that, The sum of the width of the source electrode, the width of the drain electrode, and the width of the channel is less than or equal to the width of the gate electrode.

5. The all-ferroelectric transistor according to claim 1, characterized in that, The thicknesses of the source electrode, the drain electrode, the gate electrode, and the ferroelectric bump are the same.

6. The all-ferroelectric transistor according to any one of claims 1-5, characterized in that, The ferroelectric substrate has a third electric domain. In the initial state, the directions of the first domain, the second domain, and the third domain are the same.

7. The all-ferroelectric transistor according to claim 6, characterized in that, When a first voltage is applied to the gate electrode, the direction of the first domain is the same as the direction of the second domain and opposite to the direction of the third domain, and the all-ferroelectric transistor is in the on state.

8. The all-ferroelectric transistor according to claim 7, characterized in that, When the first voltage is stopped being applied to the gate electrode, the direction of the first domain is the same as the direction of the third domain and opposite to the direction of the second domain, and the all-ferroelectric transistor is in the off state.

9. The all-ferroelectric transistor according to any one of claims 1-5, characterized in that, The ferroelectric substrate or the ferroelectric bump comprises at least one of the following materials: Lithium tantalate LiTaO3, lithium niobate LiNbO3, lithium tantalate LiTaO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, lithium niobate LiNbO3 doped with MgO, Mn2O5, Fe2O3 or La2O3, blackened lithium tantalate LiTaO3, blackened lithium niobate LiNbO3.

10. The all-ferroelectric transistor according to any one of claims 1-5, characterized in that, The source electrode, the drain electrode, or the gate electrode comprises at least one of the following materials: Tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide.

11. A method for fabricating a fully ferroelectric transistor, characterized in that, The method includes: Forming a ferroelectric substrate; Ferroelectric bumps are formed on the ferroelectric substrate to obtain the target substrate; A source electrode, a drain electrode, and a gate electrode are formed on the target substrate. The source electrode and the drain electrode are located on a first side of the ferroelectric bump, and the gate electrode is located on a second side of the ferroelectric bump opposite to the first side. The ferroelectric bump includes a first interface layer having the first side, a second interface layer having the second side, and a third interface layer located between the first interface layer and the second interface layer. The first interface layer and the second interface layer both have volatile first electric domains, and the third interface layer has non-volatile second electric domains.

12. The method according to claim 11, characterized in that, The process of forming ferroelectric bumps on the ferroelectric substrate includes: A masking layer is deposited at a first designated location on the first surface of the ferroelectric substrate; Etch other areas of the first surface except for the first designated location; Remove the masking layer to obtain the ferroelectric bump.

13. The method according to claim 11, characterized in that, The process of forming a source electrode, a drain electrode, and a gate electrode on the target substrate includes: A metal layer is deposited on a second surface of the target substrate, wherein the second surface is the surface of the target substrate having the ferroelectric bumps; A masking layer is deposited at a second, third, and fourth designated position on the metal layer, respectively. The second and third designated positions are located on a first side of the ferroelectric bump, and the fourth designated position is located on a second side of the ferroelectric bump opposite to the first side. Remove the metal layer from the second surface in areas other than the second specified location, the third specified location, and the fourth specified location to form the source electrode, drain electrode, and gate electrode.

14. The method according to claim 11, characterized in that, The thickness of the ferroelectric bump is greater than or equal to 1 nm and less than or equal to 500 nm.

15. The method according to claim 11, characterized in that, A channel is provided between the source electrode and the drain electrode, and the width of the channel is greater than or equal to 1 nm and less than or equal to 500 nm.

16. The method according to claim 15, characterized in that, The sum of the width of the source electrode, the width of the drain electrode, and the width of the channel is less than the width of the gate electrode.

17. The method according to any one of claims 11-16, characterized in that, The thicknesses of the source electrode, the drain electrode, the gate electrode, and the ferroelectric bump are the same.

18. A chip, characterized in that, The chip includes a fully ferroelectric transistor, as described in any one of claims 1-10.

19. An electronic device, characterized in that, The electronic device includes a processor and / or a memory, wherein the processor and / or the memory includes a fully ferroelectric transistor as described in any one of claims 1-10.

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