A compatible bi-cmos process programmable pinch off voltage pjfet transistor

Abstract

The application provides a compatible BiCMOS process adjustable pinch-off voltage PJFET transistor which can be widely applied to various high, medium and low pinch-off voltage application scenarios. The application comprises a buried layer, an epitaxial layer, a base region, a source region and a drain region arranged on a P-type substrate, and is characterized in that: an N-type buried layer is formed on the P-type substrate, and a P-type epitaxial layer is formed above the N-type buried layer; a circular P+ drain region is formed by base region injection on the P-type epitaxial layer; a circular ring-shaped N-type gate is formed based on N-type ESD injection on the outer periphery of the drain region; a circular ring-shaped P+ source region is formed based on base region injection on the outer periphery of the N-type gate; a circular ring-shaped isolation N well is arranged outside the source region, the isolation N well is electrically connected to the transistor BN buried layer; the channel body region of the transistor and other P epitaxial regions are isolated based on the ring-shaped isolation N well and the bottom BN buried layer; the N-type buried layer BN is used as an N-type back gate of the transistor, and the N-type back gate and the N-type gate interact to jointly pinch off the channel body region of the transistor.

Description

Technical Field

[0001] This invention relates to the field of field-effect transistor manufacturing technology, specifically to a PJFET transistor with adjustable pinch-off voltage compatible with BiCMOS process. Background Technology

[0002] Junction field-effect transistors (JFETs) were introduced in the 1980s as a replacement for less reliable MOS devices. JFETs are often used as the input stage of operational amplifiers to achieve input leakage currents several orders of magnitude smaller than bipolar circuits. JFETs are frequently used as analog switches and current sources.

[0003] Standard bipolar processes involve the hierarchical steps required to fabricate a simple JFET structure. However, with advancements in chip manufacturing processes, early bipolar processes have become insufficient to meet the demands of chip development. Modern BiCMOS processes, which integrate transistors from both CMOS and standard bipolar technologies, are currently the most advanced and mainstream manufacturing process.

[0004] PJFET transistors manufactured using modern BiCMOS processes use a single N-type injection to form the N-type gate. This N-type gate has a relatively shallow junction depth, resulting in weaker control over the P-EPI channel. The relatively shallow N-type gate leads to a relatively larger P-EPI thickness in the channel body region, thus increasing the voltage required to pinch off the P-EPI channel through the depletion region. In some low-to-medium voltage applications, the device may fail to pinch off under normal operating conditions. In such cases, the PJFET transistor functions more like a nonlinear buried P-epitaxial resistor than a true PJFET device. Summary of the Invention

[0005] To address the issue of existing PJFET transistors failing to pinch off when applied to low- and medium-voltage circuits, this invention provides a BiCMOS-compatible adjustable pinch-off voltage PJFET transistor, which can be widely applied to various high, medium, and low pinch-off voltage applications.

[0006] The technical solution of this invention is as follows: a BiCMOS-compatible adjustable pinch-off voltage PJFET transistor, comprising: a buried layer, an epitaxial layer, a base region, a source region, and a drain region disposed on a P-type substrate, characterized in that: An N-type buried layer is formed on a P-type substrate, and a P-type epitaxial layer is formed above the N-type buried layer. On the P-type epitaxial layer, a circular P+ drain region is formed by base region implantation; an annular N-type gate is formed around the drain region by N-type ESD implantation; an annular P+ source region is formed around the N-type gate by base region implantation; an annular isolation N-well is disposed outside the source region, and the isolation N-well is electrically connected to the BN buried layer of the transistor. The channel body region of the transistor is isolated from other P-epitaxial regions by using a ring-shaped isolation N-well and a bottom BN buried layer. The N-type buried layer BN is used as the N-type back gate of the transistor, and the N-type back gate interacts with the N-type gate to jointly clamp the channel body region of the transistor.

[0007] Its further features are: The N-type back gate BN achieves potential connection with the N-type gate by isolating the N+ in the N-well ring; The thickness of the P-EPI epitaxial layer in the channel body region of the transistor is controlled to be 8 micrometers; The distance between the drain region and the N-type gate, as well as the distance between the source region and the N-type gate, is greater than 5 micrometers; The spacing between the source region and the isolation N-well ring is greater than 4 micrometers; The transistor has a closed ring structure; the structure of the transistor is symmetrical about the horizontal axis passing through the center of the ring, and also symmetrical about the vertical axis passing through the center of the ring. The method for adjusting the pinch-off voltage in the pinch-off body region is as follows: When the N-type gate, N-type back gate, and source region are connected and all connected to the highest potential VCC, the pinch-off voltage is at its maximum, denoted as: maximum pinch-off voltage; When the N-type gate and N-type back gate are connected, but not connected to the source region, and the N-type gate and N-type back gate are connected to the highest potential VCC, and the voltage difference between the potential of the N-type gate and N-type back gate and the potential of the source region is the largest, the pinch-off voltage is the smallest: denoted as the minimum pinch-off voltage. When the N-type gate and the N-type back gate are connected, but they are not connected to the source region, and the potential of the N-type gate and the N-type back gate is higher than the potential of the source region and the drain region but lower than the highest potential VCC of the circuit, the pinch-off voltage is located between the maximum pinch-off voltage and the minimum pinch-off voltage, which is called the medium pinch-off voltage. The voltage difference between the drain region and the source region is the medium pinch-off voltage value.

[0008] This application provides a BiCMOS-compatible adjustable pinch-off voltage PJFET transistor. It utilizes base region implantation to form the source and drain regions, ensuring the transistor can withstand high-voltage application environments. An N-type gate is formed using N-type ESD implantation. Due to the relatively deep junction of N-type ESD implantation, an effectively pinch-off PJFET transistor can be formed, ensuring the transistor can operate under medium voltage conditions. An N-well ring isolates the channel body region of the PJFET transistor from other P-epitaxial layers, and an N-type buried layer (BN) isolates the channel body region of the PJFET transistor from the PSUB. The N-type buried layer (BN) serves as the N-type back gate of the PJFET transistor, interacting with the N-type gate formed by N-type ESD implantation to jointly pinch off the channel body region of the PJFET transistor. This application achieves pinch-off voltage adjustment through different connections of the N-type gate and N-type back gate, ensuring its wide applicability to various high, medium, and low pinch-off voltage applications. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the transistor structure of this application; Figure 2 A schematic diagram showing the connection relationship for transistors to achieve their maximum pinch-off voltage; Figure 3 A schematic diagram of the connection relationship for transistors with a moderate pinch-off voltage; Figure 4 A schematic diagram showing the connection relationship for transistors to achieve minimum pinch-off voltage; Figure 5 Here is a layout example of the transistor in this application; Figure 6 This is a schematic diagram showing the resistance relationship of the channel body region in a transistor. Figure 7 This is a schematic diagram of the low-voltage pinch-off process in the channel body region of a transistor. Figure 8 This is an application embodiment of the transistor in this application; Figure 9 This is a table showing the test results of the PCM parameters of the transistors in this application. Detailed Implementation

[0010] like Figures 1-7 As shown, this application includes a BiCMOS process-compatible adjustable pinch-off voltage PJFET transistor, which includes: a buried layer (BN), a P-type epitaxial layer, a base region, an N-type gate, a source region, and a drain region disposed on a P-type substrate (PSUB).

[0011] Figure 1This is a schematic diagram of the transistor's structure in a longitudinal cross-section. First, an N-type buried layer is formed on a P-type substrate, and a P-type epitaxial layer is formed above the N-type buried layer. The central P+ active region is implanted through the base region to form the drain region of the PJFET transistor. On both sides of the drain region, N+ active regions are implanted through N-type ESD to form the N-type gates of the PJFET transistor. Outside the two N-type gates, P+ active regions are implanted through the base region to form the source regions of the PJFET transistor. Outside the two source regions is an isolation N-well (NW) ring. The N-type buried layer BN constitutes the N-type back gate of the PJFET transistor, and the N-type back gate BN and the isolation N-well ring are electrically connected. Figure 1 In this design, the N-type gate is connected to the NW via a metal lead, and the N-type back gate (BN) and the N-type gate are electrically connected through the N+ within the isolation N-well ring. The annular isolation N-well and the bottom buried BN layer isolate the transistor's channel body region from other P-epitaxial regions. The N-type buried BN layer serves as the transistor's N-type back gate, and the N-type back gate interacts with the N-type gate to clamp the transistor's channel body region.

[0012] This application uses base region implantation to form the source and drain regions of the PJFET transistor, ensuring that the transistor can withstand high-voltage application environments. This application uses N-type ESD (Electro-Static Discharge) implantation to form the N-type gate of the PJFET transistor. Because N-type ESD implantation has a relatively deep junction, it can form an effectively pinch-off PJFET transistor.

[0013] Existing transistors typically do not use N-type ESD injection, but rather a single N-type injection to form the N-type gate of the PJFET transistor based on the N+ active region. This results in a shallow N-type gate junction, leading to weak control over the P-EPI channel. The relatively shallow N-type gate also increases the thickness of the P-EPI channel body, increasing the pinch-off voltage required to clamp the P-EPI channel through the depletion region. Consequently, existing transistor devices cannot be clamped off in low-to-medium voltage applications. In this context, existing PJFETs resemble nonlinear P-epitaxial buried layer resistors rather than true FET devices.

[0014] This application adds an N-type gate to the PJFET transistor formed by N-type ESD injection, based on a single N-type injection. This double-diffused N-type gate provides stronger control over the P-EPI channel. The junction depth of N-type ESD injection is much deeper than that of single N-type injection. In this case, the thickness of the P-EPI in the channel body region is relatively smaller, so the voltage required to pinch off the P-EPI channel is not particularly high. Therefore, this ensures the application of the transistor in low- and medium-voltage circuits.

[0015] This application uses an N-well ring to isolate the channel body region of the PJFET transistor from other P-epitaxial layers, and uses an N-type buried layer (BN) to isolate the channel body region of the PJFET transistor from the PSUB. The N-type buried layer (BN) serves as the N-type back gate of the PJFET transistor, and interacts with the N-type gate formed by N-type ESD injection to jointly clamp the channel body region of the PJFET transistor.

[0016] In this application, the optimal choice for the channel body region of the PJFET transistor, i.e., the P-EPI epitaxial thickness, is approximately 8 micrometers. If the P-EPI epitaxial thickness is too small, the pinch-off voltage of the PJFET transistor will be too low, potentially leading to premature pinch-off during normal operation. If the P-EPI epitaxial thickness is too large, the pinch-off voltage of the PJFET transistor will be too high, potentially preventing pinch-off under normal device operation and resulting in nonlinear P-epitaxy buried layer resistance characteristics.

[0017] like Figure 1 As shown, in this application, the distances between the drain region and the N-type gate, as well as between the source region and the N-type gate, are equal, both being L1; the distance between the source region and the isolation N-well ring is L2. To prevent the N-type ESD injection and base injection lateral diffusion phases from overlapping and forming a PN junction with a low breakdown voltage, the design spacing L1 between them is required to be greater than 5 micrometers. To prevent the N-well isolation ring and base injection from forming a PN junction with a low breakdown voltage, the design spacing L2 between them is required to be greater than 4 micrometers.

[0018] The method for adjusting the pinch-off voltage in the pinch-off region of the transistor in this application is as follows: When the N-type gate, N-type back gate, and source region are connected and all connected to the highest potential VCC, the pinch-off voltage is at its maximum, denoted as: maximum pinch-off voltage; When the N-type gate and N-type back gate are connected, but not connected to the source region, and the N-type gate and N-type back gate are connected to the highest potential VCC, and the voltage difference between the potential of the N-type gate and N-type back gate and the potential of the source region is the largest, the pinch-off voltage is the smallest: denoted as the minimum pinch-off voltage. When the N-type gate and the N-type back gate are connected, but they are not connected to the source region, and the potential of the N-type gate and the N-type back gate is higher than the potential of the source region and the drain region but lower than the highest potential VCC of the circuit, the pinch-off voltage is located between the maximum pinch-off voltage and the minimum pinch-off voltage, which is called the medium pinch-off voltage. The voltage difference between the drain region and the source region is the medium pinch-off voltage value.

[0019] like Figure 2As shown, the N-type gate connects the source region and the isolation N-well (NW) ring via metal leads. The isolation N-well ring is electrically connected to the N-type back gate. When the N-type gate, N-type back gate, and source region are all connected to the highest potential VCC, the PJFET transistor has the maximum pinch-off voltage. Because the N-type gate, N-type back gate, and source region are connected, their potentials are equal, resulting in the minimum width of the PN junction depletion region between them. For the PJFET transistor to pinch off and enter the saturation region, the drain voltage needs to continuously decrease. As the drain voltage decreases, the depletion regions of the N-type gate and body region and the N-type back gate and body region gradually approach each other and eventually meet, pinching off the channel body region. At this point, the voltage difference Vds between the drain and source regions reaches its maximum. The larger the voltage difference, the wider the depletion region, i.e., the highest pinch-off voltage VP.

[0020] like Figure 3 As shown, the N-type gate is connected to the N-type back gate, but there is no connection between the N-type gate and the source region. Assuming the source region potential is VS, the N-type gate potential is VG, the drain region potential is VD, and the highest potential is VCC, then: when VCC>VG>VS>VD, the PJFET transistor has a medium pinch-off voltage. This is because when the potential VG of the N-type gate and N-type back gate is higher than the drain region potential VD and the source region potential VS, the PN junction depletion regions between the N-type gate and the channel body region (hereinafter referred to as: body region) and between the N-type back gate and the body region will extend into the P-EPI epitaxial body region. Therefore, as long as the drain voltage decreases to a medium voltage value, the two closely spaced PN junction depletion regions will be pinched off. At this time, the voltage difference Vds between the drain and source regions is a medium voltage value, i.e., the pinch-off voltage VP is a medium voltage. The boundary line of the PN junction depletion region with a medium pinch-off voltage in the transistor of this application is smoother than the boundary line of the PN junction depletion region with a high pinch-off voltage, i.e., the pinch-off region is wider and the leakage current is smaller.

[0021] like Figure 4 As shown, the N-type gate is connected to the N-type back gate, but there is no connection between the N-type gate and the source region. The N-type gate and N-type back gate are connected to the highest potential VCC. Simultaneously, the PJFET transistor has the minimum pinch-off voltage when the voltage difference between VG and VS is maximized. Since the voltage difference between the N-type gate and N-type back gate potential VG and the source region potential VS reaches its maximum, the PN junction depletion regions between the N-type gate and the body region and between the N-type back gate and the body region extend to the maximum depth into the P-EPI epitaxial body region. Therefore, a slight decrease in the drain voltage will cause the two closely spaced PN junction depletion regions to pinch off. At this time, the voltage difference Vds between the drain and source regions is at its minimum value, i.e., the pinch-off voltage VP is minimum. The boundary line of the PN junction depletion region with low pinch-off voltage in the transistor of this application is smoother than the boundary line of the PN junction depletion region with medium pinch-off voltage.

[0022] In summary, this application adjusts the pinch-off voltage by controlling the voltage difference between the N-type gate, the N-type back gate voltage VG, and the source region voltage VS, thereby meeting the circuit's requirements for PJFET transistors with different pinch-off voltages and ensuring that the transistors can be flexibly applied in various high, medium, and low pinch-off voltage applications, such as analog switches or current sources.

[0023] like Figure 5 The diagram shows the layout of a PJFET transistor. At the very center is a circular P+ drain region 1 formed by base implantation, with a designed width of 10 micrometers. Outside the drain region is a circular N-type gate 2 formed by N-type ESD implantation, also with a designed width of 10 micrometers. Outside the N-type gate 2 is a circular P+ source region 3 formed by base implantation, with a designed width of 10 micrometers. Outside the source region 3 is a circular isolation N-well 4, with a designed width of 8 micrometers. The isolation N-well 4 is electrically connected to the N-type back gate (BN) buried layer of the PJFET transistor.

[0024] In this application, the transistor layout is a ring-shaped closed structure; the transistor layout structure is symmetrical vertically with respect to the horizontal axis passing through the center of the middle drain region 1, and symmetrical horizontally with respect to the vertical axis passing through the center of the circle, ensuring that all paths from the source to the drain are the same distance, that is, the resistance in each direction of the source and drain channels is uniform, thereby ensuring that the PJFET transistor device in this application has good performance.

[0025] Traditional PJFET transistors use P-type implantation to form the source and drain terminals. The conductive channel of a PJFET transistor is a P-EPI epitaxial layer, but the low doping concentration of the P-type epitaxial layer results in a high channel resistance. To optimize and reduce the source-drain resistance, this application, based on P-type implantation, adds the use of a deeper base region implantation to form the source and drain terminals of the PJFET transistor. This double-diffused source and drain terminal reduces the longitudinal P-epitaxial resistances RS and RD to some extent.

[0026] like Figure 6 As shown, the channel resistance between the source and drain regions of the PJFET transistor in this application consists of the vertical P-epitaxial resistances RS and RD, and the lateral P-epitaxial resistance RC. Since the base region implantation concentration is higher than the P-epitaxial concentration, the base region resistance is much smaller than the P-epitaxial resistance, and the deeper base region implantation can reduce part of the vertical P-epitaxial resistance. Therefore, the base region implantation used in this application can effectively reduce the channel resistance between the source and drain of the PJFET transistor.

[0027] like Figure 7As shown, this application utilizes the lower isolation layer (BN buried layer) of the PJFET transistor as an N-type back gate. This N-type back gate and the N-type gate formed by N-type ESD injection jointly act on the channel, enhancing the control capability of the P-EPI epitaxial channel. The BN buried layer, acting as the N-type back gate, controls the upward expansion of its and the P-EPI epitaxial PN junction depletion region, while the N-type gate controls its and the P-EPI epitaxial PN junction depletion region downward expansion. This combined action allows the PJFET transistor to be pinched off under low to medium voltage conditions, thus enabling its effective application in low to medium voltage circuits.

[0028] like Figure 8 As shown, based on the PJFET transistor in this application, if the metal connection between the N-type gate and NW is disconnected, that is, the potential of the N-type back gate BN is not connected to the N-type gate, a P-type epitaxial buried layer resistor with a very high resistance is formed. At the same time, the pinch-off voltage range is wider, which can be used in scenarios such as current sampling circuits.

[0029] The test results of the PJFET transistor PCM (Process Control Monitoring) parameters in this application are attached. Figure 9 As shown in the table, due to differences in each process parameter, the measured pinch-off voltage of PJFET transistors fabricated using different processes will vary. This table only represents the measured pinch-off voltage VP of PJFET transistors fabricated using the process described in this application. Although the pinch-off voltage of PJFET transistors fabricated using different processes differs, Figure 9 The data in the table is still a very good reference.

Claims

1. A programmable pinch-off voltage (PJFET) transistor compatible with a BiCMOS process, comprising: A buried layer, an epitaxial layer, a base region, a source region, and a drain region disposed on a P-type substrate, characterized in that: An N-type buried layer is formed on a P-type substrate, and a P-type epitaxial layer is formed above the N-type buried layer. On the P-type epitaxial layer, a circular P+ drain region is formed by base region implantation; an annular N-type gate is formed around the drain region by N-type ESD implantation; an annular P+ source region is formed around the N-type gate by base region implantation; an annular isolation N-well is disposed outside the source region, and the isolation N-well is electrically connected to the BN buried layer of the transistor. The channel body region of the transistor is isolated from other P-epitaxial regions by using a ring-shaped isolation N-well and a bottom BN buried layer. The N-type buried layer BN is used as the N-type back gate of the transistor, and the N-type back gate and the N-type gate interact to jointly clamp the channel body region of the transistor. The method for adjusting the pinch-off voltage in the pinch-off body region is as follows: When the N-type gate, N-type back gate, and source region are connected and all connected to the highest potential VCC, the pinch-off voltage is at its maximum, denoted as: maximum pinch-off voltage; When the N-type gate and N-type back gate are connected, but not connected to the source region, and the N-type gate and N-type back gate are connected to the highest potential VCC, and the voltage difference between the potential of the N-type gate and N-type back gate and the potential of the source region is the largest, the pinch-off voltage is the smallest: denoted as the minimum pinch-off voltage. When the N-type gate and the N-type back gate are connected, but they are not connected to the source region, and the potential of the N-type gate and the N-type back gate is higher than the potential of the source region and the drain region but lower than the highest potential VCC of the circuit, the pinch-off voltage is located between the maximum pinch-off voltage and the minimum pinch-off voltage, which is called the medium pinch-off voltage. The voltage difference between the drain region and the source region is the medium pinch-off voltage value.

2. The BiCMOS process compatible programmable pinch-off voltage (PJFET) transistor of claim 1, wherein: The N-type back gate BN achieves potential connection with the N-type gate by isolating the N+ in the N-well ring.

3. The BiCMOS process compatible programmable pinch-off voltage (PJFET) transistor of claim 1, wherein: The thickness of the P-EPI epitaxial layer in the channel body region of the transistor is controlled to be 8 micrometers.

4. The adjustable pinch-off voltage PJFET transistor compatible with BiCMOS process according to claim 1, characterized in that: The distance between the drain region and the N-type gate, as well as the distance between the source region and the N-type gate, is greater than 5 micrometers.

5. The adjustable pinch-off voltage PJFET transistor compatible with BiCMOS process according to claim 1, characterized in that: The spacing between the source region and the isolation N-well ring is greater than 4 micrometers.

6. The adjustable pinch-off voltage PJFET transistor compatible with BiCMOS process according to claim 1, characterized in that: The transistor has a closed ring structure; the structure of the transistor is symmetrical about the horizontal axis passing through the center of the ring, and also symmetrical about the vertical axis passing through the center of the ring.

Images