An LED chip preparation method and an LED chip

Abstract

The application provides an LED chip preparation method and an LED chip. A semi-finished chip containing a current blocking layer is prepared. An ITO film layer is prepared on the current blocking layer by using an electron beam evaporation method. The semi-finished chip is immersed in an acid solution so that the acid solution penetrates the ITO film layer to erode the current blocking layer. The ITO film layer prepared by using the electron beam evaporation method is more loose than a film layer obtained by using a magnetron sputtering before annealing. Because the ITO film layer is less dense before annealing, the loose characteristic of the unannealed ITO film layer can be used to deposit the ITO film layer above the current blocking layer. The ITO film layer is immersed in an HF solution. The HF acid penetrates the ITO film layer to etch the bottom current blocking layer by the diffusion of the loose film layer. The etching effect is a porous structure, thereby achieving the roughening purpose of the surface of the current blocking layer.

Description

Technical Field

[0001] This invention relates to the field of LED technology, and in particular to an LED chip fabrication method and an LED chip. Background Technology

[0002] A light-emitting diode (LED) is a semiconductor electronic component that emits light. Due to its small size, high brightness, and low power consumption, it has attracted increasing attention from researchers.

[0003] In recent years, with the great progress made in P-type gallium nitride doping technology, gallium nitride-based LEDs, which have excellent characteristics such as fast response, long life, low power consumption, small size and high brightness, have been widely used in backlights for LCD displays, full-color displays, traffic displays and other applications. However, light extraction efficiency has always been a technical challenge that has hindered its development.

[0004] Currently, the light extraction efficiency of gallium nitride-based LEDs depends on both internal quantum efficiency and light extraction efficiency. While internal quantum efficiency has been maximized, the significant difference in refraction between the surface material and air makes it easy for full emission to occur at the interface, resulting in a lower external quantum efficiency. Therefore, external quantum efficiency still needs further improvement. Summary of the Invention

[0005] Based on this, the purpose of this invention is to provide an LED chip fabrication method and an LED chip, aiming to solve the problem that in the prior art, the light extraction efficiency of gallium nitride-based LEDs currently depends on the internal quantum efficiency and the light extraction efficiency. While the internal quantum efficiency has been maximized, the large difference in refraction between the surface material and air makes it easy to form full emission at the interface, resulting in a low external quantum efficiency.

[0006] According to an embodiment of the present invention, an LED chip fabrication method includes:

[0007] Provide a semi-finished chip containing a current blocking layer;

[0008] An ITO film was prepared on the current blocking layer using electron beam evaporation.

[0009] The semi-finished chip is immersed in an acidic solution so that the acidic solution penetrates the ITO film layer and erodes the current blocking layer.

[0010] Furthermore, the thickness of the ITO film is 25 nm to 110 nm.

[0011] Furthermore, the acidic solution is an HF solution.

[0012] Furthermore, the concentration of the HF solution is 5 mol / L to 25 mol / L.

[0013] Furthermore, the semi-finished chip is immersed in an acidic solution for 30 to 100 minutes.

[0014] Furthermore, the step of providing a semi-finished chip including a current blocking layer includes:

[0015] Provide a substrate required for growth;

[0016] An epitaxial layer is formed by sequentially growing an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer on the substrate.

[0017] The epitaxial layer is etched by ICP to expose the N-type semiconductor layer on the epitaxial layer;

[0018] A current blocking layer is deposited on the etched epitaxial layer using PECVD, and photolithography and photoresist exposure and development are performed sequentially on the surface of the current blocking layer to retain the current blocking layer above the N-type semiconductor layer.

[0019] Furthermore, after the step of immersing the semi-finished chip in an acidic solution to allow the acidic solution to penetrate the ITO film and erode the current blocking layer, the following steps are included:

[0020] The soaked semi-finished chip is cleaned and placed in a rapid annealing furnace for annealing.

[0021] The surface of the semi-finished chip after annealing is subjected to photoluminescence treatment.

[0022] The semi-finished chip after photolithography is subjected to wet etching, while retaining the ITO film layer;

[0023] The semi-finished chip after wet etching is placed directly above the electron beam evaporation machine, and Cr, Al, Ti, Ni, Pt, Ni, Pt and Au layers are sequentially deposited on the semi-finished chip facing the evaporation source emitter on the electron beam evaporation machine.

[0024] A silicon oxide passivation layer is deposited on the surface of the semi-finished chip after electron beam evaporation to form an LED chip.

[0025] Furthermore, the annealing temperature in the rapid annealing furnace is 500℃~600℃, and the annealing time is 14min~16min.

[0026] Furthermore, the thickness of the current blocking layer is 290nm to 310nm.

[0027] In addition, the present invention also proposes an LED chip, which is prepared by any of the LED chip preparation methods described above.

[0028] Compared with existing technologies, the method of preparing ITO films using electron beam evaporation produces ITO films that are more porous before annealing compared to those obtained by magnetron sputtering. Because the ITO films are less dense before annealing, the porous nature of the unannealed ITO films can be utilized to deposit an ITO film on top of the current blocking layer. This film is then immersed in an HF solution. Through the diffusion effect of the porous film, the HF acid permeates the ITO film and etches the bottom current blocking layer, resulting in a porous structure. This achieves the purpose of roughening the surface of the current blocking layer. Attached Figure Description

[0029] Figure 1 This is a schematic flowchart of an LED chip fabrication method provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a surface roughening structure for an LED chip disclosed in an embodiment of the present invention. Detailed Implementation

[0031] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0032] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] This invention addresses the problem that existing chips are easily susceptible to moisture intrusion, leading to short circuits in the electrodes. It proposes a method for fabricating an LED chip and an LED chip thereof, wherein:

[0035] Please see Figure 1 The diagram shows a flowchart of an LED chip fabrication method according to an embodiment of the present invention, which includes steps S01 to S03:

[0036] Step S01: Provide a semi-finished chip containing a current blocking layer.

[0037] Specifically, a substrate required for growth is provided. In some optional embodiments of the present invention, the substrate may include, but is not limited to, one of a sapphire substrate, a SiO2-sapphire composite substrate, a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, and a zinc oxide substrate. In this embodiment, a sapphire substrate may be selected. Sapphire is currently the most commonly used GaN-based LED substrate material, and most GaN-based LEDs on the market use sapphire as the substrate material. The biggest advantages of sapphire substrates are mature technology, good stability, and low production cost.

[0038] Subsequently, an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer are sequentially grown on the substrate to form an epitaxial layer. This epitaxial layer can be grown on the substrate using metal chemical vapor deposition (MOCVD), employing high-purity hydrogen as the carrier gas, high-purity ammonia as the nitrogen source, trimethylgallium and triethylgallium as gallium sources, trimethylindium as the indium source, silane as the N-type dopant, trimethylaluminum as the aluminum source, and magnesia-dicenocene as the P-type dopant. The thickness of the N-type semiconductor layer is 1 μm to 3 μm, with a Si doping concentration of 5 × 10¹⁸–1 × 10¹⁹ cm⁻³; the thickness of the P-type semiconductor layer is 200 nm to 300 nm, with a Mg doping concentration of 5 × 10¹⁷–1 × 10²⁰ cm⁻³; and the molar proportion of In in the light-emitting layer is 10%–35%. Finally, the epitaxial layer growth on the substrate is completed by satisfying the above conditions.

[0039] The epitaxial layer is etched using ICP to expose the N-type semiconductor layer on the epitaxial layer.

[0040] A current blocking layer was deposited on the etched epitaxial layer using PECVD, and photolithography and photoresist exposure and development were performed on the surface of the current blocking layer in sequence to retain the current blocking layer above the N-type semiconductor layer.

[0041] Specifically, a current blocking layer with a thickness of 290nm to 310nm is deposited on the etched epitaxial layer using PECVD; then, photolithography and photoresist exposure and development are performed sequentially on the surface of the current blocking layer to retain the current blocking layer above the N-type semiconductor layer. In some optional embodiments of the present invention, the material of the current blocking layer can be silicon oxide, silicon nitride, and aluminum oxide.

[0042] Step S02: An ITO film is prepared on the current blocking layer using electron beam evaporation.

[0043] Specifically, ITO films with a thickness of 25nm to 110nm are prepared on the current blocking layer using electron beam evaporation. The conventional magnetron sputtering is replaced by electron beam evaporation. Electron beam evaporation is a type of physical vapor deposition. Unlike traditional evaporation methods, electron beam evaporation uses electromagnetic fields to precisely bombard the target material in the crucible with high-energy electrons, causing it to melt and deposit onto the substrate. Electron beam evaporation can deposit high-purity and high-precision thin films.

[0044] Step S03: Immerse the semi-finished chip in an acidic solution so that the acidic solution can penetrate the ITO film layer and erode the current blocking layer.

[0045] It should be noted that the ITO film layer prepared in this application is prepared by electron beam evaporation. The ITO film layer prepared by this method is more porous than the film layer obtained by magnetron sputtering before annealing. Because the ITO film layer has poor density before annealing, the porous nature of the unannealed ITO film layer can be used to deposit an ITO film layer on top of the current blocking layer. The film layer is then immersed in HF solution. Through the diffusion effect of the porous film layer, the HF acid penetrates the ITO film layer and etches the bottom current blocking layer. The etching effect is a porous structure, thereby achieving the purpose of roughening the surface of the current blocking layer.

[0046] Specifically, the semi-finished chip with an ITO film layer on its surface is immersed in an acidic HF solution with a concentration of 5 mol / L to 25 mol / L, so that the acidic HF solution can penetrate the ITO film layer and erode the current blocking layer. The immersion time is 30 min to 100 min.

[0047] In some optional embodiments of the present invention, the roughness of the current blocking layer obtained under different conditions, wherein the different conditions are only the ITO film thickness, HF solution concentration, immersion time, and roughness, are as follows:

[0048] 25nm 5mol / L 30min 15nm 45nm 10mol / L 45min 26nm 60nm 15mol / L 60min 40nm 110nm 25mol / L 75min 100nm

[0049] Additionally, in some optional embodiments of the present invention, after the step of immersing the semi-finished chip in an acidic solution to allow the acidic solution to penetrate the ITO film layer and erode the current blocking layer, the following steps are included:

[0050] After soaking, the semi-finished chips are cleaned and placed in a rapid annealing furnace for annealing.

[0051] The surface of the semi-finished chip after annealing is subjected to photoluminescence treatment.

[0052] The semi-finished chip after photolithography is wet-etched, while retaining the ITO film layer.

[0053] In practice, due to the poor density of the ITO film after deposition, annealing can make the crystal arrangement more orderly, the film more dense, and the conductivity more stable. After soaking, the wafer is cleaned and placed in an RTA rapid annealing furnace. The annealing temperature is 500℃~600℃ and the annealing time is 14min~16min. After annealing, photolithography is performed, and the ITO film at the corresponding positions is retained by wet etching.

[0054] The semi-finished chip after wet etching is placed directly above the electron beam evaporation machine, and Cr, Al, Ti, Ni, Pt, Ni, Pt and Au layers are sequentially deposited on the semi-finished chip facing the evaporation source emitter on the electron beam evaporation machine.

[0055] A silicon oxide passivation layer is deposited on the surface of the semi-finished chip after electron beam evaporation to form an LED chip.

[0056] In this process, a silicon oxide passivation layer with a thickness between 75nm and 85nm is deposited on the surface of the semi-finished chip using PECVD to produce the final LED chip.

[0057] In summary, the LED chip fabrication method and LED chip in this embodiment of the invention employ electron beam evaporation to prepare an ITO film. The ITO film prepared by this method is more porous than that obtained by magnetron sputtering before annealing. Because the ITO film has poor density before annealing, its porous nature allows for the deposition of an ITO film on top of the current blocking layer. Immersing the film in an HF solution allows the HF acid to penetrate the ITO film and etch the bottom current blocking layer through diffusion. The etching effect results in a porous structure, thereby achieving surface roughening of the current blocking layer. The roughening effect is comparable to conventional roughening methods, and the process is simpler and more economical. This invention solves the problem that the light extraction efficiency of gallium nitride-based LEDs depends on both internal quantum efficiency and light extraction efficiency. While internal quantum efficiency has been maximized, the significant difference in refraction between the surface material and air easily leads to full emission at the interface, resulting in low external quantum efficiency.

[0058] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating an LED chip, characterized in that, The preparation method includes: Provide a substrate required for growth; An epitaxial layer is formed by sequentially growing an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer on the substrate. The epitaxial layer is etched by ICP to expose the N-type semiconductor layer on the epitaxial layer; A current blocking layer is deposited on the etched epitaxial layer using PECVD to obtain a semi-finished chip containing the current blocking layer. The surface of the current blocking layer is then subjected to photolithography and photoresist exposure and development to retain the current blocking layer above the N-type semiconductor layer. An ITO film was prepared on the current blocking layer using electron beam evaporation. The semi-finished chip is immersed in an acidic solution so that the acidic solution penetrates the ITO film layer and erodes the current blocking layer. The thickness of the ITO film is 25nm~110nm.

2. The LED chip fabrication method according to claim 1, characterized in that, The acidic solution is an HF solution.

3. The LED chip fabrication method according to claim 2, characterized in that, The concentration of the HF solution is 5 mol / L to 25 mol / L.

4. The LED chip fabrication method according to claim 1, characterized in that, The semi-finished chip is immersed in an acidic solution for 30 to 100 minutes.

5. The LED chip fabrication method according to claim 1, characterized in that, The step of immersing the semi-finished chip in an acidic solution to allow the acidic solution to penetrate the ITO film and erode the current blocking layer includes: The soaked semi-finished chip is cleaned and placed in a rapid annealing furnace for annealing. The surface of the semi-finished chip after annealing is subjected to photoluminescence treatment. The semi-finished chip after photolithography is subjected to wet etching, while retaining the ITO film layer; The semi-finished chip after wet etching is placed directly above the electron beam evaporation machine, and Cr, Al, Ti, Ni, Pt, Ni, Pt and Au layers are sequentially deposited on the semi-finished chip facing the evaporation source emitter on the electron beam evaporation machine. A silicon oxide passivation layer is deposited on the surface of the semi-finished chip after electron beam evaporation to form an LED chip.

6. The LED chip fabrication method according to claim 5, characterized in that, The annealing temperature in the rapid annealing furnace is 500℃~600℃, and the annealing time is 14min~16min.

7. The LED chip fabrication method according to claim 1, characterized in that, The thickness of the current blocking layer is 290nm~310nm.

8. An LED chip, characterized in that, The LED chip is prepared using the method described in any one of claims 1 to 7.

Images