Analog-to-digital conversion device and offset correction method

Abstract

An analog-to-digital conversion device and offset correction method. The analog-to-digital conversion device includes an N-stage first ADC (analog-to-digital converter), a second ADC, a correction circuit, a data recovery circuit, and an output circuit. The N-stage first ADC time-interleaved converts an input signal into multi-stage first quantization outputs at a first sampling frequency. The second ADC converts the input signal into a second quantization output at a second sampling frequency. The first sampling frequency is (N+1) / N times the second sampling frequency. The correction circuit corrects the multi-stage first quantization outputs and the second quantization output to generate multi-stage third quantization outputs and fourth quantization outputs. The data recovery circuit outputs one of the multi-stage third quantization outputs as a fifth quantization output at the second sampling frequency, and subtracts the fifth quantization output from the fourth quantization output to generate output data. The output circuit generates an output signal according to the multi-stage third quantization outputs and the output data. The device and method can generate a correct output signal when the frequency of the input signal is an integer multiple of the first sampling frequency.

Description

Technical Field

[0001] This disclosure relates to an analog-to-digital conversion technique, and more particularly to an analog-to-digital conversion device and offset correction method for preventing the loss of sampling results. Background Technology

[0002] Analog-to-digital converters (ADCs) are widely used in communication systems, electronic instruments, and various computer systems. Due to process variations, the output signal of an ADC may contain offset errors. For example, when a 0V signal is input to an ADC, the ADC output signal may correspond to a non-0V signal. The degree of offset may vary between different ADCs due to usage conditions or random variations in components, making it difficult to uniformly correct at the factory. Therefore, ADCs typically have automatic offset correction functions. However, when the signal input to the ADC has certain specific frequencies, the ADC's automatic offset correction function may incorrectly eliminate the ADC's sampling results. Summary of the Invention

[0003] This disclosure provides an analog-to-digital converter (ADC) comprising an N-stage first ADC, a second ADC, a first correction circuit, a data recovery circuit, and an output circuit. The N-stage first ADC has a first sampling frequency for converting an input signal into multiple stages of first quantized outputs in a time-interleaved manner, where N is a positive integer greater than or equal to 2. The second ADC has a second sampling frequency for converting the input signal into a second quantized output. The first sampling frequency is (N+1) / N times the second sampling frequency. The first correction circuit corrects the offset between the multiple stages of first quantized outputs and second quantized outputs to generate multiple stages of third quantized outputs and fourth quantized outputs, respectively. The data recovery circuit is coupled to the first correction circuit and outputs one of the multiple stages of third quantized outputs at the second sampling frequency as a fifth quantized output, and subtracts the fifth quantized output from the fourth quantized output to generate multiple output data. The output circuit generates an output signal based on the multiple stages of third quantized outputs and the multiple output data.

[0004] In some embodiments of the analog-to-digital converter, in two consecutive samplings of the second ADC, the second ADC is sampled substantially simultaneously with the (K-1)th stage first ADC in the N-stage first ADC, and then sampled substantially simultaneously with the Kth stage first ADC in the N-stage first ADC, where K is a positive integer less than or equal to N.

[0005] In some embodiments of the analog-to-digital converter, the analog-to-digital converter operates as a time-interleaved analog-to-digital converter with a system sampling period. The data recovery circuit includes a selection circuit. The selection circuit is used to receive multiple levels of third quantization output and to output one of the multiple levels of third quantization output as a fifth quantization output every N system sampling periods. The sampling time interval between the current third quantization output of the selection circuit and the sampling time interval of the previous third quantization output of the selection circuit is (N+1) system sampling periods.

[0006] In some embodiments of the analog-to-digital converter, the data recovery circuit further includes a second correction circuit. The second correction circuit is coupled to the selection circuit and is used to correct an offset in one of the multiple stages of third quantization outputs to produce a fifth quantization output.

[0007] In some embodiments of the analog-to-digital converter, the data recovery circuit further includes a second correction circuit. The second correction circuit is coupled to a selection circuit for eliminating components relating to crosstalk signals from one of the multiple third quantization outputs, wherein the frequency of the crosstalk signal is substantially the same as the second sampling frequency.

[0008] In some embodiments of the analog-to-digital converter, the data recovery circuit includes processing circuitry. The processing circuitry includes a first demultiplexer, a second demultiplexer, and a plurality of first operational circuits. The first demultiplexer is used to distribute a fifth quantized output into a plurality of first data. The second demultiplexer is used to distribute a fourth quantized output into a plurality of second data. The plurality of first operational circuits are used to subtract the plurality of first data from the plurality of second data to produce a plurality of output data.

[0009] In some embodiments of the analog-to-digital converter, the sampling times corresponding to the plurality of first data are substantially the same as the sampling times corresponding to the plurality of second data.

[0010] In some embodiments of the analog-to-digital converter, the processing circuitry further includes a plurality of first averaging filters and a plurality of second averaging filters. The plurality of first averaging filters are used to average the plurality of outputs of the first demultiplexer respectively to generate a plurality of first data.

[0011] In some embodiments of the analog-to-digital converter, a first correction circuit includes a plurality of first sub-correction circuits and a second sub-correction circuit. The plurality of first sub-correction circuits are each coupled to an N-stage first ADC. Each sub-correction circuit includes a third averaging filter and a second operational circuit. The third averaging filter is used to average a corresponding output of multiple stages of first quantization. The second operational circuit is used to subtract the output of the third averaging filter from the corresponding output of the multiple stages of first quantization to produce a corresponding output of multiple stages of third quantization. The second sub-correction circuit is coupled to a second ADC and includes a fourth averaging filter and a third operational circuit. The fourth averaging filter is used to average a second quantization output. The third operational circuit is used to subtract the output of the fourth averaging filter from the second quantization output to produce a fourth quantization output.

[0012] This disclosure provides an offset correction method applicable to an analog-to-digital converter. The analog-to-digital converter includes N-stage first ADCs and a second ADC. The offset correction method includes the following steps: using the N-stage first ADC in a time-interleaved manner, converting the input signal into multiple stages of first quantized outputs according to a first sampling frequency, where N is a positive integer greater than or equal to 2; using the second ADC, converting the input signal into a second quantized output according to a second sampling frequency, where the first sampling frequency is (N+1) / N times the second sampling frequency; correcting the offset between the multiple stages of first quantized outputs and second quantized outputs to generate multiple stages of third quantized outputs and fourth quantized outputs respectively; outputting one of the multiple stages of third quantized outputs at the second sampling frequency as a fifth quantized output; subtracting the fifth quantized output from the fourth quantized output to generate multiple output data; and generating an output signal based on the multiple stages of third quantized outputs and the multiple output data.

[0013] In some embodiments of the offset correction method, in two consecutive samplings of the second ADC, the second ADC is sampled substantially simultaneously with the (K-1)th stage first ADC in the N-stage first ADC, and then sampled substantially simultaneously with the Kth stage first ADC in the N-stage first ADC, where K is a positive integer less than or equal to N.

[0014] In some embodiments of the offset correction method, the analog-to-digital converter operates as a time-interleaved analog-to-digital converter with a system sampling period. Outputting one of multiple levels of third quantization outputs as a fifth quantization output at a second sampling frequency includes: outputting one of multiple levels of third quantization outputs as the fifth quantization output every N system sampling periods, wherein the sampling time of the current third quantization output is (N+1) system sampling periods relative to the sampling time of the previous third quantization output.

[0015] In some embodiments of the offset correction method, outputting one of the multi-level third quantization outputs as the fifth quantization output every N system sampling cycles includes: correcting the offset of one of the multi-level third quantization outputs to produce the fifth quantization output.

[0016] In some embodiments of the offset correction method, the fifth quantization output, which is one of the multi-level third quantization outputs every N system sampling cycles, includes: eliminating components related to crosstalk signals from one of the multi-level third quantization outputs, wherein the frequency of the crosstalk signal is substantially the same as the second sampling frequency.

[0017] In some embodiments of the offset correction method, subtracting the fifth quantization output from the fourth quantization output to generate multiple output data includes: allocating the fifth quantization output as multiple first data; allocating the fourth quantization output as multiple second data; and subtracting the multiple first data from each of the multiple second data to obtain multiple output data.

[0018] In some embodiments of the offset correction method, the sampling times corresponding to the multiple first data are substantially the same as the sampling times corresponding to the multiple second data.

[0019] In some embodiments of the offset correction method, multiple signals formed by allocating the fifth quantization output are averaged separately to form multiple first data, and multiple signals formed by allocating the fourth quantization output are averaged separately to form multiple second data.

[0020] In some embodiments of the offset correction method, correcting the offset of the multi-level first quantization output includes: averaging the multi-level first quantization output to produce an averaged multi-level first quantization output; averaging the multi-level first quantization output to produce an averaged multi-level first quantization output; averaging the second quantization output to produce an averaged second quantization output; and subtracting the averaged second quantization output from the second quantization output to produce a fourth quantization output.

[0021] The aforementioned analog-to-digital converter and offset correction method can generate a correct output signal without losing the sampling results when the frequency of the input signal is an integer multiple of the sampling frequency of the first ADC. Attached Figure Description

[0022] Figure 1 This is a simplified functional block diagram of an analog-to-digital converter according to an embodiment of this disclosure.

[0023] Figure 2 for Figure 1 The waveform diagrams of multiple clock signals in some embodiments;

[0024] Figure 3This is a schematic diagram of the signal components of an input signal according to an embodiment of this disclosure;

[0025] Figure 4 This is a schematic diagram of the operation of a selection circuit according to an embodiment of this disclosure;

[0026] Figure 5 This is a simplified functional block diagram of a processing circuit according to an embodiment of this disclosure.

[0027] Figure 6 This is a simplified functional block diagram of a first sub-correction circuit according to an embodiment of this disclosure.

[0028] Figure 7 This is a flowchart of an offset correction method according to an embodiment of this disclosure.

[0029] [Symbol Explanation]

[0030] 100: Analog-to-digital converter

[0031] 1100~1103: First Analog-to-Digital Converter

[0032] 120: Second Analog-to-Digital Converter

[0033] 130: First correction circuit

[0034] 1320~1323: First Sub-Correction Circuit

[0035] 134: Second Sub-Correction Circuit

[0036] 140: Data Recovery Circuit

[0037] 142: Selection Circuit

[0038] 144: Processing Circuit

[0039] 146: Second correction circuit

[0040] 150: Output Circuit

[0041] CLKA0~CLKA3: First clock signal

[0042] CLKB: Second Clock Signal

[0043] DO0~DO3: Output data

[0044] QA0~QA3: First quantization output

[0045] QB: Second Quantization Output

[0046] QC0~QC3: Third quantization output

[0047] QD: Fourth Quantization Output

[0048] QE: Fifth Quantization Output

[0049] SIN: Input signal

[0050] SOUT: Output signal

[0051] TS: System sampling period

[0052] fs: System sampling frequency

[0053] TM1, TM2, TP1~TP21: Sampling time

[0054] 310: Target signal

[0055] 320: Crosstalk signal

[0056] 510: First solution multiplexer

[0057] 520: Second solution multiplexer

[0058] 5300~5303: First averaging filter

[0059] 5400~5403: Second averaging filter

[0060] 5500~5503: First operational circuit

[0061] DA0~DA3: First data

[0062] DB0~DB3: Second Data

[0063] X0~X3, Y0~Y3: Output terminals

[0064] 610: Third averaging filter

[0065] 620: Second operational circuit

[0066] 700: Offset Correction Method

[0067] S710~S760: Steps Detailed Implementation

[0068] The embodiments of this disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0069] Figure 1 This is a simplified functional block diagram of an analog-to-digital converter 100 according to an embodiment of this disclosure. Figure 2 for Figure 1 The waveform diagrams of the multiple clock signals in some embodiments are shown below. Please also refer to... Figure 1 and Figure 2 The analog-to-digital converter 100 includes multiple stages of first ADCs (analog-to-digital converters) 1100-1103, a second ADC 120, a first correction circuit 130, a data recovery circuit 140, and an output circuit 150. The first ADCs 1100-1103 sample the input signal SIN based on multiple first clock signals CLKA0-CLKA3 respectively, to generate multiple stages of first quantization outputs QA0-QA3 respectively. In some embodiments, the analog-to-digital converter 100 may further include a time-skew correction circuit and / or a gain correction circuit; for simplicity, these circuits are not shown. Figure 1 middle.

[0070] like Figure 2 As shown, the first clock signals CLKA0 to CLKA3 are time-interleaved signals. There is a time interval between adjacent signals in the first clock signals CLKA0 to CLKA3, allowing the first ADCs 1100 to 1103 to sample the input signal SIN and perform analog-to-digital conversion at different times. For example, based on the first clock signal CLKA0, the first ADC 1100 can sample at sampling time TM1. Based on the first clock signal CLKA1, the first ADC 1101 can sample at sampling time TM2. The first ADCs 1100 to 1103 are used to interleave the input signal SIN, such that the analog-to-digital converter 100 operates as a time-interleaved analog-to-digital converter in one embodiment. In one embodiment, the difference between sampling time TM1 and sampling time TM2 is one system sampling period TS of the analog-to-digital converter 100, and the reciprocal of the system sampling period TS is the system sampling frequency fs of the analog-to-digital converter 100, i.e., TS = 1 / fs.

[0071] The second ADC 120 samples the input signal SIN based on the second clock signal CLKB to generate the second quantized output QB. The frequencies of the first clock signals CLKA0 to CLKA3 are higher than the frequency of the second clock signal CLKB, causing the first sampling frequency of the first ADCs 1100 to 1103 to be higher than the second sampling frequency of the second ADC 120. The second ADC 120 helps improve the accuracy of the sampling results of the first ADCs 1100 to 1103, which will be explained in more detail in subsequent paragraphs.

[0072] In the embodiments described in the following paragraphs, for ease of explanation, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3) is assumed to be 500MHz, and the second sampling frequency (or the frequency of the second clock signal CLKB) is assumed to be 400MHz. However, the number of first ADCs 1100 to 1103, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3), and the second sampling frequency (or the frequency of the second clock signal CLKB) in this disclosure are not limited to the exemplary embodiments described in the preceding and following paragraphs. In some embodiments, when the analog-to-digital converter 100 includes N levels of first ADCs, the first sampling frequency (or the frequency of the first clock signals CLKA0 to CLKA3) is (N+1) / N times the second sampling frequency (or the frequency of the second clock signal CLKB), where N is a positive integer greater than or equal to 2. In other words, the first sampling frequency is fs / N, and the second sampling frequency is fs / (N+1).

[0073] The first correction circuit 130 is coupled to the first ADC 1100-1103, the second ADC 120, the data recovery circuit 140, and the output circuit 150. The first correction circuit 130 is used to correct the offset of the first quantization outputs QA0-QA3 to generate multiple levels of third quantization outputs QC0-QC3, and to correct the offset of the second quantization output QB to generate a fourth quantization output QD. The third quantization outputs QC0-QC3 are transmitted to the data recovery circuit 140 and the output circuit 150. The fourth quantization output QD is transmitted to the data recovery circuit 140.

[0074] In detail, the first correction circuit 130 includes multiple first sub-correction circuits 1320-1323 and a second sub-correction circuit 134. The first sub-correction circuits 1320-1323 are coupled to the first ADCs 1100-1103, respectively, and the second sub-correction circuit 134 is coupled to the second ADC 120. The first sub-correction circuits 1320-1323 have similar operations; for simplicity, only the first sub-correction circuit 1320 will be described below as an example. The first sub-correction circuit 1320 is used to average the first quantized output QA0 to obtain an offset correction amount for the first quantized output QA0. Then, the first sub-correction circuit 1320 subtracts its offset correction amount from the first quantized output QA0 to generate a third quantized output QC0. Additionally, the second sub-correction circuit 134 is used to average the second quantized output QB to obtain an offset correction amount for the second quantized output QB. Then, the second sub-correction circuit 134 subtracts its offset correction amount from the second quantized output QB to generate a fourth quantized output QD.

[0075] In some cases, the first correction circuit 130 may incorrectly correct the first quantization outputs QA0 to QA3. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of the signal components of an input signal SIN according to an embodiment of this disclosure. The input signal SIN includes a target signal 310 with a frequency of 500 MHz, wherein the analog-to-digital converter 100 is ideally used to generate a digital output signal SOUT based on the target signal 310. Figure 3 In this system, the interval between two adjacent sampling times TP1 to TP21 is one system sampling period TS.

[0076] When the frequency of the target signal 310 is the same as the first sampling frequency of the first ADCs 1100-1103 (e.g., all 500MHz), or when the frequency of the target signal 310 is a positive integer multiple of the first sampling frequency (e.g., when the first ADC has N levels, the frequency of the target signal 310 is fs×i / N, where i is a positive integer), the first ADCs 1100-1103 will each continuously sample the target signal 310 and obtain the same value. In this case, since the first correction circuit 130 obtains the offset correction amount through averaging, each offset correction amount will be the same as its corresponding first quantization output rather than equal to the true offset, causing the first correction circuit 130 to incorrectly correct the first quantization outputs QA0-QA3.

[0077] For example, such as Figure 3 As shown, when the first ADC 1100 samples the target signal 310, the target signal 310 is approximately 0.1V, causing the first quantization output QA0 to remain at 0.1V. Accordingly, the first correction circuit 130 calculates the offset correction amount of the first quantization output QA0 to be 0.1V, so that the third quantization output QC0 (i.e., the corrected first quantization output QA0) corresponds to 0V.

[0078] For example, when the first ADC 1101 samples, the target signal 310 is approximately 0.9V, causing the first quantization output QA1 to remain at 0.9V. Accordingly, the first correction circuit 130 calculates an offset correction amount for the first quantization output QA1 corresponding to 0.9V, so that the third quantization output QC1 (i.e., the corrected first quantization output QA1) corresponds to 0V.

[0079] Data recovery circuit 140 can recover (or serve as) the first quantized outputs QA0-QA3 that have been incorrectly corrected using the fourth quantization output QD of the second ADC 120 to generate output data DO0-DO3. Output circuit 150 is used to generate a digital output signal SOUT based on the third quantization outputs QC0-QC3 and the output data DO0-DO3. In one embodiment, output circuit 150 is used to add the output data DO0-DO3 to the third quantization outputs QC0-QC3 respectively. For example, the combination of the third quantization output QC0 and the output data DO0 corresponds to the sampling result of the first ADC 1100, the combination of the third quantization output QC1 and the output data DO1 corresponds to the sampling result of the first ADC 1101, and so on. Output circuit 150 can then perform a data combination operation to generate an output signal SOUT having a system sampling frequency fs. In some embodiments, output circuit 150 can be implemented by a multiplexer circuit, but this disclosure is not limited thereto.

[0080] The following explains the principle that the fourth quantization output QD can be used to recover the first quantization outputs QA0 to QA3. By setting the first sampling frequency to (N+1) / N times the second sampling frequency of the second ADC 120, the second ADC 120 samples sequentially and substantially at the same time as the first ADCs 1100 to 1103, thereby enabling the second ADC 120 to obtain the sampling results of the first ADCs 1100 to 1103. For example, as... Figure 3 As shown, the first ADC 1100 and the second ADC 120 simultaneously sample the target signal 310 at sampling time TP1. Therefore, the fourth quantization output QD at sampling time TP1 can be used to recover (or serve as) the first quantization output QA0 at sampling time TP1. Similarly, the first ADC 1101 and the second ADC 120 simultaneously sample the target signal 310 at sampling time TP6. Therefore, the fourth quantization output QD at sampling time TP6 can be used to recover (or serve as) the first quantization output QA1 at sampling time TP6, and so on. In some embodiments where the first ADC has N levels, in two consecutive samples of the second ADC 120, the second ADC 120 will first sample substantially simultaneously with the (K-1)th level first ADC in the N-level first ADC, and then sample substantially simultaneously with the Kth level first ADC, where K is a positive integer less than or equal to N.

[0081] In some embodiments, the input signal SIN also includes other crosstalk signals (e.g., crosstalk signal 320) at frequencies different from the target signal 310. Generally, these crosstalk signals are AC signals, so the effect of the crosstalk signals on the fourth quantization output QD can be eliminated by a series averaging filter, for example... Figure 5The first averaging filter 5300-5303 and the second averaging filter 5400-5403 are used in the ADC. For example, the fourth quantization output QD at sampling time TP1 can be processed by the averaging filter before being used to recover the first quantization output QA0. Similarly, the fourth quantization output QD at sampling time TP6 can be processed by another averaging filter before being used to recover the first quantization output QA1. However, when the frequency of the crosstalk signal 320 is 100MHz (i.e., when the first ADC has N stages and the frequency of the crosstalk signal 320 is fs×j / [N×(N+1)], where j is a positive integer), the effect of the crosstalk signal 320 on the fourth quantization output QD is somewhat similar to the effect caused by a DC signal, and therefore the crosstalk signal 320 cannot be removed from the fourth quantization output QD by the averaging filter.

[0082] For example, such as Figure 3 As shown, when the second ADC 120 samples at sampling time TP1 and sampling time TP21 to recover the first quantization output QA0, the crosstalk signal 320 is approximately 0.3V. Therefore, even if the two fourth quantization outputs QD are averaged, the crosstalk signal 320 will still be completely retained and not removed.

[0083] Data recovery circuit 140 can be used to solve the above-mentioned problems. Data recovery circuit 140 includes selection circuit 142 and processing circuit 144. Data recovery circuit 140 is used (e.g., through selection circuit 142) to output one of the corresponding third quantization outputs QC0 to QC3 at the second sampling frequency as the fifth quantization output QE. Therefore, the fifth quantization output QE can be understood as the quantization output obtained by sampling the input signal SIN at the second sampling frequency, and includes components related to the crosstalk signal 320 (e.g., 100MHz) but does not include components related to the target signal 310 (e.g., 500MHz), because the components related to the target signal 310 have been removed by the first correction circuit 130. Data recovery circuit 140 is also used to subtract the fifth quantization output QE from the fourth quantization output QD to remove the components related to the crosstalk signal 320 (e.g., 100MHz) in the fourth quantization output QD and retain the components related to the target signal 310 (e.g., 500MHz), thereby generating multiple output data DO0 to DO3. In some embodiments, the output data DO0 to DO3 correspond to the sampling results of the four channels of the first ADC 1100 to 1103 for the target signal 310 (e.g., 500MHz).

[0084] The following will be coordinated Figure 4 and Figure 5 Further explanation of the operation of selection circuit 142 and processing circuit 144. Please refer to [link / reference]. Figure 4 , Figure 4This is a schematic diagram of the operation of the selection circuit 142 according to an embodiment of this disclosure. As previously described, the interval between adjacent sampling times TP1 to TP21 is one system sampling period TS. The selection circuit 142 is used to receive the third quantization outputs QC0 to QC3, and to output one of the third quantization outputs QC0 to QC3 as the fifth quantization output QE every 4 system sampling periods TS (i.e., every N system sampling periods TS when the first ADC has N levels). Figure 4 As shown, the selection circuit 142 will sequentially output the third quantization output QC0 at sampling time TP1, the third quantization output QC1 at sampling time TP6, the third quantization output QC2 at sampling time TP11, and the third quantization output QC3 at sampling time TP16.

[0085] In other words, the sampling time of the current third quantized output of the selection circuit 142 is 5 system sampling periods TS compared to the sampling time of the previous third quantized output of the selection circuit 142 (that is, when the first ADC has N levels, the interval is N+1 system sampling periods TS). For example, as Figure 4 As shown, among the multiple third quantization outputs that form the fifth quantization output QE, the third quantization output QC1 (sampling time TP6) differs from the previous third quantization output QC0 (sampling time TP1) by 5 system sampling periods TS.

[0086] In one embodiment, the selection circuit 142 may include a latch circuit or random access memory to store four third quantization outputs QC0 to QC3 in every four system sampling periods TS. The selection circuit 142 may also include a multiplexer for outputting one of the four third quantization outputs QC0 to QC3.

[0087] Please refer to this again. Figure 1 In some embodiments, the data recovery circuit 140 further includes a second correction circuit 146. The second correction circuit 146 is coupled to the selection circuit 142 and is used to correct the offset of the third quantization output of the selection circuit 142 to generate a fifth quantization output QE. The correction principle of the second correction circuit 146 is similar to that of the aforementioned first sub-correction circuits 1320-1323 or second sub-correction circuit 134, and will not be repeated here for the sake of simplicity.

[0088] In some embodiments, the input signal SIN includes a crosstalk signal having a second sampling frequency (e.g., a 400MHz crosstalk signal, not shown in the figure). Figure 3 ).Depend on Figure 4It can be understood that the output of the selection circuit 142 is a quantized output obtained by sampling the input signal SIN at the second sampling frequency. This causes the crosstalk signal at the second sampling frequency to create a fixed DC component in the output of the selection circuit 142. Therefore, the second correction circuit 146 can be used to eliminate the crosstalk signal component related to the second sampling frequency from the output of the selection circuit 142 through averaging. In some embodiments, if the input signal SIN does not contain the crosstalk signal at the second sampling frequency, the second correction circuit 146 can be omitted.

[0089] Please refer to the following: Figure 5 , Figure 5 This is a simplified functional block diagram of a processing circuit 144 according to an embodiment of this disclosure. The processing circuit 144 includes a first demultiplexer 510, a second demultiplexer 520, a plurality of first averaging filters 5300-5303, a plurality of second averaging filters 5300-5303, and a plurality of first arithmetic circuits 5500-5503.

[0090] The first demultiplexer 510 is used to receive the fifth quantization output QE and to sequentially distribute the data in the fifth quantization output QE to multiple output terminals X0 to X3 of the first demultiplexer 510 according to the sampling time. For example, the first demultiplexer 510 can use output terminals X0 to X3 to output respectively. Figure 4 The third quantization output QC0 at sampling time TP1, QC1 at sampling time TP6, QC2 at sampling time TP11, and QC3 at sampling time TP16, and so on.

[0091] The first averaging filters 5300 to 5303 are respectively coupled to the output terminals X0 to X3, and are used to average the output signals of the output terminals X0 to X3 respectively to generate multiple first data DA0 to DA3. The first averaging filters 5300 to 5303 are used to eliminate crosstalk signals of other frequencies not mentioned above from the output signals of the output terminals X0 to X3.

[0092] The second demultiplexer 520 is used to receive the fourth quantization output QD and to sequentially distribute the data in the fourth quantization output QE to multiple output terminals Y0 to Y3 of the second demultiplexer 520 according to the sampling time. For example, please refer to [reference needed]. Figure 3 and Figure 5 The second demultiplexer 520 can use output terminals Y0 to Y3 to output the fourth quantization output QD of sampling times TP1, TP6, TP11 and TP16 respectively, and so on.

[0093] The second averaging filters 5400-5403 are respectively coupled to the output terminals Y0-Y3 and are used to average the output signals of the output terminals Y0-Y3 to generate multiple second data DB0-DB3. The second averaging filters 5400-5403 are used to eliminate crosstalk signals of other frequencies not mentioned above from the output signals of the output terminals Y0-Y3.

[0094] As described above, the sampling times (e.g., sampling times TP1, TP6, TP11, and TP16) corresponding to the first data DA0 to DA3 are substantially the same as the sampling times corresponding to the second data DB0 to DB3. In some embodiments, the first averaging filters 5300 to 5303 and the second averaging filters 5400 to 5403 can be implemented by moving average filters. In some embodiments, if the input signal SIN does not contain crosstalk signals of the other frequencies mentioned above, the first averaging filters 5300 to 5303 and the second averaging filters 5400 to 5403 can be omitted, and the output terminals X0 to X3 of the first demultiplexer 510 can directly output the first data DA0 to DA3, and the output terminals Y0 to Y3 of the second demultiplexer 520 can directly output the second data DB0 to DB3.

[0095] In summary, the information contained in the first data DA0 to DA3 corresponds to the crosstalk signal 320. The information contained in the second data DB0 to DB3 corresponds to the target signal 310 and the crosstalk signal 320. The frequency of the target signal 310 is 500MHz (or fs×i / N), and the frequency of the crosstalk signal 320 is 100MHz (or fs×j / [N×(N+1)]).

[0096] The first operational circuits 5500 to 5503 are used to subtract the first data DA0 to DA3 from the second data DB0 to DB3 respectively, so as to generate output data DO0 to DO3 respectively. Therefore, the information in the output data DO0 to DO3 will only correspond to the target signal 310.

[0097] Figure 6 This is a simplified functional block diagram of a first sub-correction circuit 1320 according to an embodiment of this disclosure. The first sub-correction circuit 1320 includes a third averaging filter 610 and a second operational circuit 620. The third averaging filter 610 is used to average the first quantization output QA0. The second operational circuit 620 is used to subtract the output of the third averaging filter 610 (i.e., the averaged first quantization output QA0, or the offset correction amount of the first quantization output QA0) from the first quantization output QA0 to generate a third quantization output QC0. In this embodiment, the components, connections, and operations of the other first sub-correction circuits 1321-1323 and the second sub-correction circuit 134 are all applicable to the above-described... Figure 6The description of the first sub-correction circuit 1320 is omitted here for the sake of brevity.

[0098] In summary, during offset correction, the analog-to-digital converter 100 can guarantee the generation of the correct output signal SOUT without losing sampling results when the frequency of the input signal SIN is an integer multiple of the first sampling frequency of the first ADCs 1100-1103. It is worth noting that the analog-to-digital converter 100 is also applicable when the frequency of the target signal 310 is not an integer multiple of the first sampling frequency. In this case, the first correction circuit 130 will not incorrectly correct the first quantization outputs QA0-QA3, causing the fourth quantization output QD and the fifth quantization output QE to be essentially random numbers, whose values ​​will be... Figure 5 The first averaging filter 5300–5303 and the second averaging filter 5400–5403 are eliminated. Therefore, Figure 5 The first data DA0~DA3 and the second data DB0~DB3 can both correspond to 0V, so that the output data DO0~DO3 correspond to 0V without affecting the output signal SOUT. The output circuit 150 is equivalent to using only the third quantization output QC0~QC3 to generate the correct output signal SOUT.

[0099] Figure 7 This is a flowchart of an offset correction method 700 according to an embodiment of this disclosure. The analog-to-digital converter 100 in the foregoing embodiments can be used to perform the offset correction method 700. It should be understood that any method described herein may include more or fewer steps than shown in the flowchart, and the steps in the method may be performed in any suitable order.

[0100] In step S710, the first ADCs 1100 to 1103 convert the input signal SIN into the first quantization outputs QA0 to QA3 in a time-interleaved manner according to the first sampling frequency.

[0101] In step S720, the second ADC converts the input signal SIN into a second quantization output QB according to the second sampling frequency, wherein the first sampling frequency is (N+1) / N times the second sampling frequency.

[0102] In step S730, the first correction circuit 130 corrects the offset of the first quantization outputs QA0 to QA3 to generate the third quantization outputs QC0 to QC3, and corrects the offset of the second quantization output QB to generate the fourth quantization output QD.

[0103] In step S740, the data recovery circuit 140 outputs one of the third quantization outputs QC0 to QC3 at the second sampling frequency as the fifth quantization output QE.

[0104] In step S750, the data recovery circuit 140 subtracts the fifth quantization output QE from the fourth quantization output QD to generate output data DO0 to DO3.

[0105] In step S760, the output circuit 150 generates an output signal SOUT based on the third quantization outputs QC0 to QC3 and the output data DO0 to DO3.

[0106] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element through other elements or connection means.

[0107] The use of "and / or" herein includes any combination of one or more of the listed items. Furthermore, unless otherwise specified in the specification, any singular term also includes the plural meaning.

[0108] The above are merely preferred embodiments of this disclosure. Various modifications and equivalent changes can be made to the structure of this disclosure without departing from its scope or spirit. In summary, all modifications and equivalent changes made to this disclosure within the scope of the appended claims are within the scope of this disclosure.

Claims

1. An analog-to-digital converter, characterized in that, Include: An N-stage first ADC (analog-to-digital converter) has a first sampling frequency for converting an input signal into a multi-stage first quantization output in a time-interleaved manner, where N is a positive integer greater than or equal to 2; A second ADC having a second sampling frequency for converting the input signal into a second quantized output, wherein the first sampling frequency is (N+1) / N times the second sampling frequency; A first correction circuit is used to correct the offset between the multi-stage first quantization output and the second quantization output, so as to generate multi-stage third quantization output and a fourth quantization output respectively; A data recovery circuit, coupled to the first correction circuit, is used to output one of the multiple levels of third quantization outputs at the second sampling frequency as a fifth quantization output, and to subtract the fifth quantization output from the fourth quantization output to generate multiple output data; and An output circuit is used to add the multiple output data to the multi-stage third quantization output to generate an output signal.

2. The analog-to-digital converter according to claim 1, characterized in that, In two consecutive samplings of the second ADC, the second ADC is sampled simultaneously with the (K-1)th level first ADC in the N-level first ADC, and then sampled simultaneously with the Kth level first ADC in the N-level first ADC, where K is a positive integer less than or equal to N.

3. The analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter operates as a time-interleaved analog-to-digital converter and has a system sampling period, wherein the data recovery circuit includes: A selection circuit is used to receive the multi-stage third quantization output and to output one of the multi-stage third quantization outputs as the fifth quantization output every N system sampling cycles. The sampling time of the current third quantized output of the selection circuit is (N+1) system sampling cycles, which is the time interval between the sampling time of the previous third quantized output of the selection circuit.

4. The analog-to-digital converter according to claim 3, characterized in that, The data recovery circuit also includes: A second correction circuit, coupled to the selection circuit, is used to correct the offset of one of the multi-stage third quantization outputs to generate the fifth quantization output.

5. The analog-to-digital converter according to claim 3, characterized in that, The data recovery circuit also includes: A second correction circuit, coupled to the selection circuit, is used to eliminate from one of the multi-stage third quantization outputs a component related to a crosstalk signal, wherein the frequency of the crosstalk signal is substantially the same as the second sampling frequency.

6. The analog-to-digital converter according to claim 1, characterized in that, The data recovery circuit includes a processing circuit, which includes: A first demultiplexer is used to distribute the fifth quantization output into multiple first data; A second demultiplexer is used to distribute the fourth quantization output into multiple second data; as well as Multiple first arithmetic circuits are used to subtract the multiple first data from the multiple second data respectively to generate the multiple output data.

7. The analog-to-digital converter according to claim 6, characterized in that, The sampling times corresponding to the multiple first data points are substantially the same as the sampling times corresponding to the multiple second data points.

8. The analog-to-digital converter according to claim 6, characterized in that, The processing circuit also includes: Multiple first averaging filters are used to respectively average multiple outputs of the first demultiplexer to generate the multiple first data; and Multiple second averaging filters are used to respectively average multiple outputs of the second demultiplexer to generate the multiple second data.

9. The analog-to-digital converter according to claim 1, characterized in that, The first correction circuit includes: Multiple first sub-correction circuits are respectively coupled to the N-stage first ADC, wherein each first sub-correction circuit includes: A third averaging filter is used to average one of the corresponding outputs of the first quantization stage; and A second operational circuit is used to subtract the output of the third averaging filter from the corresponding one of the multi-stage first quantization outputs to generate the corresponding one of the multi-stage third quantization outputs. as well as A second sub-correction circuit, coupled to the second ADC, and comprising: A fourth averaging filter is used to average the second quantized output; and A third operational circuit is used to subtract the output of the fourth averaging filter from the second quantization output to generate the fourth quantization output.

10. An offset correction method, applicable to an analog-to-digital converter, characterized in that, The analog-to-digital converter includes an N-stage first ADC (analog-to-digital converter) and a second ADC, and the method includes: In a time-interleaved manner, the N-stage first ADC converts an input signal into a multi-stage first quantization output based on a first sampling frequency, where N is a positive integer greater than or equal to 2; The input signal is converted into a second quantized output using the second ADC according to a second sampling frequency, wherein the first sampling frequency is (N+1) / N times the second sampling frequency; The offset between the first and second quantization outputs of the multi-level quantization is corrected to generate a third and a fourth quantization output, respectively. One of the multi-level third quantization outputs is output at the second sampling frequency as a fifth quantization output; Subtract the fifth quantization output from the fourth quantization output to generate multiple output data; as well as The output signal is generated by adding the multiple output data to the third quantization output of the multi-level system.

11. The offset correction method according to claim 10, characterized in that, In two consecutive samplings of the second ADC, the second ADC is sampled simultaneously with the (K-1)th level first ADC in the N-level first ADC, and then sampled simultaneously with the Kth level first ADC in the N-level first ADC, where K is a positive integer less than or equal to N.

12. The offset correction method according to claim 10, characterized in that, The analog-to-digital converter operates as a time-interleaved analog-to-digital converter and has a system sampling period, wherein one of the multiple levels of third quantization outputs output at the second sampling frequency is used as the fifth quantization output, which includes: Every N sampling cycles of the system, one of the multi-level third quantization outputs is output as the fifth quantization output. The sampling time of the current third quantized output is (N+1) system sampling cycles, which is the time interval between the sampling time of the current third quantized output and the sampling time of the previous third quantized output.

13. The offset correction method according to claim 12, characterized in that, Every N system sampling cycles, one of the multi-level third quantization outputs is output as the fifth quantization output, which includes: The offset of one of the multi-level third quantization outputs is corrected to produce the fifth quantization output.

14. The offset correction method according to claim 12, characterized in that, Every N system sampling cycles, one of the multi-level third quantization outputs is output as the fifth quantization output, which includes: The component relating to a crosstalk signal is removed from one of the outputs of the multi-level third quantization, wherein the frequency of the crosstalk signal is substantially the same as the second sampling frequency.

15. The offset correction method according to claim 10, characterized in that, Subtracting the fifth quantization output from the fourth quantization output to produce the plurality of output data includes: The fifth quantization output is allocated to multiple first data; The fourth quantization output is allocated to multiple second data; and Subtract the first data from each of the second data to obtain the output data.

16. The offset correction method according to claim 15, characterized in that, The sampling times corresponding to the multiple first data points are substantially the same as the sampling times corresponding to the multiple second data points.

17. The offset correction method according to claim 15, characterized in that, The multiple signals generated by the fifth quantization output are averaged separately to form the multiple first data, and the multiple signals generated by the fourth quantization output are averaged separately to form the multiple second data.

18. The offset correction method according to claim 10, characterized in that, Correcting the offset between the first quantization output and the second quantization output of the multi-level process includes: The first quantization outputs of each multi-level are averaged to produce the averaged first quantization outputs of the multi-level; The averaged multi-level first quantization output is subtracted from the multi-level first quantization output to generate the multi-level third quantization output; The second quantized output is averaged to produce an averaged second quantized output; as well as The second quantized output is subtracted from the averaged second quantized output to produce the fourth quantized output.

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