Semiconductor structure and method of fabricating the same
By forming a thinner first insulating layer and a thinner second insulating layer on the first trench sidewall of the semiconductor structure, the problem of low semiconductor structure yield is solved, the efficiency of siliconization reaction and word line fabrication space are improved, and the performance of the semiconductor structure is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-03-31
- Publication Date
- 2026-06-12
AI Technical Summary
The low yield of semiconductor structures is mainly due to the thick first insulating layer formed on the sidewall of the first trench on the substrate, which makes it difficult to remove the insulating layer at the bottom of the trench, making it difficult to carry out the silicide reaction and thus difficult to fabricate buried bit lines.
A thin first insulating layer and a second insulating layer are sequentially formed on the sidewall of the first trench. The exposed substrate undergoes a siliconization reaction, and the sum of the thicknesses of the first insulating layer and the second insulating layer is made equal to a target value to facilitate the formation of word lines.
This improves the performance and yield of semiconductor structures by increasing the exposed substrate area during the silicide reaction, making the silicided substrates interconnected and providing sufficient space for word line fabrication.
Smart Images
Figure CN116940108B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] With the development of semiconductor technology, the application of semiconductor structures is becoming more and more widespread. Semiconductor memory, especially dynamic random access memory (DRAM), is widely used in various electronic devices due to its high storage density and fast read and write speed.
[0003] Dynamic random access memory (DRAM) typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL) of the DRAM, and the voltage on the word line controls the transistor's on and off states. One of the transistor's source and drain terminals is electrically connected to the bit line (BL), and the other of the source and drain terminals is electrically connected to the capacitor. Data information is stored or output through the bit line.
[0004] To increase memory storage density, dynamic random access memory (DRAM) uses vertical transistors with a gate all around (GAA) structure, and the bit lines in DRAM are typically buried bit lines. However, the yield of semiconductor structures is relatively low. Summary of the Invention
[0005] In view of the above problems, embodiments of this application provide a semiconductor structure and a method for fabricating the same, which reduces the difficulty of forming embedded bit lines and improves the yield of semiconductor structures.
[0006] According to some embodiments, a first aspect of this application provides a method for fabricating a semiconductor structure, comprising:
[0007] Multiple spaced first grooves are formed in the matrix and extend along a first direction;
[0008] A first insulating layer is formed on the sidewall of the first trench, the thickness of the first insulating layer is less than the target value, and the first insulating layer located in the first trench surrounds the second trench.
[0009] The substrate exposed in the second trench undergoes a silicide reaction;
[0010] A second insulating layer is formed on the sidewall of the second trench, and the second insulating layer located in the second trench surrounds a third trench, and the sum of the thicknesses of the first insulating layer and the second insulating layer is equal to the target value;
[0011] An isolation layer is formed within the third trench, and the isolation layer fills the third trench.
[0012] In some possible embodiments, a first insulating layer is formed on the sidewall of the first trench, the thickness of the first insulating layer being less than a target value, and the first insulating layer located within the first trench encloses a second trench, comprising:
[0013] An initial first insulating layer is deposited on the sidewalls and bottom wall of the first trench, as well as on the substrate;
[0014] The initial first insulating layer is etched, leaving the initial first insulating layer located on the sidewall of the first trench, and the left initial first insulating layer forms the first insulating layer.
[0015] In some possible embodiments, a second insulating layer is formed on the sidewall of the second trench, and the second insulating layer located within the second trench encloses a third trench, wherein the sum of the thicknesses of the first insulating layer and the second insulating layer is equal to a target value, including:
[0016] An initial second insulating layer is deposited on the sidewalls and bottom wall of the second trench, the substrate, and the first insulating layer;
[0017] The initial second insulating layer is etched, leaving the initial second insulating layer located on the sidewall of the second trench, and the left initial second insulating layer forms the second insulating layer.
[0018] In some possible embodiments, the thickness of the first insulating layer is less than the thickness of the second insulating layer, and the target value is 5-20 nm.
[0019] In some possible embodiments, an isolation layer is formed within the third trench, and after the isolation layer fills the third trench, the method further includes:
[0020] The substrate and the isolation layer are planarized.
[0021] In some possible embodiments, before forming a plurality of spaced-apart first trenches extending along a first direction in the substrate, the method further includes:
[0022] A substrate is provided, the substrate comprising a substrate and a third insulating layer, the substrate having a plurality of spaced fourth trenches extending along a second direction, the third insulating layer filling the fourth trenches.
[0023] In some possible embodiments, a substrate is provided, the substrate comprising a substrate and a third insulating layer, the substrate having a plurality of spaced fourth trenches extending along a second direction, the third insulating layer filling the fourth trenches, comprising:
[0024] Provide substrate;
[0025] The substrate is etched to form a plurality of fourth trenches within the substrate, the depth of the fourth trenches being greater than the depth of the first trenches;
[0026] The third insulating layer is deposited in each of the fourth trenches, and the third insulating layer fills the fourth trenches.
[0027] In some possible embodiments, after the third insulating layer is deposited in each of the fourth trenches and the third insulating layer fills the fourth trenches, the method further includes:
[0028] A protective layer is deposited on the substrate, the protective layer covering the substrate and the third insulating layer.
[0029] In some possible embodiments, an isolation layer is formed within the third trench, and after the isolation layer fills the third trench, the method further includes:
[0030] A portion of the first insulating layer, a portion of the second insulating layer, and a portion of the third insulating layer are removed to form a filling space that exposes the substrate.
[0031] Within the filling space, a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer are formed.
[0032] In some possible embodiments, a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling the spaces between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer are formed within the filled space, comprising:
[0033] An initial dielectric layer is formed on the exposed surface of the substrate, and the initial dielectric layer located below the filling space forms the gate dielectric layer, with gaps between the gate dielectric layers;
[0034] The conductive layer is deposited within the filling space, and the conductive layer fills the spaces between the gate dielectric layers and between the gate dielectric layers and the isolation layer;
[0035] The fourth insulating layer is deposited within the remaining filled space.
[0036] In some possible embodiments, an initial dielectric layer is formed on the exposed surface of the substrate, the initial dielectric layer located below the filling space forms the gate dielectric layer, and gaps are present between the gate dielectric layers, including:
[0037] The initial dielectric layer is formed on the exposed surface of the substrate by a thermal oxidation process.
[0038] In some possible embodiments, after forming a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer within the filling space, the method further includes:
[0039] Remove the isolation layer to expose the third trench;
[0040] The opening of the third groove is sealed to create an air gap within the third groove.
[0041] In some possible embodiments, sealing the opening of the third trench to create an air gap within the third trench includes:
[0042] A capping layer is deposited on the substrate, which seals the opening of the third trench to form the air gap.
[0043] In some possible embodiments, removing a portion of the first insulating layer, a portion of the second insulating layer, and a portion of the third insulating layer to form a fill space that exposes the substrate includes:
[0044] Self-aligned etching of the first insulating layer, the second insulating layer and the third insulating layer to the initial depth to form an initial fill space;
[0045] A support layer is formed on the surfaces of the substrate and the isolation layer exposed in the initial fill space, and the support layer fills the initial fill space between the substrate and the isolation layer;
[0046] Using the remaining initial fill space, the first insulating layer, the second insulating layer, and the third insulating layer are etched to a preset depth to form the fill space, which includes the remaining initial fill space.
[0047] The method for fabricating the semiconductor structure provided in this application has at least the following advantages:
[0048] In the semiconductor structure fabrication method provided in this application embodiment, the substrate has a first trench extending along a first direction. A first insulating layer is formed on the sidewall of the first trench. The first insulating layer surrounds a second trench, and the thickness of the first insulating layer is less than a target value. Because the thickness is relatively thin, more substrate is exposed within the second trench. When the substrate exposed within the second trench undergoes a silicide reaction, it facilitates silicide reaction in the substrate located between adjacent second trenches, causing the silicided substrates to connect as a single unit along the second direction, thereby improving the performance of the semiconductor structure. Furthermore, a second insulating layer is formed on the sidewall of the second trench. Word lines are subsequently formed in the regions where the first and second insulating layers are located. The sum of the thicknesses of the first and second insulating layers is equal to the target value, ensuring sufficient fabrication space for the word lines and further improving the performance of the semiconductor structure.
[0049] According to some embodiments, a second aspect of this application provides a semiconductor structure formed by the fabrication method described above, thus having at least the advantage of a high yield rate for semiconductor structures. Attached Figure Description
[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0051] Figure 1 This is a top view of the word lines and bit lines in the semiconductor structure of the embodiments of this application;
[0052] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application;
[0053] Figures 3 to 6 These are schematic diagrams of the substrate cross-sections at points AA, BB, CC, and DD in the embodiments of this application.
[0054] Figures 7 to 10 These are schematic diagrams of the cross-sections at AA, BB, CC, and DD after the fourth trench is formed in the embodiments of this application.
[0055] Figures 11 to 14 These are schematic diagrams of the cross-sections of the substrate at points AA, BB, CC, and DD in the embodiments of this application.
[0056] Figures 15 to 18 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the first trench is formed in the embodiments of this application.
[0057] Figures 19 to 22 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the first insulating layer is formed in the embodiments of this application.
[0058] Figures 23 to 26 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the bit lines are formed in the embodiments of this application.
[0059] Figures 27 to 30 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the second insulating layer is formed in the embodiments of this application.
[0060] Figures 31 to 34 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the isolation layer is formed in the embodiments of this application.
[0061] Figures 35 to 38 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the filling space is formed in the embodiments of this application.
[0062] Figures 39 to 42 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the initial dielectric layer is formed in the embodiments of this application.
[0063] Figures 43 to 46 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the conductive layer is formed in the embodiments of this application.
[0064] Figures 47 to 50 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the fourth insulating layer is formed in the embodiments of this application.
[0065] Figures 51 to 54 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the isolation layer has been removed in the embodiments of this application.
[0066] Figures 55 to 58 These are schematic diagrams of cross-sections at AA, BB, CC, and DD after the capping layer is formed in the embodiments of this application. Detailed Implementation
[0067] The related technology suffers from a low yield rate for semiconductor structures. The inventors discovered that this is because, during the semiconductor structure fabrication process, when forming the first insulating layer on the sidewalls of the first trench of the substrate, the first insulating layer is typically deposited first on the sidewalls and bottom of the first trench, and then etched away at the bottom of the first trench. However, the first insulating layer is relatively thick, enclosing a small area. Furthermore, the perpendicularity of the deposited first insulating layer's outline is poor, making it difficult to remove the first insulating layer at the bottom of the first trench. This results in the first insulating layer still covering the substrate at the bottom of the first trench, making it difficult to perform silicide reaction on this portion of the substrate. Consequently, it is difficult to fabricate buried bit lines, leading to a low yield rate for the semiconductor structure.
[0068] In the semiconductor structure fabrication method provided in this application embodiment, a first insulating layer and a second insulating layer are sequentially formed on the sidewalls of a first trench. After forming the first insulating layer, a silicide reaction is performed on the substrate exposed within the area enclosed by the first insulating layer. Compared to forming the second insulating layer before performing the silicide reaction, forming the first insulating layer before performing the silicide reaction exposes more substrate, allowing the silicided substrates to be interconnected along the second direction, thereby improving the performance of the semiconductor structure. Word lines are subsequently formed in the area containing the first and second insulating layers. The sum of the thicknesses of the first and second insulating layers equals a target value, ensuring sufficient fabrication space for the word lines and further improving the performance of the semiconductor structure.
[0069] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0070] refer to Figure 1 , Figure 1 This is a top view of a semiconductor structure according to an embodiment of this application. The semiconductor structure includes a word line (WL) and a bit line (BL). The word line 2 extends along a first direction, and the bit line 1 extends along a second direction. The second direction and the first direction have an angle between them; for example, the second direction and the first direction can be perpendicular. Specifically, as shown... Figure 1 As shown, bit line 1 is along the vertical direction ( Figure 1 Extending in the Y direction (as shown), line 2 extends along the horizontal direction ( Figure 1 Extending in the X direction (as shown).
[0071] Figure 1There are four different positions: A, B, C, and D. Specifically, the cross-section at position AA is parallel to the extension direction of bit line 1 and located on bit line 1; the cross-section at position BB is parallel to the extension direction of bit line 1 and located between adjacent bit lines 1; the cross-section at position CC is parallel to the extension direction of word line 2 and located on word line 2; and the cross-section at position DD is parallel to the extension direction of word line 2 and located between adjacent word lines 2.
[0072] refer to Figure 2 , Figure 2 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this application. The method includes the following steps:
[0073] Step S10: Form multiple spaced first grooves in the substrate that extend along a first direction.
[0074] refer to Figures 3 to 10 In some possible embodiments of this application, before forming a plurality of spaced first trenches 21 extending along a first direction in the substrate 10 (step S10), the method further includes: providing a substrate 10, the substrate 10 including a substrate 11 and a third insulating layer 13, the substrate 11 having a plurality of spaced fourth trenches 12 extending along a second direction, the third insulating layer 13 filling the fourth trenches 12.
[0075] Specifically, a substrate 10 is provided, which includes a substrate 11 and a third insulating layer 13. The substrate 11 has a plurality of fourth trenches 12 spaced apart and extending along a second direction. The third insulating layer 13 fills the fourth trenches 12. The method may include the following steps:
[0076] Substrate 11 is provided.
[0077] The substrate 11 is etched to form multiple fourth trenches 12 within the substrate 11, the depth of the fourth trenches 12 being greater than the depth of the first trenches 21. For example... Figures 3 to 10 As shown, a portion of the substrate 11 is removed to form multiple fourth trenches 12 within the substrate 11. These fourth trenches 12 are spaced apart and extend along a second direction, serving to isolate bit lines 1. Exemplarily, these multiple fourth trenches 12 are formed using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process to increase the density of the fourth trenches 12 and ensure the aspect ratio of the fourth trenches 12.
[0078] Among them, reference Figures 15 to 18The depth of the fourth trench 12 is greater than the depth of the first trench 21, and the width of the fourth trench 12 can be the same as the width of the first trench 21. Here, depth refers to the distance between the bottom of the trench and the top surface of the substrate 11, and width refers to the distance between two opposite sidewalls; that is, the bottom of the fourth trench 12 can be located below the bottom of the first trench 21. Multiple fourth trenches 12 and multiple first trenches 21 are connected, dividing a portion of the substrate 11 into multiple columnar structures.
[0079] A third insulating layer 13 is deposited in each fourth trench 12, and the third insulating layer 13 fills the fourth trench 12. For example... Figures 7 to 14 As shown, the top surface of the third insulating layer 13 is flush with the top surface of the substrate 11 to fill the third trench 25.
[0080] refer to Figures 11 to 14 The substrate 10 includes a substrate 11 and a third insulating layer 13. The substrate 11 has a plurality of fourth trenches 12 spaced apart and extending in the second direction, and the third insulating layer 13 is filled within the fourth trenches 12. The substrate 11 can be a semiconductor substrate, such as a silicon substrate, germanium substrate, silicon carbide (SiC) substrate, silicon germanide (SiGe) substrate, germanium on insulator (GOI) substrate, or silicon on insulator (SOI) substrate, etc.
[0081] The third insulating layer 13 fills the fourth trench 12, such as Figures 11 to 14 As shown, the top surface of the third insulating layer 13 is flush with the top surface of the substrate 11, so that the top surface of the third insulating layer 13 and the top surface of the substrate 11 form a flat surface, which facilitates the formation of other structures on this surface. The material of the third insulating layer 13 can be an oxide, such as silicon oxide.
[0082] In some possible examples, refer to Figures 15 to 18 The substrate 10 also includes a protective layer 14, which covers the substrate 11 and the third insulating layer 13. This arrangement prevents the substrate 11 from being exposed, thereby avoiding contamination of the top surface of the substrate 11 during subsequent silaneization reactions and ensuring its performance.
[0083] Preferably, the material of the protective layer 14 can be the same as that of the third insulating layer 13. This arrangement allows the protective layer 14 and the third insulating layer 13 to be formed simultaneously, simplifying the semiconductor structure fabrication process. Specifically, a third insulating material is deposited in the fourth trench 12 and on the substrate 11, filling the fourth trench 12 and covering the substrate 11. A planarization process is then used to remove a portion of the third insulating material from the substrate 11, leaving the remaining material flush with the surface of the substrate 11. At this point, the third insulating material within the fourth trench 12 forms the third insulating layer 13, and the third insulating material on the substrate 11 forms the protective layer 14. Of course, the formation of the protective layer 14 is not limited and can be achieved through other methods. For example, the protective layer 14 can be deposited on the substrate 11 and the third insulating layer 13 after the third insulating layer 13 has been formed.
[0084] The aforementioned deposition can be chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc.; the aforementioned planarization process can be chemical mechanical polishing (CMP).
[0085] A first groove 21 is formed in the substrate 10 and extends along a first direction, that is, the extension direction of the first groove 21 is the same as the extension direction of the letter line 2. (Reference) Figures 15 to 18 The depth of the first trench 21 is lower than the depth of the fourth trench 12, that is, part of the bottom of the first trench 21 is located in the substrate 11 and part of the bottom is located in the third insulating layer 13.
[0086] In this configuration, the fourth trench 12 extends along the second direction, dividing the upper portion of the substrate 11 into multiple strip structures. The first trench 21 extends along the first direction, dividing the upper portion of each strip structure into multiple pillar structures, forming an array of active pillars. These active pillars are used to form the source, drain, and channel regions of the transistor, which are arranged vertically. In the lower portion of each strip structure, bit lines 1 are subsequently formed in each remaining strip structure to electrically connect to one of the source and drain stages of the transistor. A third insulating layer 13 fills the spaces between adjacent strip structures, further ensuring insulation between adjacent bit lines 1.
[0087] Step S20: A first insulating layer is formed on the sidewall of the first trench. The thickness of the first insulating layer is less than the target value. The first insulating layer located in the first trench forms a second trench.
[0088] refer to Figures 15 to 22The first insulating layer 22 covers the sidewalls of the first trench 21 to prevent silicide reaction from occurring on the sidewalls of the first trench 21. The material of the first insulating layer 22 can be an oxide, such as silicon oxide. The thickness of the first insulating layer 22 is less than a target value, which can be 5-20 nm. For example, the thickness of the first insulating layer 22 can be 1-2 nm. The thinner the first insulating layer 22, the less space it occupies in the first trench 21, thus exposing more of the substrate 11 within the second trench 23 enclosed by the first insulating layer 22. In other words, more of the substrate 11 is exposed within the second trench 23 enclosed by the first insulating layer 22. This arrangement facilitates both the fabrication of the first insulating layer 22 and the silicide treatment of the substrate 11 exposed at the bottom of the second trench 23.
[0089] Among some possible implementations, refer to Figures 15 to 22 A first insulating layer 22 is formed on the sidewall of the first trench 21. The thickness of the first insulating layer 22 is less than a target value. The first insulating layer 22 located within the first trench 21 forms a second trench 23, including:
[0090] An initial first insulating layer is deposited on the sidewalls and bottom wall of the first trench 21, and on the substrate 10. The initial first insulating layer covers the sidewalls and bottom wall of the first trench 21, and the substrate 10. In embodiments where the substrate 10 includes a protective layer 14, the initial first insulating layer covers the protective layer 14.
[0091] After depositing the initial first insulating layer, the initial first insulating layer is etched, retaining the initial first insulating layer located on the sidewall of the first trench 21. The retained initial first insulating layer forms the first insulating layer 22. That is, after depositing the initial first insulating layer, the initial first insulating layer is etched back to remove the initial first insulating layer located on the bottom wall of the first trench 21 and on the substrate 10, retaining the initial first insulating layer located on the sidewall of the first trench 21 to form the first insulating layer 22.
[0092] The initial thickness of the first insulating layer can be 1-2 nm. After the formation of the first insulating layer, the thickness of the first insulating layer 22 is 1-2 nm. With this configuration, when the initial first insulating layer is etched back, the etching space of the initial first insulating layer located on the bottom wall of the first trench 21 is relatively large, which can ensure that this part of the initial first insulating layer can be removed to expose the substrate 11, so that the substrate 11 can be processed subsequently.
[0093] Furthermore, the initial first insulating layer is relatively thin, and the initial first insulating layer located on the bottom wall of the first trench 21 is easy to remove. The depth of the first trench 21 can be made deeper, that is, the depth-to-width ratio of the first trench 21 is increased, and the height of the substrate 11 between adjacent first trenches 21 is increased. When the source region, drain region and channel region are subsequently formed in this part of the substrate 11, the end height of the source / drain region is increased, reducing band-to-band tunneling (BTBT) and gate-induced drain leakage current (GIDL).
[0094] Step S30: Perform a siliconization reaction on the substrate exposed in the second trench.
[0095] refer to Figures 23 to 26 A silicide reaction is performed on the substrate 11 exposed within the second trench 23 to form a metal silicide within the substrate 11. The metal silicides are connected along a second direction to form a bit line 1. The metal silicide can be titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide, etc. Specifically, a metal layer is deposited within the second trench 23, and then the metal layer is annealed to allow the metal within the metal layer to react with the substrate 11 (e.g., silicon) to form a metal silicide. Excess metal layer is then removed.
[0096] Step S40: A second insulating layer is formed on the sidewall of the second trench. The second insulating layer located in the second trench surrounds the third trench. The sum of the thicknesses of the first insulating layer and the second insulating layer is equal to the target value.
[0097] refer to Figures 23 to 30 The second insulating layer 24 covers the sidewall of the second trench 23, forming a third trench 25. The space occupied by the second insulating layer 24 and the first insulating layer 22 is subsequently used to form the word line 2. The sum of the thicknesses of the first insulating layer 22 and the second insulating layer 24 equals a target value, which can be 5-20 nm. This configuration, by increasing the target value, allows for a larger fabrication space for the word line 2, facilitating its formation; it also allows for a smaller width of the third trench 25, facilitating the subsequent air gap 70 (reference). Figure 47 The formation of ).
[0098] like Figures 27 to 30As shown, the thickness of the first insulating layer 22 can be less than the thickness of the second insulating layer 24. That is, a thinner first insulating layer 22 is first formed on the sidewall of the first trench 21, and then a thicker second insulating layer 24 is formed on the side surface of the first insulating layer 22. The material of the second insulating layer 24 can be an oxide, such as silicon oxide. Preferably, the material of the second insulating layer 24 is the same as that of the first insulating layer 22. On the one hand, this allows the second insulating layer 24 and the first insulating layer 22 to be integrated, avoiding interlayer separation; on the other hand, it allows the second insulating layer 24 and the first insulating layer 22 to be removed simultaneously, facilitating subsequent fabrication.
[0099] In some possible embodiments, a second insulating layer 24 is formed on the sidewall of the second trench 23, and the second insulating layer 24 located within the second trench 23 surrounds a third trench 25. The sum of the thicknesses of the first insulating layer 22 and the second insulating layer 24 is equal to a target value, including:
[0100] An initial second insulating layer is deposited on the sidewalls and bottom wall of the second trench 23, the substrate 10, and the first insulating layer 22. The initial second insulating layer covers the sidewalls and bottom wall of the second trench 23, the substrate 10, and the first insulating layer 22. In embodiments where the substrate 10 includes a protective layer 14, the initial second insulating layer covers the protective layer 14.
[0101] The initial second insulating layer is etched, retaining the initial second insulating layer located on the sidewalls of the second trench 23, forming the second insulating layer 24. After depositing the initial second insulating layer 24, the initial second insulating layer is etched back to remove the initial second insulating layer located on the bottom wall of the second trench 23, the first insulating layer 22, and the substrate 10, retaining the initial second insulating layer 24 located on the sidewalls of the second trench 23 to form the second insulating layer 24. Figures 19 to 30 As shown, a first insulating layer 22 and a second insulating layer 24 are sequentially formed on the sidewall of the first trench 21.
[0102] Step S50: An isolation layer is formed in the third trench, and the isolation layer fills the third trench.
[0103] refer to Figures 27 to 34 An isolation layer 30 is deposited within the third trench 25, filling the trench 25. The isolation layer 30 isolates the word lines 2, ensuring insulation between adjacent word lines 2. The second insulating layer 24 has a higher selectivity than the isolation layer 30, reducing damage to the isolation layer 30 during etching. When the second insulating layer 24 is made of oxide, the isolation layer 30 can be made of silicon nitride or silicon oxynitride, which are relatively hard materials.
[0104] In some possible embodiments, an isolation layer 30 is formed within the third trench 25. After the isolation layer 30 fills the third trench 25, the process further includes planarizing the substrate 10 and the isolation layer 30. This configuration results in a relatively flat top surface for the substrate 10 and the isolation layer 30. In embodiments where the substrate 10 includes a protective layer 14, the planarization process for the substrate 10 and the isolation layer 30 includes removing the protective layer 14 and the isolation layer 30 from the substrate 11 to expose the substrate 11, facilitating electrical connection of the substrate 11 to other structures.
[0105] In summary, in the semiconductor structure fabrication method provided in this application embodiment, the substrate 10 has a first trench 21 extending along a first direction. A first insulating layer 22 is formed on the sidewall of the first trench 21. The first insulating layer 22 surrounds a second trench 23, and the thickness of the first insulating layer 22 is less than a target value. Because the thickness is relatively thin, more substrate 11 is exposed within the second trench 23. When the substrate 11 exposed within the second trench 23 undergoes a silicide reaction, the silicided substrate 11 becomes integrally connected along a second direction, thereby improving the performance of the semiconductor structure. Furthermore, a second insulating layer 24 is formed on the sidewall of the second trench 23. Word lines 2 are subsequently formed in the region where the first insulating layer 22 and the second insulating layer 24 are located. The sum of the thicknesses of the first insulating layer 22 and the second insulating layer 24 is equal to the target value, so that the word lines 2 have sufficient fabrication space, further improving the performance of the semiconductor structure.
[0106] Based on the above embodiments, in some possible implementations, after depositing a third insulating layer 13 in each fourth trench 12 and filling the fourth trench 12 with the third insulating layer 13, the method further includes depositing a protective layer 14 on the substrate 11, the protective layer 14 covering the substrate 11 and the third insulating layer 13. The protective layer 14 isolates and protects the substrate 11 to prevent the top surface of the substrate 11 from being exposed, thereby preventing it from undergoing a siliconization reaction.
[0107] Based on the above embodiments, in some other possible implementations, before or after the step of depositing a third insulating layer 13 in each fourth trench 12 and filling the fourth trench 12 with the third insulating layer 13, the method further includes: doping the substrate 11 between adjacent fourth trenches 12 to form a source region, a drain region, and a channel region located between the source and drain regions. Doping can be achieved through processes such as ion implantation or thermal diffusion. The type of doped material (N-type or P-type) is the same for the source and drain regions, while the type of doped material for the channel region is different from that for the source / drain regions.
[0108] refer to Figures 35 to 50In some possible embodiments of this application, after an isolation layer 30 is formed in the third trench 25 and the isolation layer 30 fills the third trench 25 (step S50), the method further includes:
[0109] Step S60: Remove part of the first insulating layer, part of the second insulating layer and part of the third insulating layer to form a filling space, exposing the substrate.
[0110] like Figures 35 to 38 As shown, the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 are etched to form a filling space 40, the depth of which is as shown. Figure 37 As shown in the middle H, it is less than the depth of the first trench 21 to avoid exposing the bit line 1, thereby ensuring that the bit line 1 and the word line 2 formed in the filling space 40 are insulated from each other.
[0111] Preferably, the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 are made of the same material, so that these three insulating layers can be removed simultaneously, simplifying the semiconductor structure fabrication steps. After the filling space 40 is formed, there are multiple filling spaces 40, which are separated by an isolation layer 30. The substrate 11 exposed in each filling space 40 has a columnar structure.
[0112] In some possible implementations, a portion of the first insulating layer 22, a portion of the second insulating layer 24, and a portion of the third insulating layer 13 are removed to form a filling space 40, which exposes the substrate 11, including:
[0113] Self-aligned etching of the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 to an initial depth forms an initial filling space 40. Self-aligned etching means that when etching the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13, no mask is needed. By utilizing the selectivity ratio of the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 to the substrate 11, the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 can be directly etched, simplifying the semiconductor structure fabrication process. After the initial filling space is formed, its depth is defined as the initial depth, which is the distance between the bottom surface of the initial filling space and the top surface of the substrate 11.
[0114] A support layer is formed on the surfaces of the substrate 11 and the isolation layer 30 exposed in the initial fill space, and the support layer completely fills the initial fill space between the substrate 11 and the isolation layer 30. This configuration allows the support layer to support the isolation layer 30, preventing it from collapsing as the depth of the fill space 40 increases. The support layer can be made of the same material as the isolation layer 30, such as silicon nitride, to form a single unit between the support layer and the isolation layer 30. Since the support layer completely fills the initial fill space between the substrate 11 and the isolation layer 30, gaps exist between adjacent columnar substrate 11 structures, leaving some initial fill space remaining to facilitate further etching of the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13.
[0115] Using the remaining initial fill space, the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 are etched to a predetermined depth to form a fill space 40, which includes the remaining initial fill space. For example, etching gas or etching liquid is introduced into the remaining initial fill space to etch the first insulating layer 22, the second insulating layer 24, and the third insulating layer 13 to a predetermined depth. The remaining initial fill space and the newly formed space together form the fill space 40.
[0116] Step S70: Form a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling between the gate dielectric layers and between the gate dielectric layer and the isolation layer, and a fourth insulating layer covering the conductive layer within the filling space.
[0117] refer to Figures 39 to 50 A gate dielectric layer is formed on the substrate 11 within the filling space 40, the gate dielectric layer surrounding and covering the outer peripheral surface of the substrate 11. A conductive layer 52 fills the area enclosed by the gate dielectric layer and the isolation layer 30, serving as a word line 2. A fourth insulating layer 53 covers the conductive layer 52 and the gate dielectric layer, filling the filling space 40.
[0118] The gate dielectric layer can be made of oxides, such as silicon oxide, silicon oxynitride, tantalum oxide, aluminum oxide, hafnium oxide, etc., and the thickness of the gate dielectric layer can be determined according to actual needs. The conductive layer 52 can be made of metals, such as tantalum, tungsten, tantalum nitride, or titanium nitride, etc., and can also be made of polycrystalline silicon or other conductive materials. The fourth insulating layer 53 can be made of oxides, such as silicon oxide.
[0119] In some possible examples, the gate dielectric layer covers all surfaces of each substrate 11 exposed within the fill space 40; that is, the gate dielectric layer covers all outer peripheral surfaces of each substrate 11 within the fill space 40. In other possible examples, the gate dielectric layer covers the outer peripheral surfaces of the channel regions of each substrate 11 exposed within the fill space 40.
[0120] For details, please refer to Figures 39 to 50 The filling space 40 includes a gate dielectric layer covering at least a portion of the substrate 11, a conductive layer 52 filling between the gate dielectric layers and between the gate dielectric layer and the isolation layer 30, and a fourth insulating layer 53 covering the conductive layer 52. This may include:
[0121] An initial dielectric layer 51 is formed on the exposed surface of the substrate 11. The initial dielectric layer 51 located below the filling space 40 forms a gate dielectric layer, and gaps exist between the gate dielectric layers. Figures 39 to 42 As shown, the substrate 11 has a columnar structure with its top and sides exposed, and an initial dielectric layer 51 is formed thereon. The initial dielectric layer 51 located in the lower part of the filling space 40 forms a gate dielectric layer, which may be opposite to at least a portion of the channel region in the columnar structure, and the gate dielectric layers are spaced apart.
[0122] In some possible implementations, an initial dielectric layer 51 is formed on the surface of the exposed substrate 11 via a thermal oxidation process. Specifically, the substrate 11 undergoes a chemical reaction with a gas containing an oxidizing agent at high temperature to form a dense oxide film on the surface of the substrate 11, which serves as the initial dielectric layer 51. The thermal oxidation process can accommodate the requirements of semiconductor structure miniaturization, allowing the size of columnar structures to be reduced to below 5 nm. In other possible implementations, the initial dielectric layer 51 is formed on the surface of the exposed substrate 11 via a deposition process.
[0123] After the initial dielectric layer 51 is formed, a conductive layer 52 is deposited within the filling space 40. The conductive layer 52 fills the spaces between the gate dielectric layers and between the gate dielectric layer and the isolation layer 30. Figures 43 to 46 As shown, a conductive layer 52 is deposited in the filling space 40 where the gate dielectric layer is formed, with the conductive layer 52 opposite to the gate dielectric layer.
[0124] After the conductive layer 52 is formed, a fourth insulating layer 53 is deposited in the remaining filling space 40. For example... Figures 47 to 50 As shown, a fourth insulating layer 53 is formed by a deposition process, and the fourth insulating layer 53 fills the filling space 40. Specifically, the fourth insulating layer 53 is deposited on the remaining filling space 40 and the substrate 11, and the fourth insulating layer 53 on the substrate 11 is removed by a planarization process to expose the substrate 11.
[0125] In this embodiment, a source region, a drain region, and a channel region are formed in the columnar structure. The columnar structure, the gate dielectric layer, and the conductive layer 52 form a vertical gate all around (VGAA) transistor. When occupying the same substrate area 11, the length of the channel region can be increased by increasing the height of the columnar structure, which is conducive to improving the short-channel effect of the transistor and improving the performance of the semiconductor structure.
[0126] refer to Figures 51 to 58 In some possible embodiments of this application, after forming a gate dielectric layer covering at least a portion of the substrate 11, a conductive layer 52 filling between the gate dielectric layers and between the gate dielectric layer and the isolation layer 30, and a fourth insulating layer 53 covering the conductive layer 52 (step S70) within the filling space 40, the method further includes:
[0127] Remove the isolation layer 30 to expose the third trench 25. (As shown) Figures 51 to 54 As shown, the isolation layer 30 is removed using a dry etching or wet etching process to expose the third trench 25. In some possible examples, all of the isolation layer 30 is removed, and the third trench 25 is fully exposed. In other possible examples, the isolation layer 30 is removed to a predetermined depth, and the third trench 25 is partially exposed, in which case the conductive layer 52 is exposed within the third trench 25.
[0128] Seal the opening of the third groove 25 to create an air gap 70 within the third groove 25. For example... Figures 55 to 58 As shown, an air gap 70 is formed at least between adjacent conductive layers 52. By utilizing the characteristic that the dielectric constant of air is approximately 1, the parasitic resistance between adjacent conductive layers 52 can be reduced, thereby improving the performance of the semiconductor structure.
[0129] Specifically, sealing the opening of the third trench 25 to form an air gap 70 within the third trench 25 includes depositing a capping layer 60 on the substrate 10. The capping layer 60 seals the opening of the third trench 25 to form the air gap 70. For example, the capping layer 60 is formed by depositing a material with poor filling capacity (e.g., a nitride) at the opening of the third trench 25, but not deposited or not completely deposited into the third trench 25, thus forming the air gap 70 within the third trench 25. Alternatively, process parameters of the deposition process, such as the deposition rate, are controlled to seal the third trench 25.
[0130] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.
[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Multiple spaced first grooves are formed in the matrix and extend along a first direction; A first insulating layer is formed on the sidewall of the first trench, the thickness of the first insulating layer is less than the target value, and the first insulating layer located in the first trench surrounds the second trench. The substrate exposed in the second trench undergoes a silicide reaction; A second insulating layer is formed on the sidewall of the second trench, and the second insulating layer located in the second trench surrounds a third trench. The sum of the thicknesses of the first insulating layer and the second insulating layer is equal to the target value so that there is enough space to manufacture the letter lines. An isolation layer is formed within the third trench, and the isolation layer completely fills the third trench; The area containing the first and second insulating layers is subsequently used to form word lines.
2. The manufacturing method according to claim 1, characterized in that, A first insulating layer is formed on the sidewall of the first trench, the thickness of the first insulating layer being less than a target value. The first insulating layer located within the first trench encloses a second trench, comprising: An initial first insulating layer is deposited on the sidewalls and bottom wall of the first trench, as well as on the substrate; The initial first insulating layer is etched, leaving the initial first insulating layer located on the sidewall of the first trench, and the left initial first insulating layer forms the first insulating layer.
3. The method according to claim 1, characterized in that, A second insulating layer is formed on the sidewall of the second trench, and the second insulating layer located within the second trench encloses a third trench. The sum of the thicknesses of the first insulating layer and the second insulating layer is equal to a target value, including: An initial second insulating layer is deposited on the sidewalls and bottom wall of the second trench, the substrate, and the first insulating layer; The initial second insulating layer is etched, leaving the initial second insulating layer located on the sidewall of the second trench, and the left initial second insulating layer forms the second insulating layer.
4. The manufacturing method according to claim 1, characterized in that, The thickness of the first insulating layer is less than the thickness of the second insulating layer, and the target value is 5-20 nm.
5. The manufacturing method according to claim 1, characterized in that, An isolation layer is formed within the third trench, and after the isolation layer fills the third trench, it further includes: The substrate and the isolation layer are planarized.
6. The manufacturing method according to any one of claims 1-5, characterized in that, Before forming multiple spaced-apart first trenches extending along a first direction in the matrix, the method further includes: A substrate is provided, the substrate comprising a substrate and a third insulating layer, the substrate having a plurality of spaced fourth trenches extending along a second direction, the third insulating layer filling the fourth trenches.
7. The manufacturing method according to claim 6, characterized in that, A substrate is provided, the substrate comprising a base and a third insulating layer, the base having a plurality of spaced fourth trenches extending along a second direction, the third insulating layer filling the fourth trenches, comprising: Provide substrate; The substrate is etched to form a plurality of fourth trenches within the substrate, the depth of the fourth trenches being greater than the depth of the first trenches; The third insulating layer is deposited in each of the fourth trenches, and the third insulating layer fills the fourth trenches.
8. The manufacturing method according to claim 7, characterized in that, After depositing the third insulating layer in each of the fourth trenches, and after the third insulating layer fills the fourth trenches, the method further includes: A protective layer is deposited on the substrate, the protective layer covering the substrate and the third insulating layer.
9. The manufacturing method according to claim 6, characterized in that, An isolation layer is formed within the third trench, and after the isolation layer fills the third trench, it further includes: A portion of the first insulating layer, a portion of the second insulating layer, and a portion of the third insulating layer are removed to form a filling space that exposes the substrate. Within the filling space, a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer are formed.
10. The manufacturing method according to claim 9, characterized in that, Within the filling space, a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer are formed, comprising: An initial dielectric layer is formed on the exposed surface of the substrate, and the initial dielectric layer located below the filling space forms the gate dielectric layer, with gaps between the gate dielectric layers; The conductive layer is deposited within the filling space, and the conductive layer fills the spaces between the gate dielectric layers and between the gate dielectric layers and the isolation layer; The fourth insulating layer is deposited within the remaining filled space.
11. The manufacturing method according to claim 10, characterized in that, An initial dielectric layer is formed on the exposed surface of the substrate. The initial dielectric layer located below the filling space forms the gate dielectric layer, and there are gaps between the gate dielectric layers. The initial dielectric layer is formed on the exposed surface of the substrate by a thermal oxidation process.
12. The manufacturing method according to claim 9, characterized in that, After forming a gate dielectric layer covering at least a portion of the substrate, a conductive layer filling the spaces between the gate dielectric layers and between the gate dielectric layers and the isolation layer, and a fourth insulating layer covering the conductive layer, the method further includes: Remove the isolation layer to expose the third trench; The opening of the third groove is sealed to create an air gap within the third groove.
13. The manufacturing method according to claim 12, characterized in that, Sealing the opening of the third groove to create an air gap within the third groove includes: A capping layer is deposited on the substrate, which seals the opening of the third trench to form the air gap.
14. The manufacturing method according to claim 9, characterized in that, Removing a portion of the first insulating layer, a portion of the second insulating layer, and a portion of the third insulating layer to form a fill space that exposes the substrate includes: Self-aligned etching of the first insulating layer, the second insulating layer and the third insulating layer to the initial depth to form an initial fill space; A support layer is formed on the surfaces of the substrate and the isolation layer exposed in the initial fill space, and the support layer fills the initial fill space between the substrate and the isolation layer; Using the remaining initial fill space, the first insulating layer, the second insulating layer, and the third insulating layer are etched to a preset depth to form the fill space, which includes the remaining initial fill space.
15. A semiconductor structure, characterized in that, The semiconductor structure is formed by the fabrication method according to any one of claims 1-14.