Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first ultra-low dielectric constant dielectric layer on the first MTJ, performing a first etching fabrication process to remove part of the first ultra-low dielectric constant dielectric layer and form a damaged layer on the first ultra-low dielectric constant dielectric layer, and forming a second ultra-low dielectric constant dielectric layer on the damaged layer.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201811612412.5, application date: December 27, 2018, invention title: semiconductor element and method of manufacturing thereof). Technical Field

[0002] This invention relates to a semiconductor device and its fabrication method, and more particularly to a magnetoresistive random access memory (MRAM) and its fabrication method. Background Technology

[0003] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0004] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0005] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a first magnetic tunneling junction (MTJ) is formed on a substrate. Then, a first ultra-low dielectric constant dielectric layer is formed on the first MTJ. A first etching process is performed to remove part of the first ultra-low dielectric constant dielectric layer and form a damaged layer on the first ultra-low dielectric constant dielectric layer. Finally, a second ultra-low dielectric constant dielectric layer is formed on the damaged layer.

[0006] Another embodiment of the present invention discloses a semiconductor device comprising a first magnetic tunneling junction (MTJ) disposed on a substrate, a first ultra-low dielectric constant dielectric layer disposed on the first MTJ, a damaged layer disposed on the first ultra-low dielectric constant dielectric layer, and a second ultra-low dielectric constant dielectric layer disposed on the damaged layer.

[0007] Another embodiment of the present invention discloses a semiconductor device comprising a first magnetic tunneling junction (MTJ) and a second MTJ disposed on a substrate, a capping layer disposed on the first MTJ and the second MTJ, wherein the upper surface of the capping layer disposed between the first MTJ and the second MTJ is lower than the upper surface of the capping layer directly above the first MTJ, and an ultra-low dielectric constant dielectric layer is disposed on the capping layer.

[0008] Another embodiment of the present invention discloses a semiconductor device comprising a first magnetic tunneling junction (MTJ) and a second MTJ disposed on a substrate, a first ultra-low dielectric layer disposed on the first MTJ and the second MTJ, a first capping layer disposed within the first ultra-low dielectric layer and between the first MTJ and the second MTJ, and a second ultra-low dielectric layer disposed on the first ultra-low dielectric layer. Attached Figure Description

[0009] Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0010] Figures 8 to 11 This is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention;

[0011] Figures 12 to 14 This is a schematic diagram of a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0012] Explanation of main component symbols

[0013] 12 Base 14 MTJ Region

[0014] 18 interlayer dielectric layers 20 metal interconnect structure

[0015] 22 Metal interconnect structure 24 Intermetal dielectric layer

[0016] 26 Metal interconnects 28 Stop layer

[0017] 30 Intermetallic dielectric layer; 32 Metallic interconnect.

[0018] 34 Barrier layer 36 Metal layer

[0019] 38 MTJ stacked structure 40 cover layer

[0020] 42 Covering layer 44 First electrode layer

[0021] 46 Fixed layer 48 Free layer

[0022] 50 Covering layer 52 Second electrode layer

[0023] 54 Patterned Mask 56 Organic Dielectric Layer

[0024] 58 Silicon-containing hard mask and anti-reflective layer 60 Patterned photoresist

[0025] 62 MTJ 64 First inclined sidewall

[0026] 66 Second inclined sidewall 68 Lining layer

[0027] 70 Spacer wall 72 MTJ

[0028] 74 Covering layer 76 Opening

[0029] 78 Concave surface (upper part) 80 Concave surface (lower part)

[0030] 82 Ultra-low dielectric constant dielectric layer 84 Intermetallic dielectric layer

[0031] 86 Ultra-low dielectric constant dielectric layer 88 First opening

[0032] 90 Concave surface 92 Second opening

[0033] 94 Damaged layer 96 Inverted V-shape

[0034] 98 First etching process 100 Second etching process

[0035] 102 Third opening 104 Ultra-low dielectric constant dielectric layer

[0036] 108 Ultra-low dielectric constant dielectric layer 110 Opening

[0037] 112 Capping layer; 114 Ultra-low dielectric constant dielectric layer

[0038] 116 Covering layer 118 Covering layer

[0039] 120 Covering Layer Detailed Implementation

[0040] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, an MRAM cell, according to one embodiment of the present invention. Figures 1 to 7 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and a magnetic tunneling junction (MTJ) region 14 and a logic region (not shown) are preferably defined on the substrate 12.

[0041] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0042] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 of the MTJ region 14 and the logic region to electrically connect the aforementioned contact plugs. The metal interconnect structure 20 includes an intermetallic dielectric layer 24 and metal interconnects 26 embedded in the intermetallic dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetallic dielectric layer 30 and a plurality of metal interconnects 32 embedded in the stop layer 28 and the intermetallic dielectric layer 30.

[0043] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MTJ region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. In addition, in this example, metal layer 36 preferably includes copper, intermetallic dielectric layer 24 and 30 preferably include silicon oxide, and stop layer 28 includes a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0044] Next, an MTJ stack structure 38 is formed on the metal interconnect structure 22, a capping layer 40 is formed on the MTJ stack structure 38, and another capping layer 42 is formed on the pad layer 40. In this embodiment, the MTJ stack structure 38 can be formed sequentially by first forming a first electrode layer 44, a fixed layer 46, a free layer 48, a capping layer 50, and a second electrode layer 52. In this embodiment, the first electrode layer 44 and the second electrode layer 52 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The fixed layer 46 can be made of an antiferromagnetic (AFM) material, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers. The free layer 48 can be made of a ferromagnetic material, such as iron, cobalt, nickel, or their alloys like cobalt-iron-boron (CoFeB), but is not limited thereto. The magnetization direction of the free layer 48 can be "freely" changed by an external magnetic field. The covering layer 50 can be made of an insulating material containing oxides, such as aluminum oxide (AlO).x The materials used may be silicon nitride or magnesium oxide (MgO), but are not limited to these. Additionally, the masking layer 40 and the masking layer 42 preferably contain different materials; for example, in this embodiment, the masking layer 40 preferably contains silicon nitride and the masking layer 42 preferably contains silicon oxide, but are not limited to these.

[0045] Next, a patterned mask 54 is formed on the masking layer 42. In this embodiment, the patterned mask 54 may include an organic dielectric layer (ODL) 56, a silicon-containing hard mask bottom anti-reflective coating (SHB) layer 58, and a patterned photoresist 60.

[0046] like Figure 2 As shown, a patterned mask 54 is then used as a mask to perform one or more etching processes to remove part of the masking layers 40 and 42, part of the MTJ stack structure 38, and part of the intermetallic dielectric layer 30 to form MTJs 62 and 72 in the MTJ region 14. The masking layers 40 and 42 can be removed together during the etching process. It is worth noting that in this embodiment, a reactive ion etching (RIE) process can be performed using the patterned mask 54 to remove part of the masking layers 40 and 42 and part of the MTJ stack structure 38. Then, the patterned mask 54 is removed, and then an ion beam etching (IBE) process is performed using the patterned masking layer 42 as a mask to remove part of the MTJ stack structure 38 and part of the intermetallic dielectric layer 30 to form MTJs 62 and 72. Due to the characteristics of the ion beam etching process, the upper surface of the remaining intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface.

[0047] It should also be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, it is preferable to remove part of the metal interconnects 32 at the same time, so that the metal interconnects 32 form a first inclined sidewall 64 and a second inclined sidewall 66 near the junction of MTJ 62 and 72.

[0048] Then as Figure 3 As shown, a pad layer 68 is formed on MTJ 62, 72 and covers the surface of the intermetallic dielectric layer 30. In this embodiment, the pad layer 68 preferably contains silicon oxide, but other dielectric materials may be selected according to the manufacturing process requirements, such as silicon oxide, silicon oxynitride, or silicon carbide.

[0049] like Figure 4As shown, an etching process is then performed to remove part of the pad layer 68 to form a spacer wall 70 next to each MTJ 68. The spacer wall 70 is preferably disposed on the sidewall of each MTJ 68 and simultaneously covers and contacts the first inclined sidewall 64 and the second inclined sidewall 66 of the metal interconnect 32.

[0050] Then as Figure 5 As shown, a capping layer 74 is formed on the surface of the inter-metal dielectric layer 30 and completely covers MTJs 62 and 72. In this embodiment, the capping layer 74 can be formed using atomic deposition or high-density plasma (HDP) processes, depending on the fabrication requirements. The capping layer 74 may include, but is not limited to, tetraethyl orthosilicate (TEOS), silicon oxide, silicon nitride, or combinations thereof. It should be noted that when the capping layer 74 is formed above the inter-metal dielectric layer 30 and covers MTJs 62 and 72 in this stage, it is preferable that the outline of MTJs 62 and 72 forms an opening 76 between MTJs 62 and 72.

[0051] like Figure 6 As shown, an etching process is then performed to remove part of the capping layer 74, particularly the portion of the capping layer 74 on both sides of MTJ 62 and 72, including the left side of MTJ 62, the right side of MTJ 72, and the portion between MTJ 62 and 72. Preferably, the etching process exposes and expands the surface of the intermetallic dielectric layer 30 on the left side of MTJ 62 and the right side of MTJ 72. Figure 5 The opening 76 formed between MTJ 62 and 72 does not expose the intermetallic dielectric layer 30 between MTJ 62 and 72. In this embodiment, after the etching process is completed, the upper surface of the cover layer 74 between MTJ 62 and 72 preferably presents a concave upward surface 78, while the upper surface of the cover layer 74 directly above each MTJ 62 and 72 presents a concave downward surface 80.

[0052] like Figure 7As shown, an ultra-low dielectric constant layer 82 is then formed as another inter-metal dielectric layer 84 on the inter-metal dielectric layer 30 and covering the capping layer 74. Preferably, the ultra-low dielectric constant layer 82 surrounds MTJs 62 and 72 but does not directly contact them. In this embodiment, the ultra-low dielectric constant layer 82 and the capping layer 74 preferably contain different materials. The ultra-low dielectric constant layer 82 and the ultra-low dielectric constant layer in subsequent embodiments may contain porous dielectric materials such as, but not limited to, silicon oxycarbide (SiOC). This completes the fabrication of an MRAM cell according to an embodiment of the present invention.

[0053] Please continue to refer to Figures 8 to 11 , Figures 8 to 11 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 8 As shown, the aforementioned steps are performed first. Figures 1 to 4 The fabrication process involves forming MTJs 62 and 72 on the substrate 12, and then forming an ultra-low dielectric constant dielectric layer 86 on the MTJs 62 and 72, while simultaneously forming a first opening 88 between the MTJs 62 and 72. Preferably, the upper surface of the ultra-low dielectric constant dielectric layer 86 located directly above each MTJ 62 and 72 in this stage includes a curved surface or, more specifically, a concave curved surface 90.

[0054] Then as Figure 9 As shown, a first etching process 98 is performed to remove a portion of the ultra-low dielectric constant layer 86 and form a second opening 92 between MTJs 62 and 72. Preferably, the width of the first opening 88 is smaller than the width of the second opening 92, and the opening width mentioned in this stage preferably refers to the maximum opening width between MTJs 62 and 72. It is worth noting that during the latter half of the first etching process 98, nitrogen gas is preferably bombarded into the ultra-low dielectric constant layer 86, causing a partial surface transformation or formation of a damaged layer 94 on the ultra-low dielectric constant layer 86. Since the damaged layer 94 in this stage is formed by implanting nitrogen gas into the ultra-low dielectric constant layer 86, the damaged layer 94 may include, but is not limited to, silicon oxycarbonitride (SiOCN). It should also be noted that the first etching process 98 performed in this stage preferably removes the ultra-low dielectric layer 86 located directly above each MTJ 62, 72 when forming the second opening 92, so that the upper surface of the ultra-low dielectric layer 86, which originally presented a concave curved surface 90, is transformed into a V-shape or more specifically an inverted V-shape 96.

[0055] like Figure 10As shown, a selective second etching process 100 is then performed to remove a portion of the ultra-low dielectric constant dielectric layer 86 to form a third opening 102 between MTJs 62 and 72, wherein the width of the second opening 92 is preferably smaller than the width of the third opening 102. It should be noted that the second etching process 100 performed in this stage preferably selectively removes a portion of the damaged layer 94 on the sidewalls of each MTJ 62 and 72, but does not remove the damaged layer 94 located directly above each MTJ 62 and 72, or simultaneously located between MTJs 62 and 72 and at the bottom of the second opening 92. In other words, after completing the second etching process 100, an inverted V-shaped damaged layer 94 is still present directly above each MTJ 62 and 72, and a damaged layer 94 is still present at the bottom of the second opening 92 between MTJ 62 and 72. However, the surface of the ultra-low dielectric layer 86 on the sidewalls of each MTJ 62 and 72, or more specifically, the sidewalls of MTJ 62 and 72, preferably has no damaged layer 94 left, but only an ultra-low dielectric layer 86. In addition, the second etching process 100 performed in this stage can be achieved using diluted hydrofluoric acid (dHF) or SiCoNi fabrication process. It should be noted that the SiCoNi fabrication process mainly uses fluorine-containing gas to react with silicon oxide to generate ammonium fluorosilicate ((NH4)2SiF6) to selectively remove native silicon oxide. The aforementioned fluorine-containing gas may include hydrogen fluoride (HF) or nitrogen trifluoride (NF3).

[0056] Then as Figure 11 As shown, another ultra-low dielectric constant layer 104 is formed on the damaged layer 94 and completely covers MTJs 62 and 72. Preferably, the ultra-low dielectric constant layer 104 surrounds MTJs 62 and 72 but does not directly contact them. In this embodiment, the ultra-low dielectric constant layer 104 and the ultra-low dielectric constant layer 86 below the damaged layer 94 may contain the same or different materials. The ultra-low dielectric constant layers 86 and 104 may contain porous dielectric materials such as, but not limited to, silicon oxycarbide (SiOC). This completes the fabrication of an MRAM cell according to an embodiment of the present invention.

[0057] Please continue to refer to Figures 12 to 14 , Figures 12 to 14 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 12 As shown, the aforementioned steps are performed first. Figures 1 to 4The fabrication process involves forming MTJs 62 and 72 on a substrate 12, and then forming an ultra-low dielectric constant dielectric layer 108 on the MTJs 62 and 72, while simultaneously forming an opening 110 or a hole between the MTJs 62 and 72. In this stage, the upper surface of the ultra-low dielectric constant dielectric layer 108 located directly above each MTJ 62 and 72 preferably includes a curved surface or, more specifically, a concave curved surface.

[0058] like Figure 13 As shown, a capping layer 112 is then formed on the ultra-low dielectric layer 108 and fills the opening 110. In this embodiment, the capping layer 112 can be formed using atomic deposition or high-density plasma (HDP) processes, depending on the fabrication requirements. Preferably, the capping layer 112 and the ultra-low dielectric layer 108 contain different materials, such as, but not limited to, tetraethoxysilane (TEOS), silicon oxide, silicon nitride, or combinations thereof.

[0059] Subsequently, as Figure 14 As shown, another ultra-low dielectric constant dielectric layer 114 is formed on the capping layer 112. Preferably, the ultra-low dielectric constant dielectric layer 114 contains a different material than the capping layer 112, but may contain the same or different materials as the ultra-low dielectric constant dielectric layer 108. Then, a planarization process is performed, for example, using chemical mechanical polishing (CMP) to remove a portion of the ultra-low dielectric constant dielectric layer 114, a portion of the capping layer 112, and a portion of the ultra-low dielectric constant dielectric layer 108, so that the upper surface of the ultra-low dielectric constant dielectric layer 114 is flush with the upper surfaces of the capping layer 112 and the ultra-low dielectric constant dielectric layer 108. This completes the fabrication of an MRAM cell according to an embodiment of the present invention.

[0060] Please refer to again Figure 14 , Figure 14 This is a schematic diagram of the structure of an MRAM cell according to an embodiment of the present invention. Figure 14 As shown, the MRAM cell in this embodiment mainly includes MTJ 62 and 72 disposed on the substrate 12, an ultra-low dielectric constant dielectric layer 108 disposed on the MTJ 62 and 72, another ultra-low dielectric constant dielectric layer 114 disposed on the ultra-low dielectric constant dielectric layer 108, and a capping layer 112 disposed between the ultra-low dielectric constant dielectric layers 108 and 114.

[0061] In detail, the capping layer comprises three parts: capping layer 116 is disposed within the ultra-low dielectric constant layer 108 and between MTJs 62 and 72; capping layer 118 is disposed between the ultra-low dielectric constant layer 108 and the ultra-low dielectric constant layer 114, with MTJ 62 disposed between capping layer 116 and capping layer 118; and capping layer 120 is disposed between the ultra-low dielectric constant layer 108 and the ultra-low dielectric constant layer 114, with MTJ 72 disposed between capping layer 116 and capping layer 120. Specifically, capping layer 116, disposed between the two MTJs 62 and 72, only contacts the ultra-low dielectric constant layer 108 but not the ultra-low dielectric constant layer 114, while capping layers 118 and 120 simultaneously contact both ultra-low dielectric constant layers 108 and 114.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: The first magnetic tunnel junction is formed on the substrate; A first ultra-low dielectric constant dielectric layer is formed on the first magnetic tunnel junction, wherein the upper surface of the first ultra-low dielectric constant dielectric layer includes a curved surface, wherein the curved surface is a curved surface convex in a direction away from the substrate. A first etching process is performed to remove a portion of the first ultra-low dielectric constant layer to transform the curved surface into a V-shape, and a damaged layer is formed on the first ultra-low dielectric constant layer. The V-shape is an inverted V-shape convex away from the substrate. The curved surface and the V-shape are located directly above and cover the first magnetic tunneling junction. A second ultra-low dielectric constant dielectric layer is formed on the damaged layer.

2. The method of claim 1, wherein the first etching process comprises bombarding the first ultra-low dielectric constant dielectric layer with nitrogen gas to form the damaged layer.

3. The method of claim 1, further comprising: The first magnetic tunneling junction and the second magnetic tunneling junction are formed on the substrate; The first ultra-low dielectric constant dielectric layer is formed on the first magnetic tunnel junction and the second magnetic tunnel junction, and a first opening is formed between the first magnetic tunnel junction and the second magnetic tunnel junction. The first etching process is performed to form a second opening between the first magnetic tunnel junction and the second magnetic tunnel junction; and Before forming the second ultra-low dielectric constant dielectric layer, a second etching process is performed to remove part of the first ultra-low dielectric constant dielectric layer to form a third opening between the first magnetic tunnel junction and the second magnetic tunnel junction.

4. The method of claim 3, wherein the width of the first opening is smaller than the width of the second opening.

5. The method of claim 3, wherein the width of the second opening is smaller than the width of the third opening.

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