Linear power supply circuit

Abstract

A linear power supply circuit includes: an output stage provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, and including a first output transistor and a second output transistor connected in parallel with each other; a driver configured to drive the first output transistor and the second output transistor based on a voltage difference between the output voltage and a reference voltage; and a potential difference suppressor configured to suppress a potential difference between a control terminal of the first output transistor and a control terminal of the second output transistor.

Description

Technical Field

[0001] The invention disclosed herein relates to a linear power supply circuit. Background Technology

[0002] Linear power supply circuits (such as LDO (low dropout) type linear power supply circuits) are used as power supplies in various devices.

[0003] For linear power supply circuits, it is preferable that phase compensation is possible even when the capacitance value in the output capacitor is reduced, without a significant increase in circuit area.

[0004] Examples of known technologies related to the technologies mentioned above can be seen in the patent document 1 identified below.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2020-071681

[0008] Figure 10 This is a schematic diagram showing a known linear power supply circuit according to Patent Document 1.

[0009] A known linear power supply circuit includes an input terminal T1, an output terminal T2, a first output transistor 1, a driver 2, a reference voltage generator 3, and a phase compensation circuit 8. It also has an externally connected output capacitor 6 and a load 7. The linear power supply circuit steps down (reduces) the input voltage VIN to generate an output voltage VOUT and supplies the output voltage VOUT to the load 7. The conductivity of the first output transistor 1 and the conductivity (in other words, its on-resistance value) of the second output transistor 81, which will be described later, are controlled using a gate signal G1. Figure 10 In the configuration shown, the first output transistor 1 and the second output transistor 81 are implemented using PMOSFETs (P-channel MOSFETs). Therefore, as the voltage level of the gate signal G1 decreases, the conductivity of the first output transistor 1 and the second output transistor 81 increases, and the output voltage VOUT rises.

[0010] The driver 2 includes a differential amplifier 21, a capacitor 22, a PMOSFET 23, a current amplifier 24, and a PMOSFET 25 disposed in the current mirror circuit.

[0011] One terminal of capacitor 22 is supplied with the output of differential amplifier 21, and the other terminal of capacitor 22 is supplied with ground potential. Therefore, the connection node between differential amplifier 21 and capacitor 22 is grounded in the high-frequency band, which helps to achieve a fast response of driver 2.

[0012] The phase compensation circuit 8 includes a second output transistor 81, a resistor 82, and a capacitor 83.

[0013] One terminal of resistor 82 is connected to the gate of the first output transistor 1 and the gate of the PMOSFET 25 disposed in the current mirror circuit, and the other terminal of resistor 82 is connected to the gate of the second output transistor 81. Capacitor 83 is connected between the gate and source of the second output transistor 81.

[0014] Now, examples of known techniques will be given. Figure 10 Description of the function of phase compensation circuit 8 in the linear power supply circuit shown. Figure 11 This is a schematic diagram showing the gain response of the transfer function of the first output transistor 1 and the phase compensation circuit 8. The first pole frequency FP1' is the frequency of the first pole attributable to the parasitic capacitance CPD. The first pole of the transfer function of the first output transistor 1 is a pole independent of the output capacitor 6.

[0015] The current through the second output transistor 81, which has a CR circuit (resistor 82 and capacitor 83) connected to its gate, causes the first pole frequency FP1' to shift to a lower range compared to the case where the phase compensation circuit 8 is not provided (thick dashed line). This results in a lower gain in the range above the first pole frequency FP1' compared to the case where the first pole frequency FP1' is not shifted to a lower range.

[0016] Furthermore, since the first output transistor 1 and the second output transistor 81 are connected in parallel and the first output transistor 1 is not affected by resistor 82, the second pole appears at the original position of the first pole frequency FP1' before it shifts to a lower range. The frequency at the second pole is the second pole frequency FP2'. The shift of the first pole frequency FP1' to a lower range and the resulting drop in gain cause the zero-crossing frequency FZC' to shift to a lower range.

[0017] The first pole frequency FP1' and the second pole frequency FP2' are... Figure 10 The second pole frequency of the transfer function of the linear power supply circuit and the output capacitor 6 shown is related. Therefore, compared to the case where the phase compensation circuit 8 is not provided, the phase compensation circuit 8 can... Figure 10 The second pole frequency of the transfer function of the linear power supply circuit and output capacitor 6 shown is shifted to a lower range. Compared to the case without phase compensation circuit 8, this shift allows phase compensation circuit 8 to operate at frequencies higher than... Figure 10 The second pole frequency of the transfer function of the linear power supply circuit and output capacitor 6 shown decreases within the range of the linear power supply circuit and output capacitor 6. Figure 10 The gain of the transfer function of the linear power supply circuit and output capacitor 6 shown. This leads to Figure 10The zero-crossing frequency of the transfer function of the linear power supply circuit and output capacitor 6 shown is shifted to a lower range. Therefore, even with a reduced capacitance in output capacitor 6, Figure 10 The linear power supply circuit shown can also achieve phase compensation by adding phase compensation circuit 8 separately (i.e., without a significant increase in circuit area). Summary of the Invention

[0018] The problem that the invention aims to solve

[0019] Figure 12 It is shown in Figure 10 The diagram illustrates the relationship between the input voltage VIN, the gate voltages of the first output transistor 1 and the second output transistor 81, and the output voltage VOUT in the linear power supply circuit shown. Figure 12 In the diagram, the vertical axis represents voltage, and the horizontal axis represents time. Therefore, Figure 12 The diagram shows the time variation of each of the following: input voltage VIN, output voltage VOUT, gate voltage VPG (gate signal G1) driving the first output transistor 1, and gate voltage VPGF driving the second output transistor 81.

[0020] Figure 12 The following is revealed. At time point t1, when the input voltage VIN begins to rise from 4.75V to 16V, both the gate voltages VPG and VPGF begin to rise. However, note the time point at which the input voltage VIN finishes rising; when the gate voltage VPG has already risen to a certain level, the level of the gate voltage VPGF at that time point is lower than the level of the gate voltage VPG, and this can cause a delay in the rise of the gate voltage VPG. This can be attributed to the CR circuit (resistor 82 and capacitor 83) in the phase compensation circuit 8.

[0021] Methods for solving problems

[0022] According to one aspect of the disclosure herein, a linear power supply circuit includes: an output stage between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, the output stage including a first output transistor and a second output transistor connected in parallel with each other; a driver configured to drive the first output transistor and the second output transistor based on a voltage difference between the output voltage and a reference voltage; and a potential difference suppressor configured to suppress a potential difference between a control terminal of the first output transistor and a control terminal of the second output transistor.

[0023] According to another aspect disclosed herein, a vehicle includes a linear power supply circuit configured as described above.

[0024] The effects of the invention

[0025] According to the invention disclosed herein, overshoot in the output voltage caused by delays attributable to resistors and capacitors used for phase compensation can be suppressed. Attached Figure Description

[0026] Figure 1 This is a schematic diagram illustrating a configuration example of a linear power supply circuit according to the first embodiment.

[0027] Figure 2 This is a schematic diagram illustrating an example configuration of an operational amplifier.

[0028] Figure 3 This is a schematic diagram illustrating an example configuration of a current amplifier.

[0029] Figure 4 It is shown in Figure 1 A schematic diagram showing the relationship between the gate voltage and output voltage of the first and second output transistors in the linear power supply circuit shown.

[0030] Figure 5 This is a schematic diagram illustrating an example configuration of a linear power supply circuit according to the second embodiment.

[0031] Figure 6 This is a schematic diagram illustrating another configuration example of a current amplifier.

[0032] Figure 7 This is a schematic diagram illustrating an example configuration of a linear power supply circuit according to a third embodiment.

[0033] Figure 8 This is an external view of a semiconductor integrated circuit device.

[0034] Figure 9 This is an external view of the vehicle.

[0035] Figure 10 This is a schematic diagram illustrating an example configuration of a linear power supply circuit according to Patent Document 1.

[0036] Figure 11 It is shown Figure 10 The diagram shows the gain response of the transfer function of the linear power supply circuit and the output capacitor.

[0037] Figure 12 It is shown in Figure 10 A schematic diagram showing the relationship between the gate voltage and output voltage of the first and second output transistors in the linear power supply circuit shown. Detailed Implementation

[0038] In this specification, constant voltage means a voltage that is constant under ideal conditions, and may be a voltage that can vary slightly with changes in temperature, etc.

[0039] In this specification, the reference voltage refers to a voltage that is constant under ideal conditions, and may be a voltage that can vary slightly with changes in temperature, etc.

[0040] In this specification, constant current means a current that is constant under ideal conditions, and may be a current that can vary slightly with changes in temperature, etc.

[0041] In this specification, MOSFET refers to a transistor whose gate has a structure consisting of at least three layers: a conductor or semiconductor (e.g., polysilicon) layer with low resistance; an insulating layer; and a P-type, N-type, or intrinsic semiconductor layer. That is, MOSFET can have any gate structure other than a three-layer structure of metal, oxide, and semiconductor.

[0042] <First Implementation Method>

[0043] Figure 1 This is a schematic diagram illustrating a configuration example of a linear power supply circuit according to the first embodiment. Figure 1 The linear power supply circuit shown includes input terminal T1, output terminal T2, first output transistor 1, driver 2, reference voltage generator 3, resistors 4 and 5, and phase compensation circuit 8. The linear power supply circuit also has an externally connected output capacitor 6 and load 7.

[0044] The first output transistor 1 is provided between the input terminal T1 and the output terminal T2. The input voltage VIN is applied to the input terminal T1, and the output voltage VOUT is applied to the output terminal T2.

[0045] Driver 2 drives the first output transistor 1 and the second output transistor, as will be described later. Specifically, driver 2 supplies a gate signal G1 to the gate of the first output transistor 1 and, via resistor 82, to the gate of the second output transistor 81, thereby driving the first output transistor 1 and the second output transistor 81. The conductivity (in other words, their on-resistance) of the first output transistor 1 and the second output transistor 81 is controlled by the gate signal G1. Figure 1In the illustrated configuration, the first output transistor 1 and the second output transistor 81 are implemented using PMOSFETs. Therefore, as the voltage level of the gate signal G1 decreases, the conductivity of the first output transistor 1 and the second output transistor 81 increases, and the output voltage VOUT rises. In other words, as the voltage level of the gate signal G1 increases, the conductivity of the first output transistor 1 and the second output transistor 81 decreases, and the output voltage VOUT decreases. The first output transistor 1 and the second output transistor 81 can be implemented using NMOSFETs or bipolar transistors instead of PMOSFETs.

[0046] Driver 2 includes a differential amplifier 21, a capacitor 22, a PMOSFET 23, a current amplifier 24, and a PMOSFET 25.

[0047] The inverting input terminal (-) of differential amplifier 21 is supplied with a feedback voltage VFB, and the non-inverting input terminal (+) of differential amplifier 21 is supplied with a reference voltage VREF. Based on the difference ΔV (=VFB-VREF) between the feedback voltage VFB and the reference voltage VREF, driver 2 drives the first output transistor 1 and the second output transistor 81. As the difference ΔV increases, driver 2 raises the voltage level of the gate signal G1; as the difference ΔV decreases, driver 2 lowers the voltage level of the gate signal G1.

[0048] One terminal of capacitor 22 is supplied with the output of differential amplifier 21, and the other terminal of capacitor 22 is supplied with ground potential.

[0049] The source of PMOSFET 23 is supplied with the output voltage VOUT, and the gate of PMOSFET 23 is supplied with a voltage based on the output of differential amplifier 21 (i.e., the voltage at the connection node between differential amplifier 21 and capacitor 22). PMOSFET 23 converts the voltage based on the output of differential amplifier 21 into a current to output that current from its drain. The connection node between differential amplifier 21 and capacitor 22 is grounded in the high-frequency band, which helps to achieve a fast response of driver 2.

[0050] The differential amplifier 21 and PMOSFET 23 have lower withstand voltages than the current amplifier 24. The gain of the differential amplifier 21 is lower than the gain of the current amplifier 24. This helps to reduce the size of the differential amplifier 21 and PMOSFET 23.

[0051] Current amplifier 24 amplifies the current Ia output from the drain of PMOSFET 23. The power supply voltage of current amplifier 24 is a constant voltage VREG. That is, current amplifier 24 operates based on the voltage between the constant voltage VREG and ground potential.

[0052] PMOSFET 25, together with the first output transistor 1, forms a current mirror circuit. PMOSFET 25 converts the current Ib output from the current amplifier 24 into a voltage to supply this voltage to the gate of the first output transistor 1.

[0053] Reference voltage generator 3 produces a reference voltage VREF. Resistors 4 and 5 generate a feedback voltage VFB, which serves as a voltage divider for the output voltage VOUT.

[0054] The output voltage VOUT is supplied from the output terminal T2 to the output capacitor 6 and the load 7.

[0055] The phase compensation circuit 8 includes a second output transistor 81, a resistor 82, a capacitor 83, and an operational amplifier 84. Incidentally, a configuration different from that in this embodiment, where a delay can occur between the gate potentials of the first output transistor 1 and the second output transistor 81, allows the resistor 82 and the capacitor 83 to be omitted.

[0056] The second output transistor 81 is connected in parallel with the first output transistor 1. That is, the source of the second output transistor 81 is connected to the source of the first output transistor 1, and the drain of the second output transistor 81 is connected to the drain of the first output transistor 1. In this embodiment, the size of the second output transistor 81 is larger than the size of the output transistor 1, such that the current through the second output transistor 81 is higher than the current through the first output transistor 1. Here, "size" specifically refers to "area".

[0057] One terminal of resistor 82 is connected to the gate of the first output transistor 1 and PMOSFET 25, and the other terminal of resistor 82 is connected to the gate of the second output transistor 81.

[0058] A capacitor 83 is provided between the gate and source of the second output transistor 81. In this embodiment, the parasitic capacitor of the second output transistor 81 serves as capacitor 83. Alternatively, a capacitor other than the parasitic capacitor of the second output transistor 81 can be used as capacitor 83, or the parasitic capacitor of the second output transistor 81 can be used together with a capacitor other than the parasitic capacitor of the second output transistor 81 as capacitor 83. Using a capacitor other than the parasitic capacitor of the second output transistor 81 as part of capacitor 83 allows for easy adjustment of the capacitance value of capacitor 83. Preferably, the capacitance value of capacitor 83 is higher than the capacitance value of the parasitic capacitance CPD. The phase compensation circuit 8 may also include a capacitor provided between the gate and drain of the second output transistor 81.

[0059] Operational amplifier 84 is an example of a potential difference suppressor that suppresses the potential difference between the gates of the first output transistor 1 and the second output transistor 81. The potential difference suppressor can be configured, for example, to monitor the voltage difference between the voltages at the gates of the first output transistor 1 and the second output transistor 81, and if the voltage difference is equal to or greater than a predetermined value, to output a control signal to control at least one of the voltages at the gates of the first output transistor 1 and the second output transistor 81, thereby reducing the potential difference between the gates of the first output transistor 1 and the second output transistor 81. In this embodiment, operational amplifier 84 outputs the control signal just mentioned.

[0060] Operational amplifier 84 has an input offset voltage of 84A. The non-inverting input terminal (+) of operational amplifier 84 is connected to the gate of the first output transistor 1. The inverting input terminal (-) and output terminal of operational amplifier 84 are connected to the gate of the second output transistor 81. With this configuration, if the potential difference between the gates of the first output transistor 1 and the second output transistor 81 becomes equal to or higher than the input offset voltage 84A, operational amplifier 84 operates to maintain the potential difference between the gates of the first output transistor 1 and the second output transistor 81 equal to the input offset voltage 84A.

[0061] Figure 2 This is a schematic diagram showing an example configuration of operational amplifier 84. Figure 2 The operational amplifier 84 in the configuration example shown includes an NMOSFET 841 as a first input differential pair transistor, an NMOSFET 842 as a second input differential pair transistor, PMOSFETs 843 and 844 forming a current mirror circuit, and an NMOSFET 845 serving as a source follower output stage.

[0062] The aforementioned current mirror circuit supplies a first current to NMOSFET 841 and a second current, which is a mirror current of the first current, to NMOSFET 842.

[0063] The source of NMOSFET 841 serves as the non-inverting input (+) of operational amplifier 84, the source of NMOSFET 842 serves as the inverting input (-) of operational amplifier 84, and the source of NMOSFET 845 serves as the output of operational amplifier 84. A bias voltage Vb is applied to the gates of NMOSFETs 841 and 842. The drain of NMOSFET 841 is connected to the drain of PMOSFET 843 and the gate of NMOSFET 845. The drain of NMOSFET 842 is connected to the drain and gate of PMOSFET 844 and the gate of PMOSFET 843. An input voltage VIN is supplied to the sources of PMOSFET 843, PMOSFET 844, and the drain of NMOSFET 845. The source of NMOSFET 845 is connected to the source of NMOSFET 842.

[0064] exist Figure 2 In the operational amplifier 84 of the illustrated configuration example, the input offset voltage 84A is generated at least by giving the NMOSFETs 841 and 842 different channel width to channel length ratios or by giving the first and second currents different values ​​(setting the mirror ratio of the aforementioned current mirror circuit to be non-1). With this configuration, the input offset voltage 84A can be easily and precisely set to the design value.

[0065] Figure 3 It is shown Figure 1 The diagram illustrates an example configuration of the current amplifier 24 in the linear power supply circuit shown. The current amplifier 24 includes current-sink current mirror circuits CM_1, CM_2, ..., CM_n and current-source current mirror circuits CM_3, ..., CM_n-1 (however, CM_n-1 is not included). Figure 3 (As shown in the diagram). Between one end of the current trap current mirror circuit CN_1 and the constant current source SC1 that generates a constant current I1, and the other end of the current trap current mirror circuit CM_n, from the input to the output of the current amplifier 24, current trap current mirror circuits and current source current mirror circuits are alternately arranged to amplify the current. The amplified current is finally converted into a current Ib in the last stage to be converted into a voltage for use as the gate signal G1.

[0066] Figure 4 It is shown in Figure 1 This diagram illustrates the relationship between the input voltage VIN, the gate voltages of the first output transistor 1 and the second output transistor 81, and the output voltage VOUT in the linear power supply circuit shown. Figure 4 In the diagram, the vertical axis represents voltage, and the horizontal axis represents time. Therefore, Figure 4The diagram shows the time variation of each of the following: input voltage VIN, output voltage VOUT, gate voltage VPG (gate signal G1) driving the first output transistor 1, and gate voltage VPGF driving the second output transistor 81.

[0067] Figure 4 The following was revealed. At time point t1, when the input voltage VIN begins to rise from 4.75V to 16V, both the gate voltages VPG and VPGF begin to rise, and here, the gate voltage VPGF rises without any delay compared to the rise of the gate voltage VPG. That is, the gate voltages VPG and VPGF rise together. This is because the operational amplifier 84 suppresses the voltage difference between the gate voltages VPG and VPGF.

[0068] Note the conductivity of the first output transistor 1 and the second output transistor 81 respectively. The suppressed voltage difference between the gate voltages VPG and VPGF causes the suppressed conductivity difference between these transistors. This helps to suppress overshoot in the output voltage VOUT and prevents the output voltage VOUT from exceeding the target output voltage of 5V too far.

[0069] <Second Implementation Method>

[0070] Figure 5 This is a schematic diagram showing the configuration of a linear power supply circuit according to the second embodiment. Figure 5 In, such as in Figure 1 These parts, whose corresponding parts are found, are identified by the same reference numerals in the accompanying drawings, and their detailed descriptions will not be repeated.

[0071] In this embodiment, the driver 2 includes a differential amplifier 21', a capacitor 22', an NMOSFET 23', a current amplifier 24, and a PMOSFET 25.

[0072] The differential amplifier 21' outputs a voltage corresponding to the difference between the feedback voltage VFB and the reference voltage VREF. The supply voltage of the differential amplifier 21' is a first constant voltage VREG1. That is, the differential amplifier 21' operates based on the voltage between the first constant voltage VREG1 and the ground potential.

[0073] The differential amplifier 21' and NMOSFET 23' have lower withstand voltages than the current amplifier 24. The gain of the differential amplifier 21' is lower than the gain of the current amplifier 24. This helps to reduce the size of the differential amplifier 21' and NMOSFET 23'.

[0074] One terminal of capacitor 22' is supplied with the output of differential amplifier 21', and the other terminal of capacitor 22' is supplied with the output voltage VOUT. Instead of the output voltage VOUT, a voltage that depends on the output voltage VOUT can be supplied to the other terminal of capacitor 22.

[0075] The source of NMOSFET 23' is supplied with ground potential, and the gate of NMOSFET 23' is supplied with a voltage based on the output of differential amplifier 21' (i.e., the voltage at the connection node between differential amplifier 21' and capacitor 22'). NMOSFET 23' converts the voltage based on the output of differential amplifier 21' into current to output that current from its drain. The connection node between differential amplifier 21' and capacitor 22' serves as ground (positive ground) for the output voltage VOUT in the high-frequency band, and this contributes to the fast response of driver 2.

[0076] Current amplifier 24 amplifies the current Ia output from the drain of NMOSFET 23'. The supply voltage of current amplifier 24 is a second constant voltage VREG2. That is, current amplifier 24 operates based on the voltage between the second constant voltage VREG2 and ground potential. The first constant voltage VREG1 and the second constant voltage VREG2 can have equal values ​​or can have different values. In this configuration example, current Ia is passed from current amplifier 24 to NMOSFET 23', and therefore current amplifier 24 can utilize, for example, ... Figure 6 The circuit configuration shown is used for implementation.

[0077] Figure 5 The phase compensation circuit in the linear power supply circuit of the illustrated embodiment is similar to... Figure 1 The phase compensation circuit in the linear power supply circuit of the first embodiment shown. Therefore, it performs a similar effect to suppressing overshoot in the output voltage VOUT. Furthermore, even when the output voltage VOUT is at a low set value, Figure 5 The linear power supply circuit of this embodiment also ensures the operation of the differential amplifier 21'. Incidentally, when a low voltage is used as the input voltage VIN, the input voltage VIN can be used as the power supply voltage for the differential amplifier 21' instead of the first constant voltage VREG1, and the input voltage VIN can be used as the power supply voltage for the current amplifier 24 instead of the second constant voltage VREG2.

[0078] <Third Implementation Method>

[0079] Figure 7 This is a schematic diagram showing the configuration of a linear power supply circuit according to the third embodiment. Figure 7The linear power supply circuit shown is generated by applying phase compensation circuit 8 to a linear power supply circuit with a well-known PMOS source-grounded output stage.

[0080] Figure 7 The linear power supply circuit with a PMOS source-grounded output stage shown is a well-known conventional technique and therefore will not be described in detail. Furthermore, utilizing... Figure 7 The linear power supply circuit shown can suppress overshoot in the output voltage by suppressing the conductivity difference between the first output transistor Q1 and the second output transistor 81.

[0081] As described above, the phase compensation circuit disclosed herein can be applied not only to linear power supply circuits according to the first and second embodiments, but also to configurations that typically include multiple output transistors.

[0082] <Application Example 1>

[0083] Figure 8 This is an external view of a semiconductor integrated circuit device. Figure 8 The illustrated semiconductor integrated circuit device has external pins P1 to P14 and includes an internal power supply 9. The internal power supply 9 is one of the linear power supply circuits according to the first to third embodiments described above, and whether or not an output capacitor is provided is not important when it is included in this manner. The internal power supply 9... Figure 8 At least some circuits in the semiconductor integrated circuit device shown supply an internal supply voltage Vreg (i.e., the output voltage VOUT of the linear power supply circuit).

[0084] <Application Example 2>

[0085] Figure 9 This is an exterior view of vehicle X. The vehicle X1 in this configuration example includes various electronic devices X11 to X18 that operate by being supplied with a voltage output from a battery (not shown). For convenience, in the schematic diagram, electronic devices X11 to X18 may be shown in locations different from where they are actually located.

[0086] The X11 electronic device is an engine control unit that performs controls related to the engine (injection control, electronic throttle control, idle speed control, oxygen sensor heater control, adaptive cruise control, etc.).

[0087] Electronic device X12 is a lamp control unit that controls the lighting and extinguishing of HID (High Intensity Discharge) lamps, DRLs (Daytime Running Lights), etc.

[0088] Electronic device X13 is a transmission control unit that performs controls on the transmission.

[0089] Electronic device X14 is a movement control unit that performs controls on the movement of vehicle X1 (ABS [Anti-lock Braking System] control, EPS [Electric Power Steering] control, electronic suspension control, etc.).

[0090] Electronic device X15 is a safety control unit that drives and controls door locks, burglar alarms, etc.

[0091] Electronic equipment X16 includes equipment included in the vehicle X1 as standard or assembled by the manufacturer during the factory shipment stage, such as windshield wipers, power side mirrors, power windows, dampers (shock absorbers), power sunroof, and power seats.

[0092] Electronic devices X17 include electronic devices that can be optionally installed as user-installed devices into vehicle X1, such as A / V (audio / video) equipment, car navigation systems, and ETC (electronic toll collection control systems).

[0093] The X18 electronic devices include electronic devices with high-voltage-tolerant motors, such as vehicle blowers, oil pumps, water pumps, and battery cooling fans.

[0094] Any of the linear power supply circuits described earlier can be built into any of the electronic devices X11 to X18.

[0095] <Note>

[0096] The above embodiments are illustrative rather than restrictive in every respect, and the scope of the claims disclosed herein is not limited by the description of the above embodiments but by the appended claims, and should be understood to include any modifications made within the scope that are equivalent in meaning to the claims.

[0097] The phase compensation circuit can be any circuit capable of suppressing the delay between drive signals used for transistors connected in parallel with each other, and its circuit configuration is not limited to the circuit configuration of the phase compensation circuit 8 described only as an example.

[0098] According to one aspect of the disclosure herein, a linear power supply circuit includes: an output stage between an input terminal (T1) to which an input voltage is applied and an output terminal (T2) to which an output voltage is applied, the output stage including a first output transistor (1) and a second output transistor (81) connected in parallel with each other; a driver (2) configured to drive the first output transistor and the second output transistor based on a voltage difference between the output voltage and a reference voltage; and a potential difference suppressor (84) configured to suppress a potential difference between a control terminal of the first output transistor and a control terminal of the second output transistor. (First Configuration)

[0099] The linear power supply circuit of the first configuration described above suppresses the potential difference between the control terminals of the first and second output transistors. Therefore, overshoot in the output voltage caused by delays attributable to the resistors and capacitors used for phase compensation can be suppressed.

[0100] In the linear power supply circuit of the first configuration described above, the potential difference suppressor can be configured to monitor the voltage difference between the voltage at the control terminal of the first output transistor and the voltage at the control terminal of the second output transistor. If the voltage difference is equal to or greater than a predetermined value, a control signal is output to control at least one of the voltages at the control terminals of the first and second output transistors, so as to reduce the potential difference between the control terminals of the first and second output transistors. (Second Configuration)

[0101] The linear power supply circuit of the second configuration described above prevents the potential difference between the control terminals of the first and second output transistors from becoming equal to or greater than a predetermined value. Therefore, overshoot in the output voltage caused by delays attributable to the resistors and capacitors used for phase compensation can be reliably suppressed.

[0102] In the linear power supply circuit of the second configuration described above, the potential difference suppressor may include an operational amplifier, and the operational amplifier may output the control signal. (Third configuration)

[0103] Using the linear power supply circuit of the third configuration described above, a potential difference suppressor can be constructed with a simple configuration.

[0104] In the linear power supply circuit of the third configuration described above, the operational amplifier may have an input offset voltage. The non-inverting input terminal of the operational amplifier may be connected to the control terminal of the first output transistor, and the inverting input terminal and output terminal of the operational amplifier may be connected to the control terminal of the second output transistor. (Fourth configuration)

[0105] Using the linear power supply circuit of the fourth configuration described above, the potential difference between the control terminals of the first and second output transistors can be easily prevented from becoming equal to or greater than a predetermined value by utilizing the input offset voltage.

[0106] In the linear power supply circuit of the fourth configuration described above, the operational amplifier may include: a first input differential pair transistor connected to the control terminal of the first output transistor; a second input differential pair transistor connected to the control terminal of the second output transistor; and a current mirror circuit configured to supply a first current to the first input differential pair transistor and a second current, which is a mirror current of the first current, to the second input differential pair transistor. The input offset voltage can be generated by using MOS transistors as both the first and second input differential pair transistors and giving the MOS transistors different channel width to channel length ratios, or by giving the first and second currents different values. (Fifth Configuration)

[0107] Using the linear power supply circuit of the fifth configuration described above, the input offset voltage can be easily and accurately set to the design value.

[0108] The linear power supply circuit of any of the first to fifth configurations described above may further include: a resistor (82) between the control terminals of the first output transistor and the second output transistor; and a capacitor (83) with one terminal connected to the input terminal and the other terminal connected to the connection node between the resistor and the control terminal of the second output transistor. (Sixth Configuration)

[0109] Using the linear power supply circuit of the sixth configuration described above, phase compensation can be achieved without a significant increase in circuit area.

[0110] In the linear power supply circuit of the sixth configuration described above, the capacitor may be a parasitic capacitor of the second output transistor. (Seventh Configuration)

[0111] By utilizing the linear power supply circuit configured in the seventh way described above, the increase in circuit area can be suppressed more effectively.

[0112] In the linear power supply circuit of the sixth or seventh configuration described above, the capacitance value of the capacitor is higher than the capacitance value of the capacitor (CPD) between the first terminal of the output transistor connected to the input terminal and the control terminal of the first output transistor. (Eighth configuration)

[0113] Phase compensation can be easily achieved using the linear power supply circuit configured in the eighth step described above.

[0114] In the linear power supply circuit of any of the sixth to eighth configurations described above, the capacitor may include a capacitance different from the parasitic capacitance present between the first terminal connected to the input terminal and the control terminal of the second output transistor. (Ninth Configuration)

[0115] Using the linear power supply circuit configured in the ninth step described above, the capacitance value of the capacitor can be easily adjusted.

[0116] In any of the linear power supply circuits of the first to ninth configurations described above, the first output transistor and the second output transistor may have different sizes. (Tenth Configuration)

[0117] Using the linear power supply circuit configured in the tenth configuration described above, the current flowing through the first and second output transistors can be made to be different.

[0118] In the linear power supply circuit of the tenth configuration described above, the size of the second output transistor can be larger than the size of the first output transistor. (Eleventh configuration)

[0119] Using the linear power supply circuit configured in the eleventh configuration described above, the current through the second output transistor can be made higher than the current through the first output transistor.

[0120] In any of the linear power supply circuits described in the first to eleventh configurations above, the output stage can be configured as a PMOS source-grounded circuit. (Twelfth Configuration)

[0121] By utilizing the linear power supply circuit configured in the twelfth step above, high voltage gain can be obtained in the output stage.

[0122] According to another aspect of the disclosure herein, a vehicle includes the linear power supply circuit of any of the first to twelfth configurations described above. (Thirteenth Configuration)

[0123] Using the vehicle configured as described in the thirteenth section, overshoot in the output voltage of the linear power supply circuit can be suppressed.

[0124] List of reference numerals

[0125] 1 First output transistor

[0126] 2 drives

[0127] 3. Reference Voltage Generator

[0128] 4 and 5 resistors

[0129] 6 output capacitors

[0130] 7 load

[0131] 8-phase compensation circuit

[0132] 21, 21' differential amplifier

[0133] 22' capacitor

[0134] 23PMOSFET (An example of a converter)

[0135] 23'NMOSFET (Another example of a converter)

[0136] 24 Current Amplifier

[0137] 81 Second Output Transistor

[0138] 82 resistor

[0139] 83 Capacitor

[0140] 84 operational amplifier

[0141] 84A Input Offset Voltage

[0142] T1 Input Terminal

[0143] T2 output terminal

[0144] Vehicle X

Claims

1. A linear power supply circuit, comprising: An output stage, located between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied, includes a first output transistor and a second output transistor connected in parallel with each other. A driver configured to drive the first output transistor and the second output transistor based on the difference between a voltage based on the output voltage and a reference voltage; as well as A potential difference suppressor, configured to suppress the potential difference between the control terminals of the first output transistor and the second output transistor. Wherein, the control terminal of the first output transistor is the terminal to which the signal driving the first output transistor is supplied, and The control terminal of the second output transistor is the terminal to which the signal driving the second output transistor is supplied.

2. The linear power supply circuit according to claim 1, wherein... The potential difference suppressor is configured to Monitor the voltage difference between the voltage at the control terminal of the first output transistor and the voltage at the control terminal of the second output transistor. If the voltage difference is equal to or greater than a predetermined value, a control signal is output to control at least one of the voltage at the control terminal of the first output transistor and the voltage at the control terminal of the second output transistor, so as to reduce the potential difference between the control terminal of the first output transistor and the control terminal of the second output transistor.

3. The linear power supply circuit according to claim 2, wherein... The potential difference suppressor includes an operational amplifier, and The operational amplifier outputs the control signal.

4. The linear power supply circuit according to claim 3, wherein... The operational amplifier has an input offset voltage. The non-inverting input terminal of the operational amplifier is connected to the control terminal of the first output transistor, and The inverting input terminal and output terminal of the operational amplifier are connected to the control terminal of the second output transistor.

5. The linear power supply circuit according to claim 4, wherein... The operational amplifier includes: A first input differential pair transistor, the first input differential pair transistor being connected to the control terminal of the first output transistor; The second input differential pair transistor is connected to the control terminal of the second output transistor; as well as A current mirror circuit is configured to supply a first current to the first input differential pair transistor and a second current, which is a mirror current of the first current, to the second input differential pair transistor. The input offset voltage is generated by any of the following: By using MOS transistors as the first input differential pair transistor and the second input differential pair transistor, and giving the MOS transistors different channel width to channel length ratios, or By giving the first current and the second current different values.

6. The linear power supply circuit according to any one of claims 1 to 5, further comprising: A resistor located between the control terminal of the first output transistor and the control terminal of the second output transistor; as well as A capacitor, one terminal of which is connected to the input terminal, and the other terminal of which is connected to the connection node between the resistor and the control terminal of the second output transistor.

7. The linear power supply circuit according to claim 6, wherein... The capacitor is a parasitic capacitor of the second output transistor.

8. The linear power supply circuit according to claim 6, wherein... The capacitance value of the capacitor is higher than the capacitance value of the capacitor between the first terminal of the output transistor connected to the first terminal of the input terminal and the control terminal of the first output transistor.

9. The linear power supply circuit according to claim 6, wherein, The capacitor includes a capacitance that is different from the parasitic capacitance present between the first terminal of the second output transistor connected to the input terminal and the control terminal of the second output transistor.

10. The linear power supply circuit according to any one of claims 1 to 5, wherein, The first output transistor and the second output transistor have different dimensions.

11. The linear power supply circuit according to claim 10, wherein... The size of the second output transistor is larger than the size of the first output transistor.

12. The linear power supply circuit according to any one of claims 1 to 5, wherein, The output stage is configured as a PMOS source-grounded circuit.

13. A vehicle comprising a linear power supply circuit according to any one of claims 1 to 12.

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