bump-mapped texture loop

Abstract

The present disclosure relates to methods and apparatuses for graphics processing, including devices such as GPUs. A device can determine whether to divide a thread group into a plurality of thread subgroups, each thread in the thread group being associated with a shader program. The device can also divide the thread group into the plurality of thread subgroups upon determining to divide the thread group into the plurality of thread subgroups. Further, the device can execute a segment of the shader program for each thread subgroup in the plurality of thread subgroups upon dividing the thread group into the plurality of thread subgroups.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 191,439, filed March 3, 2021, entitled “METHODS AND APPARATUS FOR INTRA-WAVE TEXTURE LOOPING”, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to processing systems, and more specifically, to one or more techniques for graphics processing. Background Technology

[0004] Computing devices typically perform graphics and / or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices can include, for example, computer workstations, mobile phones (e.g., smartphones), embedded systems, personal computers, tablet computers, and video game consoles. A GPU is configured to execute a graphics processing pipeline comprising one or more processing stages that work together to execute graphics processing commands and output frames. The CPU can control the operation of the GPU by issuing one or more graphics processing commands to it. Modern CPUs are typically capable of executing multiple applications simultaneously, each of which may require the GPU during execution. A display processor is configured to convert digital information received from the CPU into analog values ​​and can issue commands to a display panel to display visual content. Devices that provide content for visual presentation on a display can utilize a GPU and / or a display processor.

[0005] The device's GPU can be configured to execute processes in the graphics processing pipeline. Furthermore, a display processor or display processing unit (DPU) can be configured to execute display processing processes. However, with the advent of wireless communication and small handheld devices, the demand for improved graphics or display processing is increasing. Summary of the Invention

[0006] The following is a simplified outline of one or more aspects to provide a basic understanding of them. This outline is not a comprehensive overview of all anticipated aspects, nor is it intended to identify key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] In this disclosure, a method, computer-readable medium, and apparatus are provided. The apparatus may be a graphics processing unit (GPU) or any apparatus capable of performing graphics processing. The apparatus may determine whether to divide a thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program. The apparatus may also determine whether consecutive instructions in the instruction set for the thread group are associated with the same surface. Furthermore, the apparatus may divide the thread group into multiple thread subgroups when it is determined that the thread group should be divided into multiple thread subgroups. The apparatus may also insert a loop marker for each of the multiple thread subgroups based on a segment of the shader program. Furthermore, the apparatus may execute a segment of the shader program for each of the multiple thread subgroups when the thread group is divided into multiple thread subgroups, wherein the segment of the shader program can complete the execution of a thread subgroup before the execution of a subsequent thread subgroup begins. The apparatus may also store the memory usage of the shader program segment for each of the multiple thread subgroups in a cache.

[0008] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of this disclosure will be apparent from the description, drawings, and claims. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example of a system for generating data based on one or more techniques disclosed herein.

[0010] Figure 2 Example GPUs illustrating one or more techniques according to this disclosure.

[0011] Figure 3 This is a schematic diagram illustrating a mapping process for graphics processing according to one or more techniques disclosed herein.

[0012] Figure 4 This is a schematic diagram illustrating a mapping process for graphics processing according to one or more techniques disclosed herein.

[0013] Figure 5 This is a schematic diagram illustrating a mapping process for graphics processing according to one or more techniques disclosed herein.

[0014] Figure 6 This is a communication flow diagram illustrating example communication between GPU components and cache according to one or more techniques disclosed herein.

[0015] Figure 7 This is a flowchart of an example method for graphical processing according to one or more techniques of this disclosure. Detailed Implementation

[0016] In graphics processing, specific types of shading or texture instructions can fetch data using a specific number of cache lines. Ideally, the number of cache lines used for shading or texture instruction execution can be less than the size of the cache. However, the corresponding cache size may not be large enough to hold all the fetched data for a shading or texture instruction, so previously fetched data may be overwritten. Therefore, the next instruction may not be able to utilize some data fetched by a previous instruction. Consequently, previously fetched data in the cache may not be reused by subsequent instructions, potentially leading to data being fetched from system memory instead of the cache. Thus, subsequent instructions may not be able to utilize previously fetched data. For example, performing a full wave for a single texture fetch instruction can lead to inefficient use of the texture cache and cache jitter, such as data for a subsequent texture fetch instruction being overwritten by the current texture fetch instruction. A aspect of this disclosure can perform a portion of the texture fetch operation before performing the entire texture fetch operation. By doing so, the aspect of this disclosure can utilize MIP mapping more efficiently, and adjacent pixels may not be scattered in texture space. The aspect of this disclosure can also provide efficient texture cache utilization and reduce the number of cache misses or cache jitter. Furthermore, aspects of this disclosure can allow subsequent texture instructions to utilize previously fetched data at a cache, for example, without needing to fetch data from system memory. Therefore, aspects of this disclosure can reduce or mitigate the number of times specific data (e.g., texture data) is fetched from system memory, i.e., even with a small cache size. Additionally, aspects of this disclosure can provide a looping mechanism spanning multiple texture fetch instructions, which operates on a portion of the wave during each loop iteration. Therefore, aspects of this disclosure can utilize hardware-assisted texture loops controlled by the compiler or graphics shader.

[0017] The various aspects of the systems, apparatus, computer program products, and methods will be described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided to make this disclosure comprehensive and complete, and to fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the systems, apparatus, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other aspects of this disclosure. For example, an apparatus or method may be implemented using any number of the aspects set forth herein. Furthermore, the scope of this disclosure is intended to cover such apparatuses or methods implemented using structures, functions, or structures and functions other than those set forth herein or different from the aspects set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0018] While various aspects are described herein, many variations and arrangements of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of the aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to any particular benefit, use, or objective. Rather, the aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transport protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and accompanying drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0019] Several aspects are presented with reference to various apparatuses and methods. These apparatuses and methods are described in detail below and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively, "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0020] For example, an element, any part of an element, or any combination of elements can be implemented as a "processing system" that includes one or more processors (also referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description languages, or others, software can be broadly interpreted as representing instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, executing threads, procedures, functions, etc. The term application can refer to software. As described herein, one or more technologies can refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored on memory, such as the processor's on-chip memory, system memory, or any other memory. The hardware described herein (e.g., a processor) may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. For instance, the hardware may access code from memory and execute the code accessed from memory to perform one or more technologies described herein. In some instances, components are identified in this disclosure. In these instances, a component may be hardware, software, or a combination thereof. A component may be a single component or a subcomponent of a single component.

[0021] Therefore, in one or more examples described herein, the functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored or encoded as one or more instructions or code on a computer-readable medium. A computer-readable medium includes a computer storage medium. The storage medium can be any available medium accessible to a computer. By way of example, and not limitation, such a computer-readable medium can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disc storage, magnetic disk storage, other magnetic storage devices, combinations of computer-readable media of the types described above, or any other medium that can be used to store computer-executable code having instructions or data structures accessible to a computer.

[0022] Generally, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on processing units (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a GPU). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other exemplary benefits are described throughout this disclosure.

[0023] As used herein, instances of the term "content" can refer to "graphic content," "image," or vice versa. This is true regardless of whether the term is used as an adjective, noun, or other textual expression. In some instances, as used herein, the term "graphic content" can refer to content produced by one or more processes in a graphics processing pipeline. In some instances, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some instances, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0024] In some instances, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. Graphical content can be processed to become display content. For example, a graphics processing unit can output graphical content (e.g., frames) to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content, such as one or more frames, from the buffer and perform one or more display processing techniques on it to generate display content. For example, a display processing unit can be configured to perform compositing on one or more rendering layers to generate frames. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers together into a single frame. A display processing unit can be configured to perform scaling on frames, such as up scaling or down scaling. In some instances, a frame can refer to a layer. In other instances, a frame can refer to two or more layers that have been blended together to form a frame, i.e., a frame comprises two or more layers, and frames comprising two or more layers can subsequently be blended.

[0025] Figure 1This is a block diagram illustrating an example content generation system 100 configured to implement one or more technologies of this disclosure. The content generation system 100 includes a device 104. Device 104 may include one or more components or circuitry for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a System-on-a-Chip (SOC). Device 104 may include one or more components configured to perform one or more technologies of this disclosure. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, device 104 may include several optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation thereon. In other examples, the first and second displays may receive the same frames used for rendering on them. In further examples, the results of graphics processing may not be displayed on the devices; for example, the first and second displays may not receive any frames used for rendering on them. Instead, the frames or graphics processing results may be transmitted to another device. In some respects, this can be referred to as segmented rendering.

[0026] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in a graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor, such as display processor 127, to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being rendered by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise render the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0027] External memory (e.g., system memory 124) can be accessed by processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 can be configured to read from and / or write to external memory (e.g., system memory 124). Processing unit 120 and content encoder / decoder 122 can be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 can be communicatively coupled to each other via a bus or different connections.

[0028] Content encoder / decoder 122 can be configured to receive graphic content from any source (e.g., system memory 124 and / or communication interface 126). System memory 124 can be configured to store received, encoded, or decoded graphic content. Content encoder / decoder 122 can be configured to receive, for example, encoded or decoded graphic content in the form of encoded pixel data from system memory 124 and / or communication interface 126. Content encoder / decoder 122 can be configured to encode or decode any graphic content.

[0029] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media or optical storage media or any other type of memory.

[0030] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not implemented in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is non-removable or that its contents are static. As an example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may not be removable from device 104.

[0031] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may be otherwise incorporated into a peripheral device configured to interact with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, processing unit 120 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute the instructions in hardware to perform the technology of this disclosure. Any of the foregoing items, including hardware, software, and combinations of hardware and software, may be considered as one or more processors.

[0032] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and the instructions may be executed in hardware using one or more processors to perform the technology of this disclosure. Any of the foregoing items, including hardware, software, combinations of hardware and software, etc., can be considered as one or more processors.

[0033] In some aspects, the content generation system 100 may include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Furthermore, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or location information. The transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such an example, the transceiver 132 may be configured to perform any of the receiving and / or transmitting functions described herein with respect to device 104.

[0034] Refer again Figure 1 In some aspects, processing unit 120 may include a determining component 198 configured to determine whether to divide a thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program. The determining component 198 may also be configured to determine whether consecutive instructions in the instruction set for the thread group are associated with the same surface. The determining component 198 may also be configured to divide the thread group into multiple thread subgroups when it is determined that the thread group should be divided into multiple thread subgroups. The determining component 198 may also be configured to insert a loop marker for each of the multiple thread subgroups based on shader program segmentation. The determining component 198 may also be configured to execute shader program segmentation for each of the multiple thread subgroups when the thread group is divided into multiple thread subgroups, wherein shader program segmentation can complete the execution of a thread subgroup before execution of subsequent thread subgroups begins. The determining component 198 may also be configured to store the memory usage of the shader program segmentation for each of the multiple thread subgroups in a cache. Although the following description may focus on graphics processing, the concepts described herein can be applied to other similar processing techniques.

[0035] As described herein, a device (e.g., device 104) can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation or mainframe computer), terminal product, device, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch, augmented reality device or virtual reality device), non-wearable device, display or display device, television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein. The processes described herein may be described as being performed by a specific component (e.g., GPU), but in further embodiments, other components (e.g., CPU) may be used, consistent with the disclosed embodiments.

[0036] GPUs can process various types of data or data packets within the GPU pipeline. For example, in some aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. Context register packets can be a set of global state information, such as information about global registers, shaders, or constant data, which can regulate how the graphics context will be processed. For example, a context register packet may include information about the color format. In some aspects of context register packets, there may be bits indicating which workload belongs to the context register. Furthermore, multiple functions or programs can run simultaneously and / or in parallel. For example, a function or program may describe a specific operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0037] Context states can be used to determine how individual processing units (such as vertex fetchers (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate, and / or in what modes they operate. For this purpose, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline, such as vertex or pixel workloads, based on the context register definitions of modes or states. Certain processing units (such as VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Furthermore, the workload corresponding to a mode or state can follow the changing mode or state.

[0038] Figure 2 An example GPU 200 is illustrated according to one or more technologies based on this disclosure. For example... Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-processing engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a renderer backend (RB) 236, a level 2 (L2) cache (UCHE) 238, and system memory 240. Although Figure 2 The GPU 200 is shown to include processing units 220-238, but the GPU 200 may include many additional processing units. Furthermore, processing units 220-238 are merely examples, and according to this disclosure, the GPU may use any combination or order of processing units. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0039] like Figure 2 As shown, the GPU can use a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). The CP 210 can then send the context register packet 260 or the draw call data packet 212 to a processing unit or block in the GPU via a separate path. Furthermore, the command buffer 250 can alternate between different states of the context registers and draw calls. For example, the command buffer can be constructed as follows: context register of context N, draw call of context N, context register of context N+1, and draw call of context N+1.

[0040] Some types of graphics processing units (GPUs) can utilize graphics shaders to access or fetch different textures. For example, some types of graphics shaders can access multiple textures within one or more pixel groups. Graphics shaders can also utilize different texture fetch operations (such as Texture_Fetch) to access multiple textures within a single pixel group. For example, a graphics shader can utilize the following operations: (1) Texture_Fetch R0.xyzw <- Texture(i1,j1,Tex1); and (2) Texture_Fetch R1.xyzw <- Texture(i2,j2,Tex2). In some cases, light textures or cubemap textures can be fetched after the "material" fetch. Furthermore, the GPU can include a separate cache associated with these textures, such as a texture cache.

[0041] Furthermore, some types of GPUs can perform Single Instruction / Multiple Data (SIMD) operations, such as using SIMD vectors. In some instances, SIMD vectors may be referred to as waves, wave operations, warps, or warp operations. A wave can be a set of pixels executed via a series of instructions with locked steps. The wave or warp can correspond to the width of the SIMD vector. For example, a typical wave size for a SIMD vector can include several threads or pixels, such as between 32 and 128 threads or pixels. Some architectures may also utilize a lower number of threads or pixels, such as 16 threads or pixels. These threads or pixels can run with locked steps, allowing a single instruction to be executed for each thread or pixel.

[0042] In graphics processing, mipmaps (or pyramids) are sequences of images used to represent an image or image resolution. Each mipmap in the sequence can be a pre-defined or optimized image, which can be a progressively decreasing resolution representation of a previous image. For example, the height and / or width of each image (i.e., layer) in a mipmap can be smaller than the previous layer by a specific amount, such as a power of 2. Mipmaps are associated with several anticipated benefits, such as improved rendering speed and / or reduced aliasing artifacts. For example, high-resolution mipmap images can be used for high-density samples, such as objects close to the camera, while low-resolution images can be used for low-density samples, such as objects far from the camera.

[0043] In some respects, the mipmapping process can result in mapped pixels being close to each other, i.e., separated by no more than one texture in texture space. Thus, when the wave is executed, the textured pixels (i.e., texels) generated by the wave can be localized, allowing locality to occur within a single instruction. Consequently, multiple texels can be stored in the cache simultaneously, leading to a suitable hit rate at the cache (e.g., a texture cache). When moving to the next instruction, a different texture may be used, thus texture reuse may not be necessary.

[0044] The MIP mapping aspect ensures that wave occupancy in texture space is similar in size to pixel occupancy in screen space. For example, a texture region for a wave can easily fit into several cache lines (e.g., two cache lines), which can lead to a similar number of cache misses (e.g., two misses), i.e., when fetched data is overwritten or thrown out of the cache due to subsequent fetches. Furthermore, subsequent texture fetches may come from different surfaces and can use different cache lines (i.e., potentially causing previous cache lines to be evicted).

[0045] Some aspects of graphics processing allow one texture fetch operation to be executed sequentially, for example, to avoid cache jitter. For instance, in the case of common MIP-mapped texture fetching, a full wave (e.g., a 64 or 128 pixel wave) can be fetched before moving to the next fetch instruction, because neighboring pixels in the wave can be localized in texture space. Similarly, a specific instruction (Texture_Fetch R0.xyzw<-Texture(i2,j2,Tex2)) can be executed before another instruction (Texture_Fetch R1.xyzw<-Texture(i2,j2,Tex2)) is executed.

[0046] Figure 3 This is a schematic diagram 300 illustrating a mapping process used for graphics processing, including mapping waves onto a textured surface in memory. For example... Figure 3 As shown, schematic 300 includes a wave 310 (e.g., a 64-pixel wave) and a textured surface 320 (e.g., corresponding to two cache lines). More specifically, Figure 3 This illustrates the mapping from wave 310 to texture surface 320 and the two cache lines. For example... Figure 3 As shown, some types of graphics shaders (e.g., graphics shaders for post-processing) can utilize sequential acquisition of the same textured surface. In these types of graphics shaders, MIP mapping may not be used. For example, as... Figure 3 As shown, a single wave can map to a very large area, which may not fit into the local cache.

[0047] Some downsampling operations can utilize several texture fetch operations, which are related to the size of the downsampling operation. For example, a 4x4 downsampling operation can utilize 16 texture fetch instructions: (1) Texture_Fetch R0.xyzw<-Texture(i1,j1,Tex1); (2) Texture_Fetch R1.xyzw <-Texture(i1+1,j1,Tex1); ... (16) Texture_Fetch R15.xyzw<-Texture(i1+3,j1+3,Tex1). These types of downsampling operations (e.g., downsampling for filtering operations) can have a large number of cache hits moving between consecutive instructions. This may be true if the entire occupancy from the first instruction fits in the cache. If the cache holds a limited number of lines, such as 16 lines, there may be a large number of cache misses, i.e., when fetched data is overwritten or evicted from the cache due to subsequent fetches. When this occurs, data may need to be fetched from main memory, resulting in more traffic from main memory and increased memory bandwidth. Therefore, there are texture instructions that require a significantly larger cache size compared to the cache size allowed in the cache.

[0048] Figure 4 This is a schematic diagram 400 illustrating a mapping process used for graphics processing, which includes mapping waves onto a textured surface in memory. For example... Figure 4 As shown, schematic 400 includes a wave 410 (e.g., a 64-pixel wave) and a textured surface 420 (e.g., corresponding to 24 cache lines). More specifically, Figure 4 This illustrates the mapping from wave 410 to texture surface 420 and 24 cache lines. Figure 4 This demonstrates the locality between different instructions in mapping operations (e.g., filtering or downsampling operations). For example, a high-definition texture can be converted to a standard-definition screen resolution. Figure 4 It also shows that the cache can hold 16 lines, but instructions from the wave can correspond to 24 cache lines.

[0049] like Figure 4As shown, in a 64-pixel wave 410, each pixel may be acquiring a 4x4 occupancy. Therefore, a 64-pixel wave can be mapped to a 256x256 area. Each of the 24 individual blocks in the texture surface 420 can correspond to a single cache line, and each of the 24 cache lines can hold 16 texture pixels or texels, where a single pixel is mapped to 16 texels. Therefore, texels can correspond to information stored in the texture cache, and this information can be used to shade pixels. In some cases, the cache may not be able to hold all the texture pixels or texels for each cache line, so the first line written to the cache may be overwritten by subsequent cache lines. Figure 4 As shown, the cache can hold 16 lines, but an instruction may correspond to 24 cache lines. Therefore, when fetching the 17th cache line, the first cache line may have been overwritten or discarded. Consequently, when fetching data for the first cache line, it may be necessary to fetch that data again from system memory, since the data is no longer in the cache.

[0050] like Figure 4 As shown, specific types of shading or texture instructions can fetch data using a specific number of cache lines. Ideally, the number of cache lines used for shading or texture instruction execution should be less than the size of the cache. However, the corresponding cache size may be insufficient to hold all the data fetched for a shading or texture instruction, so previously fetched data may be overwritten. Consequently, the next instruction may not be able to utilize some data fetched by a previous instruction. Therefore, data fetched into the cache by a previous instruction may not be reused by subsequent instructions, potentially leading to data being fetched from system memory instead of the cache. Thus, subsequent instructions may not be able to utilize previously fetched data.

[0051] As noted above, there are situations where performing one texture fetch operation followed by another may overwrite data, such as post-processing filtering operations. In these cases, MIP mapping may not be used, and adjacent pixels may be scattered across the texture space. Furthermore, sequential texture fetch instructions within a single pixel may be more localized than those between pixels. Performing a full fetch for a single texture fetch instruction can lead to inefficient texture cache usage and cache jitter, for example, data for subsequent texture fetch instructions being overwritten by the current one. For instance, if there are 16 texture fetches in a texture cache line, a single texture fetch might be possible because adjacent texture pixels may not be able to use other texture fetches. Therefore, adjacent texture pixels may be forced to fetch their own texture cache lines. Consequently, the amount of reuse between texture instructions may be high, but the reuse within texture instructions is low.

[0052] Based on the above, performing a portion of the texture fetch operation before executing the entire texture fetch operation can be beneficial. This also facilitates efficient texture cache usage and reduces the number of cache misses or cache thrashing. Furthermore, it can be beneficial that subsequent texture instructions can utilize previously fetched data at the cache, for example, without needing to fetch data from system memory. For instance, it is beneficial to provide a mechanism that spans multiple texture fetch instructions, operating on a portion of the wave during each loop iteration.

[0053] The aspects of this disclosure can perform a portion of the texture fetch operation before executing the entire texture fetch operation. By doing so, the aspects of this disclosure can utilize MIP mapping more efficiently, and adjacent pixels are not scattered in the texture space. The aspects of this disclosure can also provide efficient texture cache usage and reduce the number of cache misses or cache jitter. Furthermore, the aspects of this disclosure can allow subsequent texture instructions to utilize previously fetched data at the cache, for example, without needing to fetch data from system memory. Therefore, the aspects of this disclosure can reduce or mitigate the number of times specific data (e.g., texture data) is fetched from system memory, i.e., even with a small cache size. Furthermore, the aspects of this disclosure can provide a looping mechanism across multiple texture fetch instructions, which operates on a portion of the wave during each loop iteration. Therefore, the aspects of this disclosure can utilize hardware-assisted texture loops controlled by the compiler or graphics shader.

[0054] In this disclosure, instructions can be fetched across multiple textures to utilize a hardware loop mechanism. During each loop iteration, this hardware loop mechanism can operate on a portion of a pixel wave. By doing so, this allows for full utilization of pixel locality, i.e., intra-pixel locality. Furthermore, pixel locality can be fully utilized using texture caches of any size (e.g., smaller texture caches).

[0055] In some cases, the decision of whether to execute an in-wave loop can be made by the compiler. For this purpose, the compiler can detect whether sequential texture fetch instructions point to the same surface. In some respects, in-wave loop operations can be an optimization that preserves functionality regardless of whether new texture loop instructions are utilized. Furthermore, the functionality of in-wave loop operations can be preserved regardless of whether they are implemented in any particular hardware component.

[0056] As noted above, aspects of this disclosure can utilize intra-wave texture loop operations, such as compiler-controlled intra-wave texture loop hardware. For example, aspects of this disclosure can enable the compiler to determine whether consecutive texture instructions correspond to the same texture surface. If consecutive texture instructions correspond to the same texture surface, the compiler can insert a texture loop marker, such as a `Tex_Loop` marker, at that location. This texture loop marker can indicate the length of the intra-wave loop used for accessing the same surface. The hardware can then loop within a sub-wave, which can alleviate the burden on the local cache. By doing so, aspects of this disclosure can reduce cache footprint and increase the number of cache hits, i.e., if the entire region does not fit within the cache size.

[0057] In one example, aspects of this disclosure may utilize a texture loop along with a specific number of texture fetch instructions. For example, aspects of this disclosure may utilize the following operations: (0) Tex_Loop 16; (1) Texture_Fetch R0.xyzw<-Texture(i1,j1,Tex1); (2) Texture_Fetch R1.xyzw<-Texture(i1+1,j1,Tex1); ... (16) Texture Fetch R15.xyzw<-Texture(i1+3,j1+3,Tex1). In some cases, the texture loop (e.g., Tex_Loop 16) may be a new instruction.

[0058] Figure 5 This is a schematic diagram 500 illustrating a mapping process for graphics processing according to one or more techniques of this disclosure, the mapping process including mapping waves onto a textured surface in memory. For example... Figure 5 As shown, schematic diagram 500 includes wave 510, for example, a 64-pixel wave with four different 16-pixel sub-waves. For example, wave 510 includes sub-waves 512, 514, 516, and 518, each sub-wave being 16 pixels. Schematic diagram 500 also includes textured surfaces 520, for example, corresponding to eight (8) cache lines. Figure 5 This describes the mapping of wave 510 (including sub-waves 512, 514, 516, and 518) to texture surface 520 and eight buffer lines or sub-waves. Each sub-wave 512, 514, 516, and 518 can be individually mapped to texture surface 520.

[0059] like Figure 5As shown, aspects of this disclosure can divide a pixel wave (e.g., a wave 510 comprising 64 pixels) into multiple pixel sub-waves, such as sub-waves 512, 514, 516, and 518 each comprising 16 pixels. Therefore, the occupancy for each 16 pixels of a sub-wave is less than the occupancy for the 64 pixels of wave 510. Instructions can then be executed for each pixel sub-wave. Therefore, instructions are not executed for the entire wave because the cache size might be too small to store data for the entire pixel wave. However, as the pixel wave size decreases, i.e., is divided into 16-pixel sub-waves, the amount of cache lines can be adapted to the size of each sub-wave. Figure 5 As shown, eight (8) cache lines can be fetched, and then 16 instructions can be processed without overwriting any data fetched by previous instructions. By doing so, subsequent instructions for the subwave do not need to fetch any data from system memory, because all data for the instruction is stored in the cache without any overwriting. Therefore, each subsequent instruction can receive the full benefits of the cache.

[0060] Figure 5 This demonstrates that the instructions for each subwave (e.g., subwave 512) can fit within the cache size. Therefore, subsequent instructions for subwave 512 do not need to fetch any data from system memory, as all data for the instructions for subwave 512 is stored in the cache without any overwriting. Thus, each subsequent instruction for subwave 512 can receive the full benefits of the cache. Once the texels or data for subwave 512 are stored in the cache and subsequent instructions are processed, the next subwave, such as subwave 514, can be processed. This process can continue using pixels for subwaves 516 and 518 until all instructions for each subwave have been processed. Therefore, dividing a wave into subwaves allows for the use of a smaller cache with the benefit of instruction reuse, which would otherwise be impossible if the entire wave were processed at once. Thus, dividing pixel waves or thread waves into subwaves allows a smaller cache to provide cache reuse between consecutive instructions.

[0061] This disclosure allows determining whether the amount of data required to execute a specific instruction (e.g., a segmentation of a shader program) exceeds the size of a cache. Furthermore, this disclosure allows determining whether a pixel wave is divided into multiple pixel sub-waves. If so, this disclosure allows dividing a pixel wave (i.e., a thread group) into multiple pixel sub-waves (i.e., multiple thread subgroups). After this, this disclosure allows the execution of specific instructions, such as segments of a shader program.

[0062] Furthermore, aspects of this disclosure can determine whether a set of texture captures corresponds to the same texture surface. For example, the compiler can identify when a set of texture captures corresponds to the same surface. If a set of texture captures corresponds to the same texture surface, there is locality between texture instructions for a particular pixel. Therefore, there is a higher probability of reusing data stored in the cache between consecutive instructions. This is a good indication that pixel waves should be divided into pixel sub-waves such that the memory footprint of the shader program segmented for the instruction does not exceed the size of the cache.

[0063] Some aspects of this disclosure can provide hardware-assisted, compiler-generated wavelet operations. Therefore, the compiler can determine whether a wavelet operation is beneficial, i.e., whether it reduces the amount of power used at the GPU or improves GPU performance. Thus, the compiler can determine whether consecutive texture instructions correspond to the same texture surface. If so, the compiler can utilize texture loop hardware that allows the compiler to perform wavelet operations across multiple texture instructions. Therefore, if the compiler determines that consecutive texture instructions correspond to the same texture surface, the compiler can perform segmentation of the shader program for multiple texture instructions. Furthermore, aspects of this disclosure can insert a texture loop marker when it is determined that consecutive texture instructions correspond to the same texture surface. By doing so, the hardware can detect that a wavelet mode should be initiated for the next set of instructions.

[0064] There can be many benefits or advantages to utilizing the aforementioned looping mechanisms across multiple texture fetch instructions. In one example (e.g., 4x4 downsampling post-processing), there can be a specific amount of performance benefit or power reduction, such as a 50% performance benefit or power reduction. Furthermore, the amount of texture cache misses can be reduced by a specific factor, such as factor eight (8). In addition, these looping mechanisms can be utilized in conjunction with software operations, in addition to hardware operations. Furthermore, aspects of this disclosure can reduce cache footprint and increase cache hits.

[0065] Figure 6 This is a schematic diagram 600 illustrating a communication process using graphical processing based on one or more techniques according to this disclosure. For example... Figure 6 As shown, schematic diagram 600 includes example communication between GPU component 602 (e.g., graphics shader or compiler) and cache 604 (e.g., texture cache at GPU) according to one or more techniques of this disclosure.

[0066] At 610, GPU component 602 can determine whether to divide a thread group (e.g., wave 510) into multiple thread subgroups (e.g., sub-waves 512, 514, 516, 518), each thread in the thread group being associated with a shader program. In some aspects, the thread group can be a thread wave, such as wave 510, and the multiple thread subgroups can be multiple thread sub-waves, such as sub-waves 512, 514, 516, 518. The thread group can be at least one of a pixel group (e.g., wave 510), a vertex group, or a work item group. Furthermore, the pixel group (e.g., wave 510) can be a texture pixel group or a texels group. The determination of whether to divide the thread group into multiple thread subgroups can be performed by the compiler.

[0067] At 620, GPU component 602 can determine whether consecutive instructions in an instruction set for a thread group (e.g., wave 510) are associated with the same surface. This instruction set can be texture instructions, and the same surface can be a textured surface. Furthermore, the instruction set can correspond to downsampling instructions.

[0068] At 630, GPU component 602 can divide a thread group (e.g., wave 510) into multiple thread subgroups (e.g., sub-waves 512, 514, 516, 518) when determining to divide the thread group into multiple thread subgroups.

[0069] At 640, GPU component 602 can insert a loop marker for each of the multiple thread subgroups (e.g., subgroups 512, 514, 516, 518) based on the segmentation of the shader program. The loop marker can define the range of the shader program segment. This range can include the start and end of the shader program segment. Furthermore, the loop marker can be associated with an initiation mechanism or a hardware initiation mechanism.

[0070] At 650, GPU component 602 can, when dividing a thread group into multiple thread subgroups, execute segments of the shader program for each of the multiple thread subgroups (e.g., subgroups 512, 514, 516, 518), wherein the segmentation of the shader program can complete the execution of a thread subgroup before execution for a subsequent thread subgroup begins. The segmentation of the shader program for each of the multiple thread subgroups (e.g., subgroups 512, 514, 516, 518) can be executed by a graphics shader in the graphics processing unit (GPU).

[0071] In some respects, the memory footprint 662 of the shader program segment for each of the multiple thread subgroups (e.g., wavelets 512, 514, 516, 518) can be associated with the size of a cache (e.g., cache 604). The memory footprint of all segments of the shader program for the thread groups (e.g., wavelets 512, 514, 516, 518) can exceed the size of the cache (e.g., cache 604). Furthermore, the cache (e.g., cache 604) can be a texture cache or a Level 1 (L1) texture cache.

[0072] At 660, GPU component 602 may store in cache 604 the memory footprint 662 of the shader program segment for each of the multiple thread subgroups (e.g., subgroups 512, 514, 516, 518).

[0073] Figure 7 This is a flowchart 700 of an example method for graphics processing according to one or more techniques disclosed herein. The method can be performed by (e.g., a graphics processing device, GPU or other graphics processor, graphics shader, compiler, GPU pipeline, wireless communication device, and / or can perform a combination of) Figures 1-6 The example uses any device that performs graphics processing.

[0074] At 702, the device can determine whether to divide the thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program, such as in conjunction with... Figures 1-6 The example described in the text. For instance, GPU component 602 can determine whether to divide a thread group into multiple thread subgroups, each thread in which is associated with a shader program. Furthermore, processing unit 120 can execute 702.

[0075] In some respects, a thread group can be a thread wave, and multiple thread subgroups can be multiple thread subwaves, such as combining... Figures 1-6 The example described in the text. A thread group can be at least one of a pixel group, a vertex group, or a work item group, such as in combination. Figures 1-6 The example described in [the text]. Furthermore, pixel groups can be texture pixel groups or texels groups, as combined... Figures 1-6 The example described in [the document] illustrates this. The determination of whether to divide a thread group into multiple thread subgroups can be performed by the compiler, such as in conjunction with [other parameters]. Figures 1-6 The examples described in the text.

[0076] At 704, the device can determine whether consecutive instructions in a set of instructions for a thread group are associated with the same surface, such as in combination. Figures 1-6The example described in the text. For example, GPU component 602 can determine whether consecutive instructions in an instruction set for a thread group are associated with the same surface. Furthermore, processing unit 120 can execute 704. The instruction set can be textured instructions, and the same surface can be a textured surface, as combined... Figures 1-6 The example described in [the text]. Furthermore, the instruction set can correspond to downsampling instructions, such as those combined with [other instructions]. Figures 1-6 The examples described in the text.

[0077] At point 706, when determining to divide a thread group into multiple thread subgroups, the device can divide the thread group into multiple thread subgroups, such as in combination with... Figures 1-6 The example described in the text. For example, GPU component 602 can divide a thread group into multiple thread subgroups when it is determined that a thread group should be divided into multiple thread subgroups. Furthermore, processing unit 120 can perform 706.

[0078] At 708, the device can insert a loop marker for each of the multiple thread subgroups based on the segmentation of the shader procedure, such as combining... Figures 1-6 The example described in the text. For instance, GPU component 602 can insert a loop marker for each of multiple thread subgroups based on the segmentation of the shader program. Furthermore, processing unit 120 can execute 708. The loop marker can define the range of the segmentation of the shader program, such as in combination with... Figures 1-6 The example described in the text. This scope can include the beginning and end of a segment of the shader procedure, as in combination. Figures 1-6 The example described in [the document] further illustrates this. Additionally, the cycle marker can be associated with an initiation mechanism or a hardware initiation mechanism, such as in combination with [other mechanisms]. Figures 1-6 The examples described in the text.

[0079] At 710, the device can, when dividing a thread group into multiple thread subgroups, execute segments of the shader program for each of the multiple thread subgroups, wherein the segmentation of the shader program can complete the execution of a thread subgroup before execution for subsequent thread subgroups begins, as in combination with... Figures 1-6 The example described herein. For instance, GPU component 602 can execute segments of the shader program for each of the multiple thread subgroups when a thread group is divided into multiple thread subgroups. Furthermore, processing unit 120 can execute 710. The segments of the shader program for each of the multiple thread subgroups can be executed by a graphics shader in the graphics processing unit (GPU), as in combination with... Figures 1-6 The examples described in the text.

[0080] In some respects, the memory footprint of a segment of the shader program for each thread subgroup within multiple thread subgroups can be correlated with the size of the cache, such as by combining Figures 1-6 The example described in [the text] illustrates that the memory footprint of all segments of a thread group and shader program can exceed the size of the cache, as illustrated by [the example description]. Figures 1-6 The example described in the text. Furthermore, the cache can be a texture cache or a Level 1 (L1) texture cache, as combined with... Figures 1-6 The examples described in the text.

[0081] At 712, the device can store in the cache the segmented memory usage of the shader program for each of the multiple thread subgroups, such as in combination Figures 1-6 The example described in the text. For example, GPU component 602 can store the memory footprint of the shader program segments for each of the multiple thread subgroups in a cache. Furthermore, processing unit 120 can execute 712.

[0082] In this configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a graphics processor, a graphics shader, a compiler, or some other processor capable of performing graphics processing. In various aspects, the apparatus may be a processing unit 120 within device 104, or some other hardware within device 104 or another device. The apparatus may include units for determining whether to divide a thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program. The apparatus may further include units for dividing the thread group into multiple thread subgroups when it is determined that the thread group should be divided into multiple thread subgroups. The apparatus may further include units for executing segments of the shader program for each of the multiple thread subgroups when the thread group is divided into multiple thread subgroups. The apparatus may further include units for inserting loop markers for each of the multiple thread subgroups based on the segments of the shader program. The apparatus may further include units for determining whether consecutive instructions in an instruction set for a thread group are associated with the same surface. The device may further include units for storing in a cache the memory footprint of segments of the shader program for each of the multiple thread subgroups.

[0083] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the graphics processing techniques described herein can be implemented using GPUs, graphics processors, graphics shaders, compilers, or some other processor capable of performing graphics processing. This technique can also be implemented at a lower cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques of this invention can improve or accelerate data processing or execution. In addition, the graphics processing techniques of this invention can improve resource or data utilization and / or resource efficiency. Furthermore, aspects of this disclosure can utilize intratexture loops to improve memory bandwidth and / or reduce performance overhead at the GPU.

[0084] It is understood that the specific order or hierarchy of blocks in the disclosed process / flowchart is illustrative of the exemplary method. Based on design preferences, it is understood that the specific order or hierarchy of blocks in the process / flowchart can be rearranged. Furthermore, some blocks can be combined or omitted. The appended method claims present the elements of the blocks in an exemplary order, but are not intended to limit one to the specific order or hierarchy presented.

[0085] The foregoing description is provided to enable any person skilled in the art to implement the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein, unless otherwise specifically stated, the singular element referred to is not intended to mean "one and only one," but rather "one or more." The term "exemplary" as used herein means "as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as superior to or advantageous over other aspects.

[0086] Unless otherwise specified, the term "some" refers to one or more, and the term "or" may be interpreted as "and / or" unless the context indicates otherwise. Combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" include any combination of A, B, and / or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as "at least one of A, B, or C", "one or more of A, B, or C", "at least one of A, B, and C", "one or more of A, B, and C", and "A, B, C, or any combination thereof" may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, wherein any such combination may contain one or more members of A, B, or C. All structural and functional equivalents known or to be known hereafter by those skilled in the art to elements pervading all aspects of this disclosure are expressly incorporated herein by reference and are intended to be included in the claims. Furthermore, nothing disclosed herein is intended for public disclosure, whether or not such disclosure is expressly stated in the claims. Terms such as “module,” “mechanism,” “element,” and “device” are not substitutes for the word “unit.” Therefore, unless an element is explicitly stated using the phrase “unit for…,” no claim element should be construed as a unit plus a function.

[0087] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, then such function, processing unit, technique, or other module may be stored on or transmitted through a computer-readable medium as one or more instructions or code.

[0088] According to this disclosure, the term "or" may be replaced by "and / or" unless the context specifies otherwise. Furthermore, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not for others, the absence of such language in a feature where the context does not specify otherwise may be interpreted as implying such a meaning.

[0089] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” is used throughout this disclosure, these processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, then the function, processing unit, technique, or other module described herein may be stored on or transmitted via a computer-readable medium as one or more instructions or code. A computer-readable medium may include a computer data storage medium or a communication medium, including any medium that facilitates the transfer of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is non-transitory; or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described herein. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. The disks and optical discs used in this document include compact optical discs (CDs), laser discs, optical discs, digital versatile optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs copy data optically using lasers. Combinations of these products should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0090] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein can refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be fully implemented in one or more circuit or logic elements.

[0091] The techniques disclosed herein can be implemented in a wide variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or IC sets (e.g., chipsets). Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but are not necessarily required to be implemented through different hardware units. Rather, as described above, various units can be combined in any hardware unit or provided by a set of interoperable hardware units, including one or more processors as described above, combined with suitable software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above-described structures or any other structure suitable for implementing the techniques described herein. Furthermore, these techniques can be implemented entirely within one or more circuit or logic elements.

[0092] The following aspects are illustrative only and may be combined with other aspects or teachings described herein without limitation.

[0093] Aspect 1 is a method for graphics processing. The method includes determining whether to divide a thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program; dividing the thread group into multiple thread subgroups when it is determined to do so; and, when the thread group is divided into multiple thread subgroups, executing a segment of the shader program for each of the multiple thread subgroups, the segment of the shader program completing execution for one thread subgroup before execution for a subsequent thread subgroup begins.

[0094] Aspect 2 is the method described in aspect 1, wherein a thread group is a thread wave, and multiple thread subgroups are multiple thread subwaves.

[0095] Aspect 3 is the method described in either aspect 1 or 2, wherein the thread group is at least one of the pixel group, vertex group, or work item group.

[0096] Aspect 4 is the method described in any one of aspects 1 to 3, wherein the pixel group is a texture pixel group or a texels group.

[0097] Aspect 5 is the method described in any one of aspects 1 to 4, further comprising: inserting a loop marker for each of the multiple thread subgroups based on the segmentation of the shader program.

[0098] Aspect 6 is the method described in any of aspects 1 to 5, wherein the loop marker defines the range of segments of the shader procedure.

[0099] Aspect 7 is the method described in any one of aspects 1 to 6, wherein the scope includes the beginning of a segment of a shader procedure and the end of a segment of a shader procedure.

[0100] Aspect 8 is the method described in any of aspects 1 to 7, wherein the cycle mark is associated with an initiation mechanism or a hardware initiation mechanism.

[0101] Aspect 9 is the method described in any one of aspects 1 to 8, further comprising: determining whether consecutive instructions in the instruction set for the thread group are associated with the same surface.

[0102] Aspect 10 is the method described in any one of aspects 1 to 9, wherein the instruction set is a texture instruction and the same surface is a textured surface.

[0103] Aspect 11 is the method described in any one of aspects 1 to 10, wherein the instruction set corresponds to the downsampling instruction.

[0104] Aspect 12 is the method described in any of Aspects 1 to 11, wherein the memory footprint of the shader program segments for each of the multiple thread subgroups is associated with the size of the cache.

[0105] Aspect 13 is the method described in any of aspects 1 to 12, wherein the memory usage of all segments of the shader program for the thread group exceeds the size of the cache.

[0106] Aspect 14 is the method of any one of aspects 1 to 13, further comprising: storing in a cache the memory footprint of a segment of the shader program for each of the multiple thread subgroups.

[0107] Aspect 15 is the method described in any of aspects 1 to 14, wherein the cache is a texture cache or a level 1 (L1) texture cache.

[0108] Aspect 16 is the method described in any of aspects 1 to 15, wherein the determination of whether to divide the thread group into multiple thread subgroups is performed by the compiler.

[0109] Aspect 17 is the method described in any of aspects 1 to 16, wherein the segmentation of the shader program for each of the multiple thread subgroups is executed by a graphics shader in a graphics processing unit (GPU).

[0110] Aspect 18 is an apparatus for graphics processing, including at least one processor coupled to memory and configured to implement the method as described in any one of aspects 1 to 17.

[0111] Aspect 19 is an apparatus for graphics processing, including units for implementing the method as described in any one of aspects 1 to 17.

[0112] Aspect 20 is a computer-readable medium storing computer-executable code that, when executed by at least one processor, causes at least one processor to implement the method as described in any one of aspects 1 to 17.

Claims

1. A method for image processing, comprising: Determine whether to divide the thread group into multiple thread subgroups, where each thread in the thread group is associated with a shader program; Based on the determination that the thread group is divided into the plurality of thread subgroups, the thread group is divided into the plurality of thread subgroups; Based on the segmentation of the shader program, a loop marker is inserted for each of the plurality of thread subgroups, wherein the loop marker is a texture loop marker associated with a texture instruction, wherein the texture loop marker is inserted based on the fact that consecutive texture instructions for the thread group are associated with the same texture surface, and wherein the texture loop marker indicates the length of the intra-wave loop for accessing the same surface; and Based on dividing the thread group into the plurality of thread subgroups, the shader program is executed for each of the plurality of thread subgroups, and the shader program segment completes the execution of a thread subgroup before starting the execution for the subsequent thread subgroup.

2. The method according to claim 1, wherein, The thread group is a thread wave, and the multiple thread subgroups are multiple thread subwaves.

3. The method according to claim 1, wherein, The thread group is at least one of a pixel group, a vertex group, or a work item group.

4. The method according to claim 3, wherein, The pixel group is a texture pixel group.

5. The method according to claim 1, wherein, The loop marker defines the range of the segment in the shader program.

6. The method according to claim 5, wherein, The range includes the beginning of the segment of the shader program and the end of the segment of the shader program.

7. The method according to claim 1, wherein, The cycle marker is associated with the initiation mechanism.

8. The method of claim 1, further comprising: Determine whether consecutive instructions in the instruction set for the thread group are associated with the same textured surface.

9. The method according to claim 8, wherein, The instruction set is the texture instruction.

10. The method according to claim 8, wherein, The instruction set corresponds to downsampling instructions.

11. The method according to claim 1, wherein, The memory footprint of the shader program segment for each of the plurality of thread subgroups is associated with the cache size.

12. The method according to claim 11, wherein, The memory usage for all segments of the shader program for the thread group exceeds the size of the cache.

13. The method of claim 11, further comprising: The cache stores the memory usage of the segments of the shader program for each of the plurality of thread subgroups.

14. The method according to claim 11, wherein, The cache is a texture cache.

15. The method according to claim 1, wherein, The determination of whether to divide the thread group into the multiple thread subgroups is performed by the compiler.

16. The method according to claim 1, wherein, The segment of the shader program for each of the plurality of thread subgroups is executed by a graphics shader in a graphics processing unit (GPU).

17. An apparatus for graphics processing, comprising: Memory; as well as At least one processor, coupled to the memory, is configured to: Determine whether to divide the thread group into multiple thread subgroups, where each thread in the thread group is associated with a shader program; Based on the determination that the thread group is divided into the plurality of thread subgroups, the thread group is divided into the plurality of thread subgroups; Based on the segmentation of the shader program, a loop marker is inserted for each of the plurality of thread subgroups, wherein the loop marker is a texture loop marker associated with a texture instruction, wherein the at least one processor is configured to insert the texture loop marker based on the fact that consecutive texture instructions for the thread group are associated with the same texture surface, wherein the texture loop marker indicates the length of the intra-wave loop for accessing the same surface; and Based on dividing the thread group into the plurality of thread subgroups, the shader program is executed for each of the plurality of thread subgroups, and the shader program segment completes the execution of a thread subgroup before starting the execution for the subsequent thread subgroup.

18. The apparatus according to claim 17, wherein, The thread group is a thread wave, and the multiple thread subgroups are multiple thread subwaves.

19. The apparatus according to claim 17, wherein, The thread group is at least one of a pixel group, a vertex group, or a work item group.

20. The apparatus according to claim 19, wherein, The pixel group is a texture pixel group.

21. The apparatus according to claim 17, wherein, The loop marker defines the range of the segment in the shader program.

22. The apparatus according to claim 21, wherein, The range includes the beginning of the segment of the shader program and the end of the segment of the shader program.

23. The apparatus according to claim 17, wherein, The cycle marker is associated with the initiation mechanism.

24. The apparatus according to claim 17, wherein, The at least one processor is further configured to: Determine whether consecutive instructions in the instruction set for the thread group are associated with the same textured surface.

25. The apparatus according to claim 24, wherein, The instruction set is the texture instruction.

26. The apparatus according to claim 24, wherein, The instruction set corresponds to downsampling instructions.

27. The apparatus according to claim 17, wherein, The memory footprint of the shader program segment for each of the plurality of thread subgroups is associated with the cache size.

28. The apparatus according to claim 27, wherein, The memory usage for all segments of the shader program for the thread group exceeds the size of the cache.

29. The apparatus according to claim 27, wherein, The at least one processor is further configured to: The cache stores the memory usage of the segments of the shader program for each of the plurality of thread subgroups.

30. The apparatus according to claim 27, wherein, The cache is a texture cache.

31. The apparatus according to claim 17, wherein, The determination of whether to divide the thread group into the multiple thread subgroups is configured to be performed by the compiler.

32. The apparatus according to claim 17, wherein, The at least one processor is configured to execute the segments of the shader program for each of the plurality of thread subgroups using a graphics shader in a graphics processing unit (GPU).

33. An apparatus for graphics processing, comprising: A unit for determining whether to divide a thread group into multiple thread subgroups, each thread in the thread group being associated with a shader program; A unit for dividing the thread group into the plurality of thread subgroups based on determining that the thread group is divided into the plurality of thread subgroups; A unit for inserting a loop marker for each of the plurality of thread subgroups based on segmentation of the shader program, wherein the loop marker is a texture loop marker associated with a texture instruction, wherein the texture loop marker is inserted based on consecutive texture instructions for the thread group being associated with the same texture surface, and wherein the texture loop marker indicates the length of the intra-wave loop for accessing the same surface; and A unit for executing a segment of the shader program for each of the plurality of thread subgroups based on dividing the thread group into the plurality of thread subgroups, wherein the segment of the shader program completes execution for a thread subgroup before execution for a subsequent thread subgroup begins.

34. The apparatus of claim 33, further comprising: Units for implementing the method according to any one of claims 2 to 16.

35. A non-transitory computer-readable medium storing computer-executable code for graphics processing, said code, when executed by a processor, causing the processor to: Determine whether to divide the thread group into multiple thread subgroups, where each thread in the thread group is associated with a shader program; Based on the determination that the thread group is divided into the plurality of thread subgroups, the thread group is divided into the plurality of thread subgroups; Based on the segmentation of the shader program, a loop marker is inserted for each of the plurality of thread subgroups, wherein the loop marker is a texture loop marker associated with a texture instruction, wherein the texture loop marker is inserted based on the fact that consecutive texture instructions for the thread group are associated with the same texture surface, and wherein the texture loop marker indicates the length of the intra-wave loop for accessing the same surface; and Based on dividing the thread group into the plurality of thread subgroups, the shader program is executed for each of the plurality of thread subgroups, and the shader program segment completes the execution of a thread subgroup before starting the execution for the subsequent thread subgroup.

36. The non-transitory computer-readable medium according to claim 35, wherein, When executed by the processor, the code causes the processor to implement the method according to any one of claims 2 to 16.

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