Display panel and display device

Abstract

A display panel and a display device. The display panel comprises: a substrate substrate, a driving circuit layer and a light-emitting structure layer arranged on the substrate substrate; the driving circuit layer comprises a plurality of circuit units, and the light-emitting structure layer comprises a plurality of light-emitting devices; at least one circuit unit comprises a plurality of initial signal lines and a pixel driving circuit; the pixel driving circuit comprises a plurality of transistors, and the plurality of transistors comprise at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor; the plurality of initial signal lines each comprise a sub-signal line (31, 61) along a first direction (X), and at least one of the plurality of initial signal lines comprises a sub-signal line (73, 74) extending along a second direction (Y); the first direction (X) and the second direction (Y) intersect; and the sub-signal line (31, 61) extending along the first direction (X) of the initial signal line and the sub-signal line (73, 74) extending along the second direction (Y) are electrically connected.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display panel and display device. Background Technology

[0002] Active matrix organic light-emitting diode (AMOLED) display panels are becoming increasingly widely used. AMOLED pixels are organic light-emitting diodes (OLEDs). AMOLEDs emit light by driving thin-film transistors to generate a driving current in a saturated state, which then drives the light-emitting devices to emit light. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a display panel and display device.

[0004] In a first aspect, embodiments of this disclosure provide a display panel, comprising: a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the driving circuit layer on a side opposite to the substrate; the driving circuit layer includes a plurality of circuit units, and the light-emitting structure layer includes a plurality of light-emitting devices; at least one circuit unit includes a plurality of initial signal lines and a pixel driving circuit; the pixel driving circuit includes a plurality of transistors, and the plurality of transistors includes at least one oxide thin-film transistor and at least one low-temperature polycrystalline silicon thin-film transistor;

[0005] Each of the plurality of initial signal lines includes a sub-signal line along a first direction, and at least one of the plurality of initial signal lines includes a sub-signal line extending along a second direction; the first direction and the second direction intersect; the sub-signal line extending in the first direction and the sub-signal line extending in the second direction of the initial signal line are electrically connected.

[0006] The driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged sequentially along the direction away from the substrate.

[0007] The first semiconductor layer includes the active layer of the low-temperature polycrystalline silicon thin-film transistor;

[0008] The first conductive layer includes the gate of the low-temperature polycrystalline silicon thin-film transistor;

[0009] The second conductive layer includes a first gate of the oxide thin-film transistor and at least one sub-signal line extending along the first direction;

[0010] The second semiconductor layer includes the active layer of the oxide thin-film transistor;

[0011] The third conductive layer includes the second gate of the oxide thin-film transistor;

[0012] The fourth conductive layer includes at least one sub-signal line extending along the first direction;

[0013] The fifth conductive layer includes sub-signal lines extending along the second direction.

[0014] The plurality of initial signal lines include a first initial signal line and a second initial signal line;

[0015] At least one sub-signal line extending along the first direction in the second conductive layer includes a first sub-signal line of the first initial signal line;

[0016] At least one sub-signal line extending along the first direction in the fourth conductive layer includes a third sub-signal line of the second initial signal line.

[0017] The sub-signal lines extending along the second direction in the fifth conductive layer include the third sub-signal line of the first initial signal line and / or the fourth sub-signal line of the second initial signal line.

[0018] Wherein, when the first initial signal line includes the first sub-signal line and the second sub-signal line; the fourth conductive layer further includes a plurality of first connection electrodes; the first sub-signal line is electrically connected to the first region of the active layer of the first transistor in the pixel driving circuit through a via; the first region of the active layer of the first transistor is electrically connected to the first connection electrode through a via; the first connection electrode is electrically connected to the second sub-signal line through a via;

[0019] When the second initial signal line includes the third sub-signal line and the fourth sub-signal line, the third sub-signal line is electrically connected to the fourth sub-signal line through a via.

[0020] The driving circuit layer includes multiple cell rows and multiple cell columns. The cell row includes multiple circuit cells arranged side by side along the first direction; the cell column includes multiple circuit cells arranged side by side along the second direction.

[0021] When the first initial signal line includes the first sub-signal line and the second sub-signal line, in at least one of the unit columns, the second sub-signal lines in adjacent circuit units are interconnected.

[0022] When the second initial signal line includes a third sub-signal line and the fourth sub-signal line, in at least one of the unit columns, the fourth sub-signal lines in adjacent circuit units are interconnected.

[0023] The plurality of light-emitting devices include a red light-emitting device, a first green light-emitting device, a second green light-emitting device, and a blue light-emitting device; the plurality of circuit units include a first circuit unit electrically connected to the red light-emitting device, a second circuit unit electrically connected to the blue light-emitting device, a third circuit unit electrically connected to the first green light-emitting device, and a fourth circuit unit electrically connected to the second green light-emitting device; the plurality of unit columns include a first unit column and a second unit column, the first unit column including the first circuit unit and the second circuit unit alternately arranged along the second direction, and the second unit column including the third circuit unit and the fourth circuit unit alternately arranged along the second direction;

[0024] When the first initial signal line includes the first sub-signal line and the second sub-signal line, at least a portion of the second sub-signal line is disposed in the second cell column;

[0025] When the second initial signal line includes a third sub-signal line and the fourth sub-signal line, at least a portion of the fourth sub-signal line is disposed in the second unit column.

[0026] The fifth conductive layer further includes multiple first power lines; in the same unit column, the first power lines in adjacent circuit units are interconnected.

[0027] The second sub-signal line and the fourth sub-signal line are located between the first power lines in the two cell columns to which they are connected.

[0028] The driving circuit layer includes multiple unit structures arranged side by side along the first direction; each unit structure includes two adjacent unit columns.

[0029] The first power line in the circuit unit includes a first segment and a second segment that extend along a second direction and are electrically connected to each other; in the unit column, the first segment of the first power line of one of the adjacent circuit units is electrically connected to the second segment of the other; in the unit structure, the spacing between adjacent second segments in the first direction is smaller than the spacing between adjacent first segments.

[0030] The fourth conductive layer further includes a plurality of second connecting electrodes; in the unit structure, the second connecting electrodes electrically connect the second line segments arranged adjacent to each other in the first direction through vias.

[0031] The fifth conductive layer further includes multiple data lines; in the unit column, adjacent data lines are interconnected.

[0032] The first power line includes a first side and a second side disposed opposite to each other along a first direction; the data line in the first unit column is located on the first side of the first power line, and the data line in the second unit column is located on the second side of the first power line.

[0033] The circuit unit further includes a third connection electrode; the first region of the active layer of the fourth transistor is electrically connected to the third connection electrode through a via; the third connection electrode is electrically connected to the data line through a via.

[0034] The fourth conductive layer further includes a plurality of fourth connection electrodes; the fourth connection electrodes are electrically connected to the gate of the third transistor in the pixel driving circuit through vias; the second region of the active layer of the first transistor in the pixel driving circuit and the first region of the second transistor are electrically connected to the fourth connection electrodes through vias.

[0035] The fourth conductive layer further includes a plurality of fifth connection electrodes; the fifth connection electrodes are electrically connected to the second region of the active layer of the third transistor in the pixel driving circuit through vias, and the second region of the active layer of the second transistor in the pixel driving circuit is electrically connected to the fifth connection electrodes through vias.

[0036] The fourth conductive layer further includes a plurality of sixth connecting electrodes and a plurality of seventh connecting electrodes; the sixth connecting electrodes are electrically connected to the second region of the active layer of the sixth transistor through vias; the sixth connecting electrodes are electrically connected to the seventh connecting electrodes through vias; and the anode of the light-emitting device is electrically connected to the seventh connecting electrodes through vias.

[0037] The display panel further includes a shielding electrode layer located on the side of the first semiconductor layer near the substrate; the shielding electrode layer includes a plurality of shielding electrodes; the orthographic projection of the shielding electrodes on the substrate covers the orthographic projection of the active layer of the third transistor of the pixel driving circuit on the substrate.

[0038] The shielding electrodes arranged side by side along the first direction are electrically connected; the shielding electrodes arranged side by side along the second direction are electrically connected.

[0039] The shielding electrode layer is electrically connected to the first power line through a via.

[0040] The first conductive layer further includes a first scan line, a light emission control line, and the first electrode of the storage capacitor in the pixel driving circuit;

[0041] The second conductive layer also includes a second electrode of a storage capacitor, a first portion of a second scan line, and a first portion of a first reset signal line;

[0042] The third conductive layer also includes a second portion of the second scan line and a second portion of the first reset signal line.

[0043] Secondly, embodiments of this disclosure also provide a display device, which includes any of the display panels described above. Attached Figure Description

[0044] Figure 1a and Figure 1b This is a schematic diagram of a planar structure of a display panel.

[0045] Figure 2 This is a schematic diagram of an exemplary pixel driving circuit.

[0046] Figure 3 This is a layout of the display panel according to an embodiment of the present disclosure.

[0047] Figure 4 This is a schematic diagram showing the distribution of the display panel according to an embodiment of the present disclosure.

[0048] Figure 5 This is a layout of the first semiconductor layer of the display panel according to an embodiment of the present disclosure.

[0049] Figure 6 This is a layout of the first conductive layer of the display panel according to an embodiment of the present disclosure.

[0050] Figure 7 This is a layout of the second conductive layer of the display panel according to an embodiment of the present disclosure.

[0051] Figure 8 This is a layout of the second semiconductor layer of the display panel according to an embodiment of the present disclosure.

[0052] Figure 9 This is a layout of the third conductive layer of the display panel according to an embodiment of the present disclosure.

[0053] Figure 10 This is a layout of the display panel after the second conductive layer, the second semiconductor layer, and the third conductive layer are stacked, according to an embodiment of this disclosure.

[0054] Figure 11 This is a layout of the fourth conductive layer of the display panel according to an embodiment of the present disclosure.

[0055] Figure 12 This is a layout of the fifth conductive layer of the display panel according to an embodiment of the present disclosure.

[0056] Figure 13This is a layout of the display panel after the fourth and fifth conductive layers are superimposed, according to an embodiment of this disclosure.

[0057] Figure 14 This is a layout of the shielding electrode layer of the display panel according to an embodiment of the present disclosure.

[0058] Figure 15 This is another layout of the fifth conductive layer of the display panel according to an embodiment of the present disclosure.

[0059] Figure 16 This is a layout of the sixth conductive layer of the display panel according to an embodiment of the present disclosure. Detailed Implementation

[0060] To enable those skilled in the art to better understand the technical solutions of the embodiments of this invention, the embodiments of this invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0061] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0062] Figure 1a and Figure 1bThis is a schematic diagram of a planar structure of a display panel. In an exemplary embodiment, the display panel may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and two third sub-pixels P3 and a fourth sub-pixel P4 emitting a third color light. Each of the four sub-pixels may include a circuit unit and a light-emitting device. The circuit unit may include a scan signal line, a data signal line, a light-emitting signal line, and a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the data signal line, and the light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting device in each sub-pixel is connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0063] In some examples, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light. In exemplary embodiments, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. In one exemplary embodiment, the four sub-pixels can be arranged in a square to form a GGRB pixel arrangement, such as... Figure 1a As shown. In another exemplary embodiment, the four sub-pixels can be arranged in a diamond shape to form an RGBG pixel arrangement, such as... Figure 1b As shown. In other exemplary embodiments, the four sub-pixels can be arranged in a horizontal or vertical arrangement. In an exemplary embodiment, a pixel unit may include three sub-pixels, which can be arranged in a horizontal, vertical, or triangular arrangement, etc., and this disclosure does not limit the specific arrangement.

[0064] In an exemplary embodiment, multiple sub-pixels arranged sequentially in the horizontal direction are called pixel rows, and multiple sub-pixels arranged sequentially in the vertical direction are called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array arranged in an array. Figure 2 This is a schematic diagram of an exemplary pixel driving circuit; such as Figure 2As shown, the pixel driving circuit may include: a first reset sub-circuit 2, a threshold compensation sub-circuit 8, a driving sub-circuit 1, a data writing sub-circuit 7, a first light emission control sub-circuit 501, a second light emission control sub-circuit 502, a second reset sub-circuit 4, and a storage sub-circuit 6. The first reset sub-circuit 2 is connected to the control terminal of the driving sub-circuit 1 and is configured to reset the control terminal of the driving sub-circuit 1 under the control of a first reset signal. The threshold compensation sub-circuit 8 is electrically connected to the control terminal and the second terminal of the driving sub-circuit 1, and is configured to perform threshold compensation on the driving sub-circuit 1. The data writing sub-circuit 7 is electrically connected to the first terminal of the driving sub-circuit 1 and is configured to write data signals into the storage sub-circuit under the control of a scan signal. The storage sub-circuit 6 is electrically connected to the control terminal and the first power supply terminal VDD of the driving sub-circuit 1, and is configured to store data signals. The first light-emitting control sub-circuit 501 is connected to the first power supply terminal VDD and the first terminal of the driving sub-circuit 1, and is configured to enable or disable the connection between the driving sub-circuit 1 and the first power supply terminal VDD. The second light-emitting control sub-circuit 502 is electrically connected to the second terminal of the driving sub-circuit 1 and the first electrode of the light-emitting device OLED, and is configured to enable or disable the connection between the driving sub-circuit 1 and the light-emitting device OLED. The second reset sub-circuit 4 is electrically connected to the first electrode of the light-emitting device OLED, and is configured to reset the control terminal of the driving sub-circuit 1 and the first electrode of the light-emitting device OLED under the control of the second reset control signal.

[0065] Continue to refer to Figure 2 The first reset sub-circuit includes a first transistor T1, the threshold compensation sub-circuit 8 includes a second transistor T2, the driving sub-circuit 1 includes a third transistor T3, the control terminal of the driving sub-circuit 1 includes the control electrode of the third transistor T3, the first terminal of the driving sub-circuit 1 includes the first electrode of the third transistor T3, and the second terminal of the driving sub-circuit 1 includes the second electrode of the third transistor T3. The data writing sub-circuit 7 includes a fourth transistor T4, the storage sub-circuit 6 includes a storage capacitor Cst, the first light-emitting control sub-circuit 501 includes a fifth transistor T5, the second light-emitting control sub-circuit 502 includes a sixth transistor T6, and the second reset sub-circuit 4 includes a seventh transistor T7.

[0066] It should be noted that, based on their characteristics, transistors can be divided into N-type transistors and P-type transistors. For clarity, Figure 2 The pixel driving circuit in the example is illustrated by using N-type transistors (e.g., oxide thin film transistors) for the first and second transistors, and P-type transistors (e.g., low-temperature polycrystalline silicon thin film transistors) for the third, fourth, fifth, sixth, and seventh transistors.

[0067] Furthermore, the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. Each transistor includes a first electrode, a second electrode, and a control electrode; wherein the control electrode serves as the gate of the transistor, one of the first electrode and the second electrode serves as the source of the transistor, and the other serves as the drain of the transistor; and the source and drain of the transistor can be symmetrical in structure, so their physical structures can be indistinguishable. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate which serves as the control electrode, the first electrode is directly described as the source and the second electrode as the drain. Therefore, in the embodiments of this disclosure, the source and drain of all or some of the transistors can be interchanged as needed.

[0068] Continue to refer to Figure 2 The drain of the fourth transistor T4 is electrically connected to the source of the third transistor T3. The source of the fourth transistor T4 is configured to be electrically connected to the data line Data to receive a data signal. The gate of the fourth transistor T4 is configured to be electrically connected to the first scan signal line G1 to receive a scan signal. The second plate of the storage capacitor C is electrically connected to the first power supply terminal VDD, and the first plate of the storage capacitor C is electrically connected to the gate of the third transistor T3. The source of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the drain of the second transistor T2 is electrically connected to the drain of the third transistor T3. The gate of the second transistor T2 is configured to be electrically connected to the second scan signal line G2 to receive a compensation control signal. The source of the first transistor T1 is configured to be electrically connected to the first initial signal line Vinit1 to receive a first reset signal. The drain of the first transistor T1 is electrically connected to the gate of the third transistor T3, and the gate of the first transistor T1 is configured to be electrically connected to the first reset signal terminal Re1. The system receives a first reset control signal; the drain of the seventh transistor T7 is configured to be electrically connected to the first initial signal line Vinit1 to receive the first reset signal, the source of the seventh transistor T7 is electrically connected to the first electrode of the light-emitting device OLED, and the gate of the seventh transistor T7 is configured to be electrically connected to the second reset signal terminal Re2 to receive the second reset control signal; the source of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, the drain of the fifth transistor T5 is electrically connected to the source of the third transistor T3, and the gate of the fifth transistor T5 is configured to be electrically connected to the first enable signal terminal EM1 to receive the first light emission control signal; the source of the sixth transistor T6 is electrically connected to the drain of the third transistor T3, the drain of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device OLED, and the gate of the sixth transistor T6 is configured to be electrically connected to the second enable signal terminal EM2 to receive the second light emission control signal; the second electrode of the light-emitting device OLED is electrically connected to the second power supply terminal VSS.

[0069] For example, one of the first power line VDD and the second power line VSS is a high-voltage power line, and the other is a low-voltage power line. For example, as... Figure 2 As shown, the first power line VDD is a voltage source that outputs a constant first voltage, which is a positive voltage; while the second power line VSS can be a voltage source that outputs a constant second voltage, which is a negative voltage, and so on. For example, in some examples, the second power line VSS can be grounded.

[0070] Continue to refer to Figure 2 The first and second light-emitting control signals can be the same. That is, the gates of the fifth transistor T5 and the sixth transistor T6 can be electrically connected to the same signal line, such as the first enable signal terminal EM1, to receive the same signal (e.g., the first light-emitting control signal). In this case, the display panel can omit the second enable signal terminal EM2, reducing the number of ports. Alternatively, the gates of the fifth transistor T5 and the sixth transistor T6 can be electrically connected to different signal terminals. That is, the gate of the fifth transistor T5 is electrically connected to the first enable signal terminal EM1, and the gate of the sixth transistor T6 is electrically connected to the second enable signal terminal EM2, while the signals transmitted by the first enable signal terminal EM1 and the second enable signal terminal EM2 are the same.

[0071] It should be noted that when the fifth transistor T5 and the sixth transistor T6 are transistors of different types, for example, the fifth transistor T5 is a P-type transistor and the sixth transistor T6 is an N-type transistor, the first light-emitting control signal and the second light-emitting control signal may also be different. The embodiments of this disclosure do not impose this limitation. In this disclosure, the example is taken where the gates of both the fifth transistor T5 and the sixth transistor T6 are connected to the enable signal terminal EM.

[0072] Continue to refer to Figure 2 Since the first and seventh transistors have opposite switching characteristics, their gates are electrically connected to different reset signal lines. In some examples, to reduce wiring, the reset signal line connected to the gate of the first transistor in this row can be multiplexed with the reset signal line connected to the gate of the seventh transistor in the previous row.

[0073] For example, the source of the first transistor T1 and the drain of the seventh transistor T7 are respectively connected to the first initial signal line Vinit1 and the second initial signal line Vinit2. The first initial signal line Vinit1 and the second initial signal line Vinit2 can be DC reference voltage terminals to output a constant DC reference voltage. The first initial signal line Vinit1 and the second initial signal line Vinit2 can be the same; for example, the source of the first transistor T1 and the drain of the seventh transistor T7 can be connected to the same initial signal line. The first initial signal line Vinit1 and the second initial signal line Vinit2 can be high-voltage terminals or low-voltage terminals, as long as they can provide a first reset signal and a first reset signal to reset the gate of the third transistor T3 and the first terminal of the light-emitting element. This disclosure does not impose any limitations on this. For example, the source of the first transistor T1 and the drain of the seventh transistor T7 can both be connected to the reset power supply signal line Vinit.

[0074] in addition, Figure 2 The first reset sub-circuit 2, threshold compensation sub-circuit 8, driving sub-circuit 1, data writing sub-circuit 7, first light emission control sub-circuit 501, second light emission control sub-circuit 502, second reset sub-circuit 4, and storage sub-circuit 6 in the pixel circuit shown are only illustrative. The specific structure of the sub-circuits such as the first reset sub-circuit 2, threshold compensation sub-circuit 8, driving sub-circuit 1, data writing sub-circuit 7, first light emission control sub-circuit 501, second light emission control sub-circuit 502, second reset sub-circuit 4, and storage sub-circuit 6 can be set according to actual application requirements, and the embodiments disclosed herein do not impose specific limitations on this.

[0075] It should be noted that, in the embodiments of this disclosure, the pixel circuit of the sub-pixel can be, in addition to being, Figure 2 In addition to the 7T1C (i.e., seven transistors and one capacitor) structure shown, there may be circuit structures that include other numbers of transistors and capacitors, such as 7T12C, 6T1C, 6T12C or 9T12C structures. This disclosure does not limit the specific implementation of these structures.

[0076] In the embodiments of the invention, the light-emitting device OLED can be an organic light-emitting diode (OLED). Of course, the light-emitting device OLED can also be a miniature inorganic light-emitting diode, and further, it can be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED). One of the first and second electrodes of the light-emitting device OLED is the anode, and the other is the cathode; in this embodiment of the invention, the first electrode of the light-emitting device OLED is the anode, and the second electrode is the cathode, as an example.

[0077] Firstly, such as Figure 3-16 As shown, this disclosure provides a display panel including a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the side of the driving circuit layer facing away from the substrate. The driving circuit layer includes pixel driving circuits and multiple initial signal lines. The light-emitting structure layer includes multiple light-emitting devices, and each pixel driving circuit can be electrically connected to another pixel driving circuit. The pixel driving circuit in this disclosure embodiment can employ... Figure 2The pixel driving circuit shown in the diagram uses N-type transistors for both the first and second transistors, and both are oxide thin-film transistors. The third, fourth, fifth, sixth, and seventh transistors are all P-type transistors, and all are low-temperature polycrystalline silicon thin-film transistors. Specifically, in at least one circuit unit in this embodiment, multiple initial signal lines include sub-signal lines extending along a first direction X, with at least one including a sub-signal line extending along a second direction Y. The initial signal lines include sub-signal lines in both directions, and these two sub-signal lines are electrically connected. To clarify the structure of the display panel in this embodiment, taking a display substrate including the aforementioned two initial signal lines as an example, one is a first initial signal line, and the other is a second initial signal line. For example, at least one of the first and second initial signal lines in at least one circuit unit includes a sub-signal line extending along the first direction X and a sub-signal line extending along the second direction Y, with the first direction X and the second direction Y intersecting. For example, the first initial signal line includes a first sub-signal line 31 extending along a first direction X and a second sub-signal line 73 extending along a second direction Y, and the first sub-signal line 31 and the second sub-signal line 73 are electrically connected and intersected; and / or, the second initial signal line includes a third sub-signal line 61 extending along a first direction X and a fourth sub-signal line 74 extending along a second direction Y, and the third sub-signal line 61 and the fourth sub-signal line 74 are electrically connected and intersected. In the following description, the example of the first initial signal line including a first sub-signal line 31 and a second sub-signal line 73 extending along a first direction X, and the second initial signal line including a third sub-signal line 61 and a fourth sub-signal line 74 extending along a first direction X, will be used.

[0078] In some examples, multiple circuit units on the driving circuit layer are arranged side-by-side along a first direction X to form multiple unit rows 10, and the multiple unit rows 10 are arranged side-by-side along a second direction Y; multiple circuit units on the driving circuit layer are arranged side-by-side along the second direction Y to form multiple unit columns 20, and the multiple unit columns 20 are arranged side-by-side along the first direction X. Each unit row 10 may contain a first sub-signal line 31 of a first initial signal line and a third sub-signal line 61 of a second initial signal line. In at least one unit column 20, the second sub-signal lines 73 of the first initial signal lines in adjacent circuit units are interconnected, and the fourth sub-signal lines 74 of the second initial signal lines are interconnected. The second sub-signal lines 73 are arranged in spaced-out unit columns 20, and similarly, the fourth sub-signal lines 74 are also arranged in spaced-out unit columns 20. That is, there is at least one unit column 20 between two adjacent second sub-signal lines 73 arranged in the first direction X, and similarly, there is at least one unit column 20 between two adjacent fourth sub-signal lines 74 arranged in the first direction X.

[0079] In some examples, such as Figure 4 As shown, the multiple sub-pixels in the display panel may include a red sub-pixel R emitting red light, a blue sub-pixel B emitting blue light, a first green sub-pixel G1 emitting green light, and a second green sub-pixel G2 emitting green light. The red sub-pixel R may include a red light-emitting device emitting red light and a first circuit unit Q1 connected to the red light-emitting device. The blue sub-pixel B may include a blue light-emitting device emitting blue light and a second circuit unit Q2 connected to the blue light-emitting device. The first green sub-pixel G1 may include a first green light-emitting device emitting green light and a third circuit unit Q3 connected to the first green light-emitting device. The second green sub-pixel G2 may include a second green light-emitting device emitting green light and a fourth circuit unit Q4 connected to the second green light-emitting device. The first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 constitute a circuit unit group. At least four circuit units in at least one circuit unit group may be arranged in a square manner, that is, the four circuit units are arranged in two unit rows 10 and two unit columns 20. In this disclosure, a sub-pixel refers to a region divided according to a light-emitting device, and a circuit unit refers to a region divided according to a pixel driving circuit. In exemplary embodiments, the positions of sub-pixels and circuit units may correspond, or the positions of sub-pixels and circuit units may not correspond.

[0080] In some examples, the multiple unit columns 20 may include a first unit column and a second unit column. The first unit column refers to a column formed by multiple first circuit units Q1 and second circuit units Q2, and the second unit column refers to a column formed by multiple third circuit units Q3 and fourth circuit units Q4. The first circuit units Q1 and second circuit units Q2 in the first unit column are alternately arranged along the second direction Y, and the third circuit units Q3 and fourth circuit units Q4 in the second unit column are alternately arranged along the second direction Y.

[0081] In one example, the second sub-signal of the first initial signal line and the fourth sub-signal line 74 of the second initial signal line can be set in the first unit column. For example, if the Nth unit column 20 and the N+2th unit column 20 are the first unit columns, and the N+1th unit column 20 and the N+3th unit column 20 are the second unit columns, then the second initial signal line can be set in the Nth unit column 20, the N+2th unit column 20, the N+4th unit column 20, ..., and the second initial signal line repeats every other second unit column.

[0082] In another example, the second sub-signal of the first initial signal line and the fourth sub-signal line 74 of the second initial signal line can be set in the second unit column. For example, if the Nth unit column 20 and the N+2th unit column 20 are the first unit columns, and the N+1th unit column 20 and the N+3th unit column 20 are the second unit columns, then the second initial signal line can be set in the N+1th unit column 20, the N+3th unit column 20, the N+5th unit column 20, ..., and the second initial signal line repeats every other first unit column.

[0083] In yet another example, the second sub-signal of the first initial signal line and the fourth sub-signal line 74 of the second initial signal line may be provided in the first unit column and the second unit column.

[0084] In some examples, the Nth and N+2th unit columns 20 can be first unit columns, and the N+1th and N+3th unit columns 20 can be second unit columns. In the Nth unit column 20, the circuit units in the Mth row are first circuit units, and the circuit units in the M+1th row are second circuit units; therefore, the first and second circuit units in the Nth unit column 20 are alternately arranged along the second direction Y. In the N+2th unit column 20, the circuit units in the Mth row are second circuit units, and the circuit units in the M+1th row are first circuit units; therefore, the second and first circuit units in the N+2th unit column 20 are alternately arranged along the second direction Y.

[0085] In some examples, since both the circuit unit in row M, column N and the circuit unit in row M+1, column N+2 are first circuit units, the first sub-signal line 31 of the first initial signal line in the circuit unit in row M, column N can have the same shape as the first sub-signal line 31 of the first initial signal line in the circuit unit in row M+1, column N+2. Similarly, the fourth sub-signal line 74 of the second initial signal line in the circuit unit in row M, column N can have the same shape as the fourth sub-signal line 74 of the second initial signal line in the circuit unit in row M+1, column N+2. Since both the circuit unit in row M+1, column N and the circuit unit in row M+2 are second circuit units, the shape of the second initial signal line in the circuit unit in row M+1, column N can have the same shape as the first sub-signal line 31 of the first initial signal line in the circuit unit in row M, column N+2. Furthermore, the shape of the second initial signal line in the circuit unit in row M+1, column N can have the same shape as the fourth sub-signal line 74 of the second initial signal line in the circuit unit in row M+1, column N+2.

[0086] In some possible exemplary embodiments, the second sub-signal line 73 of the first initial signal line can be arranged in the spaced first or second unit columns, that is, between two adjacent second sub-signal lines 73 in the first direction X, there are three unit columns 20 spaced apart. For example, the second sub-signal line 73 can be arranged in the Nth unit column 20, the N+4th unit column 20, the N+8th unit column 20, ..., with the second sub-signal line 73 repeating every one first unit column and every two second unit columns. Alternatively, the second sub-signal line 73 can be arranged in the N+1th unit column 20, the N+5th unit column 20, the N+9th unit column 20, ..., with the second sub-signal line 73 repeating every two first unit columns and every one second unit column. In exemplary embodiments, there is no special requirement for the number of unit columns 20 spaced between adjacent second sub-signal lines 73, and it can be set as needed, which is not limited here. The arrangement of the fourth sub-signal line 74 of the second initial signal line is the same as that of the second sub-signal line 73 of the first initial signal line described above, and therefore will not be repeated here.

[0087] In some examples, such as Figure 12 As shown, the circuit unit of the display panel includes not only the above-described structure, but also a first power line 71 and a data line 72. The first power line 71 is configured as a signal line to receive power signals, and the data line 72 is configured as a signal line to receive data voltage signals. In at least one unit column 20, the first power lines 71 in adjacent circuit units are interconnected, and the data lines 72 are interconnected. The first power line 71 includes a first side (left side) and a second side (right side) arranged opposite each other along a first direction X. If the data line 72 in one of the adjacent unit columns 20 is located on the first side of the first power line 71, then the data line 72 in the other unit column is located on the second side of the first power line 71; or, if the data line 72 in one of the adjacent unit columns 20 is located on the second side of the first power line 71, then the data line 72 in the other unit column is located on the first side of the first power line 71. Meanwhile, in unit column 20, the second sub-signal line 73 and the fourth sub-signal line 74 of the first initial signal line are located on the same side of the first power line 71 in the first direction X, and are located on a different side of the first power line 71 in the first direction X from the data line 72. That is, in this unit column 20, the second sub-signal line 73 and the fourth sub-signal line 74 are located on the first side of the first power line 71, and the data line 72 is located on the second side of the first power line 71, or the second sub-signal line 73 and the fourth sub-signal line 74 are located on the second side of the first power line 71, and the data line 72 is located on the first side of the first power line 71.

[0088] In some examples, two data lines 72 are provided between the first power line 71 in the Nth column 20 and the first power line 71 in the N+1th column 20 (one data line 72 is in the Nth column 20 and the other is in the N+1th column 20), and a second sub-signal line 73 and a fourth sub-signal line 74 (in the N+1th column 20) are provided between the first power line 71 in the N+1th column 20 and the first power line 71 in the N+2th column 20.

[0089] In some examples, the driving circuit layer includes a plurality of cell structures 100 arranged side by side along the first direction X; each cell structure 100 includes two adjacent cell columns 20; for example, each cell structure 100 includes a first cell column and a second cell column arranged adjacently. In some examples, the first power lines 71 in the two adjacent cell columns 20 in the first direction X are mirror-symmetrical about the axis of symmetry in the second direction Y, that is, the two first power lines 71 in each cell structure 100 are mirror-symmetrical. The first power line 71 in the circuit unit includes a first segment 71-1 and a second segment 71-2 extending along the second direction Y and electrically connected to each other; in the unit column 20, the first segment 71-1 of the first power line 71 of one of the adjacent circuit units is electrically connected to the second segment 71-2 of the other; in the unit structure 100, the spacing between adjacent second segments 71-2 in the first direction X is smaller than the spacing between adjacent first segments 71-1; in each unit structure 100, adjacent second segments 71-2 in the first direction X are short-circuited, in which case each first power line 71 forms a conductive mesh-like structure, thereby reducing resistance.

[0090] Additionally, it should be noted that the first segment 71-1 and the second segment 71-2 of the first power line 71 in each circuit unit are electrically connected by a connecting segment 71-3. The angle formed by the extension direction of the connecting segment 71-3 and the second direction Y is less than 90°, for example, 30°, 45°, 60°, etc. The line widths of the first segment 71-1, the second segment 71-2, and the connecting segment 71-3 of the first power line 71 can be the same or different. In some examples, the line width of the first segment 71-1 is greater than the line widths of the second segment 71-2 and the connecting segment 71-3.

[0091] In some examples, such as Figure 5-13As shown, in a plane perpendicular to the display panel, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged sequentially in a direction away from the substrate. The first semiconductor layer includes the gates of the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor in the pixel driving circuit; the first conductive layer includes a first scan line 21, a light emission control line 23, and a first electrode 22 of the storage capacitor in the pixel driving circuit; the second conductive layer includes the first gate of the first transistor, the first gate of the second transistor, the second electrode 34 of the storage capacitor, a first portion 33 of the second scan line, a first portion 32 of the first reset signal line, and a first sub-signal line 31 in the pixel driving circuit; the second semiconductor layer includes the active layer 41 of the first transistor and the active layer 42 of the second transistor in the pixel driving circuit; the third conductive layer includes the second gate of the first transistor and the second gate of the second transistor in the pixel driving circuit, a second portion 52 of the second scan line, and a second portion 51 of the first reset signal line; the fourth conductive layer includes a third sub-signal line 61; the fifth conductive layer includes a second sub-signal line 73 of the first initial signal line and a fourth sub-signal line 74 of the second initial signal line.

[0092] In some examples, such as Figure 11 As shown, the fourth conductive layer not only includes the above structure, but may also include multiple first connection electrodes 62. The first sub-signal line 31 of the first initial signal line is electrically connected to the first region (source) of the active layer 41 of the first transistor through a via. The first region of the active layer 41 of the first transistor is electrically connected to the first connection electrode 62 through a via. The first connection electrode 62 is electrically connected to the second sub-signal line 73 through a via.

[0093] In some examples, such as Figure 12 and 13 As shown, the fifth conductive layer includes a first power line 71, and the fourth conductive layer also includes a plurality of second connection electrodes 63 in each of the unit structures 100. In the unit structure 100, a second connection electrode 63 electrically connects the second segments 71-2 of the first power lines 71 adjacent to each other in the first direction X through a via. Figure 13 As shown, the second connecting electrode 63 includes two chamfers, which is designed to reserve space for other structures. The shape of the second connecting electrode 63 can also be varied, for example, it can be a circle, a regular polygon, etc.

[0094] In some examples, such as Figure 12 and 13As shown, the fifth conductive layer also includes a data line 72, and the fourth conductive layer also includes a plurality of third connection electrodes 64; in each circuit unit, the first region (source) of the active layer 12 of the fourth transistor of the pixel driving circuit is connected to the third connection electrode 64 through a via; the third connection electrode 64 is connected to the data line 72 through a via.

[0095] In some examples, such as Figure 11 As shown, the fourth conductive layer also includes a plurality of fourth connection electrodes 65; in each circuit unit, the fourth connection electrode 65 is connected to the gate of the third transistor in the pixel driving circuit through a via; the second region (drain) of the active layer 41 of the first transistor and the first region (source) of the second transistor in the pixel driving circuit are electrically connected to the fourth connection electrode 65 through a via. For example, the extension direction of the fourth connection electrode 65 has a certain angle with the second direction Y, and it has a first end and a second end disposed opposite to each other in its extension direction. The first end of the fourth connection electrode 65 is connected to the gate of the third transistor through a via, and the second end of the fourth connection electrode 65 is connected through the second region of the active layer 41 of the first transistor and the first region of the second transistor.

[0096] In some examples, such as Figure 11 As shown, the fourth conductive layer also includes a plurality of fifth connection electrodes 66. In each circuit unit, the fifth connection electrode 66 is electrically connected to the second region (drain) of the active layer 42 of the third transistor in the pixel driving circuit through a via, and the second region (drain) of the active layer 42 of the second transistor in the pixel driving circuit is electrically connected to the fifth connection electrode 66 through a via. In some examples, such as Figure 11-13 As shown, the fourth conductive layer further includes a sixth connection electrode 67, and the fifth conductive layer further includes a seventh connection electrode 75. In each circuit unit, the sixth connection electrode 67 is electrically connected to the second region (drain) of the active layer 14 of the sixth transistor through a via; the sixth connection electrode 67 is electrically connected to the seventh connection electrode 75 through a via; the anode of the light-emitting device is electrically connected to the seventh connection electrode 75 through a via. In some examples, such as Figure 14As shown, the driving circuit layer may further include a shielding electrode layer located on the side of the first semiconductor layer near the substrate; the shielding electrode layer includes a plurality of shielding electrodes 81; the orthographic projection of the shielding electrodes 81 on the substrate covers the orthographic projection of the active layer 11 of the third transistor of the pixel driving circuit on the substrate. In some examples, the shielding electrodes 81 arranged side by side along the first direction X are electrically connected; the shielding electrodes 81 arranged side by side along the second direction Y are electrically connected. In some examples, the shielding electrode layer is electrically connected to the first power line 71 through a via. Of course, the shielding electrode layer may also be electrically connected to the second power line, or connected to the first initial signal line (or the second initial signal line), or the shielding electrode layer may be in a floating state, all of which are within the protection scope of the embodiments of this disclosure.

[0097] In some examples, the driving circuit layer may further include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer. The first insulating layer is disposed between the substrate and the shielding electrode layer; the second insulating layer is disposed between the first semiconductor layer and the first conductive layer; the third insulating layer is disposed between the first conductor layer and the second conductor layer; the fourth insulating layer is disposed between the second conductive layer and the second semiconductor layer; the fifth insulating layer is disposed between the second semiconductor layer and the third conductive layer; the sixth insulating layer is disposed between the fourth conductive layer and the third conductive layer; and the seventh insulating layer is disposed between the fourth conductive layer and the fifth conductive layer. The following description uses the fabrication process of a display panel as an example. The "patterning process" described in this disclosure, for metallic materials, inorganic materials, or transparent conductive materials, includes processes such as coating photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating organic materials, mask exposure, and development. Deposition can be performed using one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using one or more of spraying, spin coating, and inkjet printing; etching can be performed using one or more of dry etching and wet etching, and this disclosure does not limit the methods. "Thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require patterning during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires patterning during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display panel. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0098] The fabrication process of the driving circuit layer in this embodiment may include the following operations.

[0099] (1) Forming a shielding electrode layer pattern. In some examples, forming a shielding electrode layer pattern may include depositing a shielding electrode 81 material thin film on a substrate, and patterning the shielding electrode 81 material thin film using a patterning process to form a shielding electrode layer, such as... Figure 14 As shown.

[0100] In some examples, the plurality of shielding electrodes 81 of the shielding electrode layer may be in a block structure. For example, a square block, a circular block, a regular polygon block, etc. In the embodiments of the present disclosure, the shape of the shielding electrode 81 is not limited, as long as the orthographic projection of the shielding electrode 81 on the substrate can cover the orthographic projection of the active layer 11 of the third transistor in the pixel driving circuit formed subsequently on the substrate.

[0101] (2) Form a first semiconductor pattern. In some examples, forming the first semiconductor pattern may include sequentially depositing a first insulating film and a first semiconductor film on the substrate of the foregoing pattern, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a first semiconductor layer provided on the first insulating layer, as Figure 5 shown.

[0102] In some examples, the first semiconductor layer of each circuit unit may include the active layer 11 of the third transistor to the active layer 15 of the seventh transistor, and the active layer 11 of the third transistor to the active layer 15 of the seventh transistor are of an integral structure.

[0103] In some examples, the active layer 12 of the fourth transistor in the Mth row of circuit units is located on the side of the active layer 11 of the third transistor in this circuit unit away from the (M + 1)th row of circuit units, and the active layers 13, 14, and 15 of the fifth, sixth, and seventh transistors are located on the side of the active layer 11 of the third transistor in this circuit unit close to the (M + 1)th row of circuit units, and the active layer 15 of the seventh transistor is located on the side of the active layers 13 and 14 of the fifth and sixth transistors away from the active layer 11 of the third transistor.

[0104] In some examples, the active layer 11 of the third transistor is in a "ji" shape, the shapes of the active layers 12 of the fourth transistor and 13 of the fifth transistor may be in a "1" shape, the shape of the active layer 14 of the sixth transistor may be in an "L" shape, and the shape of the active layer 15 of the seventh transistor may be in a "7" shape.

[0105] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The first region of the active layer 11 of the third transistor serves as the second region of the active layer 12 of the fourth transistor and the second region of the active layer 13 of the fifth transistor at the same time, the second region of the active layer 11 of the third transistor serves as the first region of the active layer 14 of the sixth transistor at the same time, and the second region of the active layer 14 of the sixth transistor serves as the second region of the active layer 15 of the seventh transistor at the same time. In some examples, the first regions of the active layer 12 of the fourth transistor and the active layer 13 of the fifth transistor are separately provided.

[0106] (3) Forming a first conductive layer pattern. In some examples, forming a first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer. The first conductive layer pattern includes at least: a first scan line 21, a light-emitting control line 23, and a first electrode 22 of a storage capacitor, such as... Figure 6 As shown.

[0107] Combination Figure 6 As shown, the first scan line 21 and the light emission control line 23 extend along the first direction X. The first scan line 21 in the Mth row of the circuit unit is located on the side of the first electrode 22 of the storage capacitor of the current row of the circuit unit away from the M+1th row of the circuit unit, and the light emission control line 23 can be located on the side of the first electrode 22 of the current circuit unit closer to the M+1th row of the circuit unit.

[0108] In some examples, the first electrode 22 of the storage capacitor can be rectangular, with chamfered corners. The orthographic projection of the first electrode 22 onto the substrate overlaps with the orthographic projection of the active layer 11 of the third transistor onto the substrate. In an exemplary embodiment, the first electrode 22 can simultaneously serve as both an electrode of the storage capacitor and an electrode of the third transistor. The region 21-1 where the first scan line 21 overlaps with the active layer 12 of the fourth transistor serves as the gate of the fourth transistor. The region 23-1 where the light-emitting control line 23 overlaps with the active layer 13 of the fifth transistor serves as the gate of the fifth transistor, and the region where the light-emitting control line 23 overlaps with the active layer 14 of the sixth transistor serves as the gate of the sixth transistor.

[0109] (4) Forming a second conductive layer pattern. In some examples, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer. The second conductive layer pattern includes at least: a first sub-signal line 31 of a first initial signal line, a first portion 32 of a reset signal line, a first portion 33 of a second scan line, a second electrode 34 of a storage capacitor, and electrode connection lines, such as... Figure 7 As shown.

[0110] Combination Figure 7As shown, the first sub-signal line 31, the first part 32 of the reset signal line, and the first part 33 of the second scan line extend along the first direction X. In the Mth row of circuit units, the first sub-signal line 31, the first part 33 of the second scan line, and the first part 32 of the reset signal line are all located on the side of the second electrode plate 34 of the storage capacitor in this row of circuit units away from the M+1th row of circuit units. In the same row of circuit units, the first sub-signal line 31 and the first part 32 of the reset signal line are both located on the side of the first part 33 of the second scan line in this row of circuit units away from the second electrode plate 34 of the storage capacitor. The reset signal line is located on the first sub-signal line 31 and the first part 33 of the second scan line.

[0111] In some examples, the outline of the second electrode plate 34 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second electrode plate 34 on the substrate overlaps with the orthographic projection of the first electrode plate 22 on the substrate. The first electrode plate 22 and the second electrode plate 34 constitute the storage capacitor of the pixel driving circuit. An opening 34-1 is provided on the second electrode plate 34, and the opening 34-1 can be located in the middle of the second electrode plate 34. The opening can be rectangular, so that the second electrode plate 34 forms a ring structure. The opening 34-1 exposes the third insulating layer covering the first electrode plate 22, and the orthographic projection of the first electrode plate 22 on the substrate includes the orthographic projection of the opening on the substrate. In an exemplary embodiment, the opening is configured to accommodate a subsequently formed first via V1, the first via V1 being located within the opening and exposing the first electrode plate 22, so that the second electrode of the subsequently formed first transistor is connected to the first electrode plate 22.

[0112] In some examples, the electrode connection line is disposed between the second electrode plates 34 of adjacent circuit units in the first direction X or in the opposite direction of the first direction X. The first end of the electrode connection line is connected to the second electrode plate 34 of the circuit unit, and the second end of the electrode connection line extends along the first direction X or in the opposite direction of the first direction X and is connected to the second electrode plate 34 of the adjacent circuit unit. That is, the electrode connection line is configured to connect the second electrode plates 34 of adjacent circuit units in a unit row 10 to each other. In some examples, the electrode connection line can form an integrated structure in which the second electrode plates 34 of multiple circuit units in a unit row 10 are interconnected. The integrated structure of the second electrode plates 34 can be reused as power signal lines, ensuring that the multiple second electrode plates 34 in a unit row 10 have the same potential. This helps to improve the uniformity of the panel, avoid display defects, and ensure the display effect of the display panel.

[0113] In some examples, the first and second transistors in the pixel driving circuit employ a dual-gate structure. The region where the first portion 32 of the reset signal line overlaps with the active layer 41 to which the first transistor is to be formed serves as the first gate of the first transistor. For example, a gate block 32-1 protruding towards the second scan signal line is provided on the first portion 32 of the reset signal line, and this gate block 32-1 serves as the first gate of the first transistor. The region where the first portion 33 of the second scan line overlaps with the active layer 42 to which the second transistor is to be formed serves as the first gate of the second transistor. For example, multiple protruding gate blocks 33-1 are provided on the first portion 33 of the second scan line, and these gate blocks 33-1 serve as the first gate of the second transistor.

[0114] (5) Forming a second semiconductor layer pattern. In some examples, the step of forming a second semiconductor layer pattern includes: depositing a fourth insulating layer thin film and a second semiconductor thin film on a substrate on which the aforementioned pattern is formed; patterning the first semiconductor thin film using a patterning process to form a fourth insulating layer covering the second conductive layer; and a second semiconductor layer disposed on the fourth insulating layer, such as... Figure 8 As shown.

[0115] In some examples, the active layer 41 of the first transistor and the active layer 42 of the second transistor in the circuit cell of the Mth row are located on the side of the active layer 11 of the third transistor in the same row away from the circuit cell of the M+1th row.

[0116] In some examples, the second semiconductor layer of each circuit unit includes the active layer 41 of the first transistor and the active layer 42 of the second transistor. In some examples, the second region of the first transistor also serves as the first region of the second transistor.

[0117] In some examples, the active layer 41 of the first transistor and the active layer 42 of the second transistor can be in the shape of an "I".

[0118] (6) Forming a third conductive layer pattern. In some examples, forming a third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a third conductive layer pattern disposed on the fifth insulating layer. The second conductive layer pattern includes at least: a second portion 51 of a reset signal line and a second portion 52 of a second scan line, such as... Figure 9 As shown.

[0119] Combination Figure 9 and 10As shown, the second portion 51 of the reset signal line and the second portion 52 of the second scan line extend along the first direction X. The second portion 51 of the reset signal line has the same or substantially the same pattern as the first portion 32 of the reset signal line. Furthermore, the orthographic projections of the second portion 51 of the reset signal line and the first portion 32 of the reset signal line, which are disposed opposite to it, substantially coincide on the substrate; the orthographic projections of the second portion 52 of the second scan line and the first portion 33 of the second scan line, which are disposed opposite to it, substantially coincide on the substrate.

[0120] In some examples, the region where the second portion 51 of the reset signal line overlaps with the active layer 41 of the first transistor serves as the second gate of the first transistor, thus forming a dual-gate structure of the first transistor. Similarly, the region where the second portion 52 of the second scan line overlaps with the active layer 42 of the second transistor serves as the second gate of the second transistor, thus forming a dual-gate structure of the second transistor.

[0121] (7) Forming a sixth insulating layer pattern. In some examples, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the second conductive layer, wherein each circuit unit is provided with a plurality of vias, the plurality of vias including at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7 and an eighth via V8.

[0122] Combination Figure 11 As shown, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the first region of the active layer 41 of the first transistor onto the substrate. The fifth and sixth insulating layers within the first via V1 are etched away, exposing the first region of the active layer 41 of the first transistor. The first via V1 is configured to electrically connect the subsequently formed first connection electrode 62 to the first region of the first transistor.

[0123] In some examples, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the first region of the active layer 12 of the fourth transistor onto the substrate. The second, third, fourth, fifth, and sixth insulating layers within the second via V2 are etched away, exposing the first region of the active layer 12 of the fourth transistor. The second via V2 is configured to electrically connect the subsequently formed third connection electrode 64 to the first region of the active layer 12 of the fourth transistor.

[0124] In some examples, the third via V3 is located within the opening of the second electrode plate 34, and the orthographic projection of the third via V3 onto the substrate falls within the range of the orthographic projection of the gate of the third transistor onto the substrate. The third, fourth, fifth, and sixth insulating layers within the third via V3 are etched away, exposing the surface of the first electrode plate 22 of the storage capacitor. The third via V3 is configured to connect the subsequently formed fourth connection electrode 65 to the first electrode plate 22 of the storage capacitor.

[0125] The orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection range of the second region of the active layer 41 of the first transistor and the first region of the second transistor onto the substrate. The fifth and sixth insulating layers within the fourth via V4 are etched away, exposing the second region of the active layer 41 of the first transistor and the first region of the second transistor. The fourth via V4 is configured to connect the subsequently formed fourth connection electrode 65 to the second region of the active layer 41 of the first transistor and the first region of the second transistor, thereby electrically connecting the first electrode 22 (gate of the third transistor) of the storage capacitor in the pixel driving circuit to the drain of the first transistor and the source of the second transistor via the fourth connection electrode 65.

[0126] In some examples, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection range of the second region of the active layer 11 of the third transistor onto the substrate. The second, third, fourth, fifth, and sixth insulating layers within the fifth via V5 are etched away, exposing the second region of the active layer 11 of the third transistor. The fifth via V5 is configured to electrically connect the subsequently formed fifth connection electrode 66 to the second region of the third transistor.

[0127] The orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection range of the second region of the active layer 42 of the second transistor onto the substrate. The fifth and sixth insulating layers within the sixth via V6 are etched away, exposing the second region of the second transistor. The sixth via V6 is configured to electrically connect the subsequently formed fifth connection electrode 66 to the second region of the active layer 42 of the second transistor, thereby enabling the drain of the third transistor and the drain of the second transistor to be electrically connected through the fifth connection electrode 66.

[0128] In some examples, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the second region of the active layer 14 of the sixth transistor onto the substrate. The second, third, fourth, fifth, and sixth insulating layers within the seventh via V7 are etched away, exposing the second region of the active layer 14 of the sixth transistor. The seventh via V7 is configured to electrically connect the subsequently formed sixth connection electrode 67 to the second region of the active layer 14 of the sixth transistor.

[0129] In some examples, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection range of the second electrode 34 of the storage capacitor onto the substrate. The fourth, fifth, and sixth insulating layers within the eighth via V8 are etched away, exposing the surface of the second electrode 34 of the storage capacitor. The eighth via V8 is configured to electrically connect the subsequently formed second connection electrode 63 to the second electrode 34 of the storage capacitor.

[0130] (7) Forming a fourth conductive layer pattern. In some examples, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a pattern of a fourth conductive layer disposed on the sixth insulating layer. The fourth conductive layer includes at least: a first connecting electrode 62, a second connecting electrode 63, a third connecting electrode 64, a fourth connecting electrode 65, a fifth connecting electrode 66, a sixth connecting electrode 67, and a third sub-signal line 61 of the second initial signal line, such as... Figure 11 As shown.

[0131] In some examples, the third sub-signal line 61 of the second initial signal line extends in the first direction X. The third sub-signal line 61 in the Mth row of the circuit cell is located on the side of the first sub-signal line 31 in the same row of the circuit cell that is closer to the (M+1)th row of the circuit cell.

[0132] In some examples, the first connection electrode 62 in the Mth row, Nth circuit unit and the first connection electrode 62 in the Mth row, N+1th circuit unit are connected as a single structure. The first connection electrode 62 covers the first connection via and is configured to electrically connect the first sub-signal line 31 of the first initial signal line and the subsequently formed second sub-signal line 73.

[0133] In some examples, the second connection electrode 63 is a single-piece structure configured to short-circuit the subsequently formed first power line 71 to reduce resistance. The second connection electrodes 63 in every two adjacent circuit units in the first direction X are connected as a single unit. The second connection electrode 63 covers the eighth via V8, connecting the second plate 34 of the storage capacitor to the first power line 71 in subsequent models.

[0134] In some examples, the third connection electrode 64 can be a pad structure, with one third connection electrode 64 covering a second via V2. That is, the third connection electrode 64 and the second via V2 are configured to electrically connect the first region (source) of the active layer 12 of the fourth transistor to the subsequently formed data line 72.

[0135] In some examples, the fourth connection electrode 65 covers the third via V3 and the fourth via V4 and is configured to electrically connect the first plate 22 (gate of the third transistor) of the storage capacitor in the pixel driving circuit to the second region (drain) of the active layer 41 of the first transistor and the first region (source) of the active layer 42 of the second transistor through the third via V3 and the fourth via V4.

[0136] In some examples, the fifth connection electrode 66 covers the fifth via V5 and the sixth via V6 and is configured to electrically connect the second region (drain) of the active layer 11 of the third transistor in the pixel driving circuit to the second region (drain) of the active layer 42 of the second transistor through the fifth via V5 and the sixth via V6.

[0137] In some examples, the sixth connection electrode 67 covers the seventh via V7 and is configured to electrically connect the second region (drain) of the active layer 14 of the sixth transistor to the anode of the subsequently formed light-emitting device through the seventh via V7.

[0138] (8) Forming a seventh insulating layer pattern. In some examples, forming a seventh insulating layer pattern may include: depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer covering the third conductive layer, and the plurality of vias provided in each circuit unit further include: a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0139] Combination Figure 12 and 13 As shown, the orthographic projection of the ninth via V9 on the substrate is within the range of the orthographic projection of the first connection electrode 62 on the substrate. The seventh insulating layer within the ninth via V9 is etched away, exposing the first connection electrode 62. The ninth via V9 is configured to electrically connect the second sub-signal line 73 of the subsequently formed first initial signal line to the first connection electrode 62, thereby realizing the electrical connection between the first sub-signal line 31 and the second sub-signal line 73 of the first initial signal line.

[0140] In some examples, the orthographic projection of the tenth via V10 onto the substrate is within the range of the orthographic projection of the third sub-signal line 61 of the second initial signal line. The seventh insulating layer within the tenth via V10 is etched away, exposing the third sub-signal line 61 of the second initial signal line. The tenth via V10 is configured to electrically connect the subsequently formed fourth sub-signal line 74 of the second initial signal line to the first connection electrode 62, thereby achieving the electrical connection between the third sub-signal line 61 of the second initial signal line and the second fourth sub-signal line.

[0141] In some examples, the orthographic projection of the eleventh via V11 onto the substrate covers the orthographic projection of the second connection electrode 63 onto the substrate. The seventh insulating layer within the eleventh via V11 is etched away, exposing the second connection electrode 63. The eleventh via V11 is configured to electrically connect the subsequently formed first power line 71 to the second connection electrode 63 to form a conductive mesh structure, while simultaneously achieving electrical connection between the first power line 71 and the second electrode 34 of the storage capacitor.

[0142] In some examples, the orthographic projection of the twelfth via V12 onto the substrate covers the area of ​​the orthographic projection of the third connection electrode 64 onto the substrate. The seventh insulating layer within the twelfth via V12 is etched away, exposing the third connection electrode 64. The twelfth via V12 is configured to electrically connect the subsequently formed data line 72 to the third connection electrode 64, thereby electrically connecting the first region (source) of the active layer 12 of the fourth transistor to the data line 72.

[0143] In some examples, the orthographic projection of the thirteenth via V13 onto the substrate covers the orthographic projection of the sixth connection electrode 67 onto the substrate. The seventh insulating layer within the thirteenth via V13 is etched away, exposing the sixth connection electrode 67. The thirteenth via V13 is configured to electrically connect the subsequently formed seventh connection electrode 75 to the sixth connection electrode, thereby achieving electrical connection between the anode of the subsequently formed light-emitting device and the second region (drain) of the active layer 14 of the sixth transistor.

[0144] (9) Forming a pattern for the fifth conductive layer. In some examples, forming the pattern for the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a pattern of the fifth conductive layer disposed on the seventh insulating layer. The fifth conductive layer includes at least: a first power line 71, a second sub-signal line 73 of the first initial signal line, a fourth sub-signal line 74 of the second initial signal line, a data line 72, and a seventh connection electrode 75, such as... Figure 12 and 13 As shown.

[0145] In some examples, the first power line 71, the second sub-signal line 73 of the first initial signal line, the fourth sub-signal line 74 of the second initial signal line, and the data line 72 all extend along the second direction Y. The first power line 71, the second sub-signal line 73 of the first initial signal line, the fourth sub-signal line 74 of the second initial signal line, and the data line 72 can be straight lines or bent lines. Figure 12In this example, the second sub-signal line 73 of the first initial signal line, the fourth sub-signal line 74 of the second initial signal line, and the data line 72 are straight lines, while the first power line 71 is a bent line. In some examples, the first power line 71 in the circuit unit includes a first segment 71-1 and a second segment 71-2 extending along the second direction Y and electrically connected to each other; in the unit column 20, the first segment 71-1 of the first power line 71 of one of the adjacent circuit units is electrically connected to the second segment 71-2 of the other; in the unit structure 100, the spacing between adjacent second segments 71-2 in the first direction X is smaller than the spacing between adjacent first segments 71-1; in each unit structure 100, adjacent second segments 71-2 in the first direction X are short-circuited. In this case, each first power line 71 forms a conductive mesh-like structure, thereby reducing resistance.

[0146] In some examples, the second sub-signal line 73 of the first initial signal line is connected to the first connection electrode 62 through the ninth via V9 to achieve an electrical connection between the first sub-signal line 31 and the second sub-signal line 73 of the first initial signal line.

[0147] In some examples, the fourth sub-signal line 74 of the second initial signal line is electrically connected to the third sub-signal line 61 through the tenth via V10.

[0148] In some examples, the first power line 71 is connected to the second connection electrode 63 through the eleventh via V11 to achieve electrical connection between the second plate 34 of the storage capacitor and the first power line 71.

[0149] In some examples, the data line 72 is connected to the third connection electrode 64 through the twelfth via V12 to achieve electrical connection between the data line 72 and the first region of the active layer 12 of the fourth transistor.

[0150] In some examples, the seventh connection electrode 75 is electrically connected to the sixth connection electrode 67 via the thirteenth via V13 to achieve electrical connection between the drain of the sixth transistor and the anode of the subsequently formed light-emitting device.

[0151] It should be noted that, as Figure 15 As shown, only the first initial signal line includes the first sub-signal line 31 and the second sub-signal 73, which is different from the previous one. Figure 12 Regarding the first conductive layer shown, Figure 15 The first conductive layer is only missing the fourth sub-signal line 74; the rest of the structure is the same. Figure 12 Consistent. Similarly, only the second initial signal line includes the third sub-signal line 61 and the fourth sub-signal 74, which is consistent with... Figure 12 Regarding the first conductive layer shown, the first conductive layer of this display panel is only missing the second sub-signal line 73; the rest of the structure is the same. Figure 12 Since they are consistent, I will not repeat them here.

[0152] (10) Forming a first planarization layer pattern. In some examples, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, patterning the first planarization film using a patterning process to form a first planarization layer covering a fifth conductive layer, wherein a fourteenth via V14 is provided on the first planarization layer.

[0153] As shown in Figure 16, the orthographic projection of the fourteenth via V14 on the substrate is within the range of the orthographic projection of the seventh connecting electrode 75 on the substrate. The first planarization layer within the fourteenth via V14 is removed, exposing the surface of the seventh connecting electrode 75. The fourteenth via V14 is configured to allow the subsequently formed anode to be connected to the seventh connecting electrode 75 through the via.

[0154] At this point, the driving circuit layer has been fabricated on the substrate.

[0155] In some examples, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations.

[0156] (11) Forming an anode pattern. In some examples, forming an anode pattern may include: depositing a sixth conductive film on the substrate on which the aforementioned pattern is formed, patterning a fifth conductive film using a patterning process to form an anode pattern disposed on a second planarization layer, wherein the anode forms a GGRB pixel arrangement, such as... Figure 16 As shown.

[0157] Combination Figure 16 As shown, the anode pattern may include a first anode 91A of a red light-emitting device, a second anode 91B of a blue light-emitting device, a third anode 91C of a first green light-emitting device, and a fourth anode 91D of a second green light-emitting device. The area where the first anode 91A is located can form a red sub-pixel R that emits red light, the area where the second anode 91B is located can form a blue sub-pixel B that emits blue light, the area where the third anode 91C is located can form a first green sub-pixel G1 that emits green light, and the area where the fourth anode 91D is located can form a second green sub-pixel G2 that emits green light. The red sub-pixel R and the blue sub-pixel B are arranged sequentially along the second direction Y, and the first green sub-pixel G1 and the second green sub-pixel G2 are arranged sequentially along the second direction Y. The first green sub-pixel G1 and the second green sub-pixel G2 are respectively located on one side of the red sub-pixel R and the blue sub-pixel B in the first direction X. The red sub-pixel R, the blue sub-pixel B, the first green sub-pixel G1 and the second green sub-pixel G2 form a pixel unit.

[0158] In some examples, in a pixel unit, the first anode 91A is electrically connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the Mth row and Nth column, the second anode 91B is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and Nth column, the third anode 91C is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the Mth row and N+1th column, and the fourth anode 91D is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and N+1th column. In another pixel unit, the first anode 91A is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and (N+2)th column; the second anode 91B is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M)th row and (N+2)th column; the third anode 91C is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M+1)th row and (N+3)th column; and the fourth anode 91D is connected to the seventh connecting electrode 75 in the circuit unit through the fourteenth via V14 in the circuit unit of the (M)th row and (N+3)th column.

[0159] In some examples, since the seventh connection electrode 75 in at least one circuit unit is connected to the sixth connection electrode 67 through the thirteenth via V13, and the sixth connection electrode 67 is connected to the second region of the active layer 14 of the sixth transistor through the sixth via V6, the four anodes in at least one pixel unit are respectively connected to the pixel driving circuits of the four circuit units in a group of circuit units, enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0160] In some examples, the shape and position of the first anode 91A in different pixel units may be the same or different. The shape and position of the second anode 91B in different pixel units may be the same or different. The shape and position of the third anode 91C in different pixel units may be the same or different. The shape and position of the fourth anode 91D in different pixel units may be the same or different. In some examples, the two first anodes 91A connected to the pixel driving circuits in the circuit unit of row M, column N and row M+1, column N+2 respectively have the same shape and position; the two second anodes 91B connected to the pixel driving circuits in the circuit unit of row M+1, column N and row M+2 respectively have the same shape and position; the two third anodes 91C connected to the pixel driving circuits in the circuit unit of row M, column N+1 and row M+1, column N+3 respectively have the same shape and position; and the two fourth anodes 91D connected to the pixel driving circuits in the circuit unit of row M+1, column N+1 and row M+3 respectively have the same shape and position.

[0161] In some examples, the anode shapes and areas of the four sub-pixels in a pixel unit may be the same or different. In some examples, the shapes and areas of the first anode 91A, the second anode 91B, the third anode 91C, and the fourth anode 91D in a pixel unit are all different.

[0162] In some examples, the first anode 91A in the red sub-pixel may include a first anode body portion, the shape of which may be a hexagonal shape. In an exemplary embodiment, the first anode 91A may further include a first protrusion 91-1 and a second protrusion 91-2, both of which are connected to the first anode body portion. The first protrusion 91-1 may be a rectangle protruding toward the gate electrode of the third transistor T3 in the connected pixel driving circuit, and the second protrusion 91-2 may be a rectangle protruding toward the sixth transistor T6 in the connected pixel driving circuit. The first protrusion 91-1 and the second protrusion 91-2 are configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance between adjacent circuit units of the N3 node, thereby reducing brightness differences and improving display performance.

[0163] In some examples, the second anode 91B in the blue sub-pixel may include a second anode body, the shape of which may be a hexagonal shape. In an exemplary embodiment, the second anode 91B may further include a third protrusion 91-3, a fourth protrusion 91-4, and a fifth protrusion 91-5, all of which are connected to the second anode body. The third protrusion 91-3 may be a rectangle protruding toward the first power line 71 in the connected pixel driving circuit, the fourth protrusion 91-4 may be a rectangle protruding away from the first power line 71 in the connected pixel driving circuit, and the fifth protrusion 91-5 may be a polygon protruding toward the sixth transistor T6 in the connected pixel driving circuit. The third protrusion 91-3, the fourth protrusion 91-4, and the fifth protrusion 91-5 are configured to adjust the parasitic capacitance of the connection nodes in the connected pixel driving circuit, reducing the difference in parasitic capacitance between the connection nodes in adjacent circuit units, thereby reducing brightness differences and improving display performance.

[0164] In some examples, the third anode 91C may include a third anode body portion, the shape of which may be a pentagonal shape. In an exemplary embodiment, the third anode 91C may further include a sixth protrusion 91-6, which is connected to the third anode body portion. The sixth protrusion 91-6 may be a rectangle protruding toward the sixth transistor T6 in the connected pixel driving circuit. The sixth protrusion 91-6 is configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance between the N3 nodes in adjacent circuit units, thereby reducing brightness differences, particularly reducing the brightness difference between the current sub-pixel and the second green sub-pixel, and improving the display effect.

[0165] In some examples, the fourth anode 91D may include a fourth anode body portion, the shape of which may be a pentagonal shape. In an exemplary embodiment, the fourth anode 91D may further include a seventh protrusion 91-7, which is connected to the fourth anode body portion. The seventh protrusion 91-7 may be a strip protruding toward the gate electrode of the third transistor T3 in the connected pixel driving circuit. The seventh protrusion 91-7 is configured to adjust the parasitic capacitance of the N3 node in the connected pixel driving circuit, reducing the difference in parasitic capacitance between the N3 nodes in adjacent circuit units, thereby reducing brightness differences, particularly reducing the brightness difference between the current sub-pixel and the first green sub-pixel, and improving the display effect.

[0166] (12) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film by a patterning process to form a pixel definition layer pattern.

[0167] The pixel definition layer 72 pattern may include a first pixel opening 73A that exposes a first anode 91A, a second pixel opening 73B that exposes a second anode 91B, a third pixel opening 73C that exposes a third anode 91C, and a fourth pixel opening 73D that exposes a fourth anode 91D.

[0168] In some examples, subsequent fabrication processes may include: forming an organic light-emitting layer using vapor deposition or inkjet printing; the organic light-emitting layer being connected to an anode through pixel openings; forming a cathode on the organic light-emitting layer; and connecting the cathode to the organic light-emitting layer. An encapsulation layer is then formed, which may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is positioned between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.

[0169] In some examples, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz, while the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0170] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, fifth conductive layer, and shielding electrode layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer, sixth insulating layer, seventh insulating layer, and first planarization layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The first semiconductor layer can be made of silicon-containing materials such as amorphous silicon (a-Si) or polycrystalline silicon (p-Si). The second semiconductor layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), or other oxide materials. The first planarization layer can be made of organic materials, such as resin. The sixth conductive layer can be a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multi-layer composite structure, such as ITO / Ag / ITO. The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate. The cathode can be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals.

[0171] As can be seen from the structure and manufacturing process of the display panel described above, the display panel provided in this disclosure uses a first sub-signal line 31 extending along the first direction X and a second sub-signal line 73 extending along the second direction Y as the first initial signal line, and / or uses a third sub-signal line 61 extending along the first direction X and a fourth sub-signal line 74 extending along the second direction Y as the second initial signal line, so that at least one of the first initial signal line and the second initial signal line forms a mesh structure. This not only effectively reduces the resistance of the initial signal line and reduces the voltage drop of the initial voltage, but also effectively improves the uniformity of the initial voltage in the display panel, effectively improves the display uniformity, and improves the display quality.

[0172] Secondly, embodiments of this disclosure provide a display device, which includes the aforementioned display panel. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; embodiments of this invention are not limited thereto.

[0173] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the protection scope of the present invention.

Claims

1. A display panel comprising: A substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the side of the driving circuit layer facing away from the substrate; The driving circuit layer includes multiple circuit units, and the light-emitting structure layer includes multiple light-emitting devices; at least one circuit unit includes multiple initial signal lines and a pixel driving circuit; the pixel driving circuit includes multiple transistors, and the multiple transistors include at least one oxide thin-film transistor and at least one low-temperature polycrystalline silicon thin-film transistor. Each of the plurality of initial signal lines includes a sub-signal line along a first direction, and at least one of the plurality of initial signal lines includes a sub-signal line extending along a second direction; the first direction and the second direction intersect; the sub-signal line extending in the first direction and the sub-signal line extending in the second direction of the initial signal line are electrically connected. The driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged sequentially along the direction away from the substrate. The first semiconductor layer includes the active layer of the low-temperature polycrystalline silicon thin-film transistor; The first conductive layer includes the gate of the low-temperature polycrystalline silicon thin-film transistor; The second conductive layer includes a first gate of the oxide thin-film transistor and at least one sub-signal line extending along the first direction; The second semiconductor layer includes the active layer of the oxide thin-film transistor; The third conductive layer includes the second gate of the oxide thin-film transistor; The fourth conductive layer includes at least one sub-signal line extending along the first direction; The fifth conductive layer includes sub-signal lines extending along the second direction; The plurality of initial signal lines includes a first initial signal line and a second initial signal line; At least one sub-signal line extending along the first direction in the second conductive layer includes a first sub-signal line of the first initial signal line; At least one sub-signal line extending along the first direction in the fourth conductive layer includes a third sub-signal line of the second initial signal line. The sub-signal lines extending along the second direction in the fifth conductive layer include a second sub-signal line of the first initial signal line and / or a fourth sub-signal line of the second initial signal line. The driving circuit layer includes multiple cell rows and multiple cell columns. The cell row includes multiple circuit cells arranged side by side along the first direction; the cell column includes multiple circuit cells arranged side by side along the second direction. When the first initial signal line includes the first sub-signal line and the second sub-signal line, in at least one of the unit columns, the second sub-signal lines in adjacent circuit units are interconnected. When the second initial signal line includes a third sub-signal line and the fourth sub-signal line, in at least one of the unit columns, the fourth sub-signal lines in adjacent circuit units are interconnected.

2. The display panel according to claim 1, wherein, When the first initial signal line includes the first sub-signal line and the second sub-signal line; the fourth conductive layer further includes a plurality of first connection electrodes; the first sub-signal line is electrically connected to the first region of the active layer of the first transistor in the pixel driving circuit through a via; the first region of the active layer of the first transistor is electrically connected to the first connection electrode through a via; the first connection electrode is electrically connected to the second sub-signal line through a via; When the second initial signal line includes the third sub-signal line and the fourth sub-signal line, the third sub-signal line is electrically connected to the fourth sub-signal line through a via.

3. The display panel according to claim 1, wherein, The plurality of light-emitting devices include a red light-emitting device, a first green light-emitting device, a second green light-emitting device, and a blue light-emitting device; the plurality of circuit units include a first circuit unit electrically connected to the red light-emitting device, a second circuit unit electrically connected to the blue light-emitting device, a third circuit unit electrically connected to the first green light-emitting device, and a fourth circuit unit electrically connected to the second green light-emitting device; the plurality of unit columns include a first unit column and a second unit column, the first unit column including the first circuit unit and the second circuit unit alternately arranged along the second direction, and the second unit column including the third circuit unit and the fourth circuit unit alternately arranged along the second direction; When the first initial signal line includes the first sub-signal line and the second sub-signal line, at least a portion of the second sub-signal line is disposed in the second cell column; When the second initial signal line includes a third sub-signal line and the fourth sub-signal line, at least a portion of the fourth sub-signal line is disposed in the second unit column.

4. The display panel according to claim 3, wherein, The fifth conductive layer also includes multiple first power lines; in the same unit column, the first power lines in adjacent circuit units are interconnected. The second sub-signal line and the fourth sub-signal line are located between the first power lines in the two cell columns to which they are connected.

5. The display panel according to claim 4, wherein, The driving circuit layer includes multiple unit structures arranged side by side along the first direction; each unit structure includes two adjacent unit columns. The first power line in the circuit unit includes a first segment and a second segment that extend along a second direction and are electrically connected to each other; in the unit column, the first segment of the first power line of one of the adjacent circuit units is electrically connected to the second segment of the other; in the unit structure, the spacing between adjacent second segments in the first direction is smaller than the spacing between adjacent first segments. The fourth conductive layer further includes a plurality of second connecting electrodes; in the unit structure, the second connecting electrodes electrically connect the second line segments arranged adjacent to each other in the first direction through vias.

6. The display panel according to claim 4, wherein, The fifth conductive layer also includes multiple data lines; in the unit column, adjacent data lines are interconnected. The first power line includes a first side and a second side disposed opposite to each other along a first direction; the data line in the first unit column is located on the first side of the first power line, and the data line in the second unit column is located on the second side of the first power line.

7. The display panel according to claim 6, wherein, The circuit unit further includes a third connection electrode; the first region of the active layer of the fourth transistor is electrically connected to the third connection electrode through a via; the third connection electrode is electrically connected to the data line through a via.

8. The display panel according to claim 1, wherein, The fourth conductive layer further includes a plurality of fourth connection electrodes; the fourth connection electrodes are electrically connected to the gate of the third transistor in the pixel driving circuit through vias; the second region of the active layer of the first transistor and the first region of the second transistor in the pixel driving circuit are electrically connected to the fourth connection electrodes through vias.

9. The display panel according to claim 1, wherein, The fourth conductive layer further includes a plurality of fifth connection electrodes; the fifth connection electrodes are electrically connected to the second region of the active layer of the third transistor in the pixel driving circuit through vias, and the second region of the active layer of the second transistor in the pixel driving circuit is electrically connected to the fifth connection electrodes through vias.

10. The display panel according to claim 1, wherein, The fourth conductive layer further includes a plurality of sixth connecting electrodes and a plurality of seventh connecting electrodes; the sixth connecting electrodes are electrically connected to the second region of the active layer of the sixth transistor through vias; the sixth connecting electrodes are electrically connected to the seventh connecting electrodes through vias; the anode of the light-emitting device is electrically connected to the seventh connecting electrodes through vias.

11. The display panel according to any one of claims 1-10, wherein, It also includes a shielding electrode layer located on the side of the first semiconductor layer near the substrate; the shielding electrode layer includes a plurality of shielding electrodes; the orthogonal projection of the shielding electrodes on the substrate covers the orthogonal projection of the active layer of the third transistor of the pixel driving circuit on the substrate.

12. The display panel according to claim 11, wherein, The shielding electrodes arranged side by side along the first direction are electrically connected; the shielding electrodes arranged side by side along the second direction are electrically connected.

13. The display panel according to claim 11, wherein, The shielding electrode layer is electrically connected to the first power line through a via.

14. The display panel according to any one of claims 1-10, wherein, The first conductive layer also includes a first scan line, a light emission control line, and a first plate of a storage capacitor in the pixel driving circuit; The second conductive layer also includes a second electrode of a storage capacitor, a first portion of a second scan line, and a first portion of a first reset signal line; The third conductive layer also includes a second portion of the second scan line and a second portion of the first reset signal line.

15. A display device comprising a display panel according to any one of claims 1-14.

Images