Differential signal amplitude detection circuit, method, receiving circuit and data security method

Abstract

The application discloses a differential signal amplitude detection circuit, a method, a receiving circuit and a data security method. The amplitude detection module of the differential signal amplitude detection circuit receives a differential signal and obtains an input peak voltage of the differential signal, a reference peak voltage obtaining module receives the differential signal and obtains a reference peak voltage of the differential signal, a comparison module compares the input peak voltage and the reference peak voltage to compare an input differential voltage with a reference differential threshold, a first comparison signal is output according to a comparison result, and whether the amplitude of the differential signal meets a requirement can be known according to the first comparison signal, so that whether the differential signal is in an abnormal state of open circuit, suspension or short circuit can be known. Therefore, the differential signal amplitude detection circuit can accurately identify and judge the abnormal state of the differential signal open circuit, suspension or short circuit.

Description

Technical Field

[0001] This application relates to the field of differential signal comparator technology, and in particular to a differential signal amplitude detection circuit, method, receiving circuit, and data preservation method. Background Technology

[0002] LVDS (Low-Voltage Differential Signaling) is a serial interface technology for high-speed data transmission from a transmitter to a receiver. It boasts advantages such as high speed, low power consumption, low noise, and low cost, leading to its widespread application. In data transmission devices employing LVDS (such as…) Figure 1 As shown in the diagram, to ensure the stability and reliability of the data transmission device, the differential signal comparator needs to be equipped with a fail-safe circuit or a data protection circuit to detect whether there are any abnormalities in the signal received at the receiver end of the differential signal comparator. When an abnormality is detected in the receiver signal, the state of the receiver's output signal is controlled so that the data output by the receiver can be controlled. For example, when the receiver signal is abnormal, the data protection circuit controls the receiver's output to maintain a high logic level to indicate that the differential signal is abnormal and to prevent errors in the data transmission device. The receiver end of a differential signal comparator may generally experience three abnormal conditions: open circuit, floating (suspended) receiver, and short circuit receiver. In other words, the signal at the receiver end of the differential signal comparator may exhibit all three of these abnormal conditions. However, existing data protection circuits have many shortcomings; they can only detect one or two of these abnormal states, and the detection accuracy is low. Summary of the Invention

[0003] The main objective of this application is to provide a differential signal amplitude detection circuit, method, receiving circuit, and data preservation method, aiming to solve the problems existing in the detection of signal anomalies at the receiver end of the differential signal comparator in the prior art.

[0004] The first embodiment of this application provides a differential signal amplitude detection circuit for detecting the amplitude of a differential signal. The differential signal amplitude detection circuit includes:

[0005] A first receiving end and a second receiving end, wherein the first receiving end and the second receiving end are used to receive the differential signal;

[0006] An amplitude detection module is connected to the first receiving end and the second receiving end to obtain the input peak voltage of the differential signal. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal.

[0007] A reference peak voltage acquisition module, connected to the first receiving end and the second receiving end, acquires the input common-mode voltage of the differential signal, and acquires a reference peak voltage of the differential signal based on the input common-mode voltage. The reference peak voltage is related to the sum of the input common-mode voltage and a reference differential threshold of the differential signal.

[0008] The comparison module has a first input terminal connected to the output terminal of the amplitude detection module to receive the input peak voltage; and a second input terminal connected to the output terminal of the reference peak voltage acquisition module to receive the reference peak voltage. The comparison module is used to compare the input peak voltage with the reference peak voltage and output a first comparison signal based on the comparison result.

[0009] As an optional implementation of the first embodiment, the reference peak voltage acquisition module includes:

[0010] An acquisition unit is connected to the first receiving end and the second receiving end to receive the differential signal and acquire the input common-mode voltage based on the differential signal.

[0011] An adjustment unit is provided, the input terminal of which is connected to the acquisition unit to receive the input common-mode voltage, and the output terminal of which is connected to the second input terminal of the comparison module; the adjustment unit is used to adjust and obtain the reference peak voltage according to the input common-mode voltage and the reference differential threshold, and then output the reference peak voltage.

[0012] As an optional implementation of the first embodiment, the acquisition unit includes a first resistor unit and a second resistor unit, the resistance values ​​of the first resistor unit and the second resistor unit are substantially the same, the first resistor unit and the second resistor unit are connected in series between the first receiving end and the second receiving end to receive the differential signal, and the voltage at the connection point between the first resistor unit and the second resistor unit is the input common-mode voltage; and

[0013] The input terminal of the adjustment unit is connected to the connection point between the first resistor unit and the second resistor unit to receive the input common-mode voltage.

[0014] As an optional implementation of the first embodiment, the adjustment unit includes an operational amplifier, a current source, and a third resistor unit;

[0015] The non-inverting input of the operational amplifier is connected to the acquisition unit to receive the input common-mode voltage. The inverting input of the operational amplifier is connected to the output of the operational amplifier. The output of the operational amplifier is connected to the first terminal of the third resistor unit. The second terminal of the third resistor unit is connected to the output of the current source and the adjustment unit to output the reference peak voltage to the second input of the comparison module.

[0016] Wherein, the voltage difference across the third resistor unit is the reference differential threshold; the adjustment unit sets the reference differential threshold by adjusting the output current of the current source and / or the resistance value of the third resistor unit, and the voltage at the connection point between the current source and the third resistor unit is the sum of the input common-mode voltage and the reference differential threshold.

[0017] As an optional implementation of the first embodiment, the amplitude detection module includes a first diode, a second diode, and an RC parallel unit;

[0018] The first diode and the second diode have substantially the same forward voltage; the anode of the first diode is connected to the first receiving terminal, and the anode of the second diode is connected to the second receiving terminal, so as to receive the differential signal;

[0019] The cathode of the first diode is connected together with the cathode of the second diode and connected to the first input terminal of the comparator module to output the input peak voltage to the first input terminal of the comparator module;

[0020] One end of the RC parallel unit is connected to the first input terminal of the comparator module, and the other end of the RC parallel unit is grounded.

[0021] As an optional implementation of the first embodiment, the adjustment unit further includes a third diode, and the second terminal of the third resistor unit and the current source are connected to the output terminal of the adjustment unit through the third diode;

[0022] The forward voltage of the third diode is substantially the same as that of the first diode and the second diode, and the voltage at the output of the adjustment unit is the sum of the input common-mode voltage and the reference differential threshold minus the forward voltage.

[0023] As an optional implementation of the first embodiment, the comparison module includes a first comparator, the first input terminal of the first comparator being connected to the cathode of the first diode and the cathode of the second diode to receive the input peak voltage;

[0024] The second input terminal of the first comparator is connected to the cathode of the third diode to receive the reference peak voltage;

[0025] Wherein, the input peak voltage is equal to the sum of the input common-mode voltage and half of the input differential voltage minus the turn-on voltage, and the reference peak voltage is equal to the sum of the input common-mode voltage and the reference differential threshold minus the turn-on voltage. The first comparator determines whether half of the input differential voltage is greater than or equal to the reference differential threshold by determining whether the input peak voltage is greater than or equal to the reference peak voltage.

[0026] As an optional implementation of the first embodiment, the amplitude detection module includes a first diode, a second diode, and two RC parallel units, and the comparison module includes a second comparator, a third comparator, and a judgment unit;

[0027] The first diode and the second diode have essentially the same forward voltage. The anode of the first diode is connected to the first receiving terminal, and the cathode of the first diode is connected to the first input terminal of the second comparator and one end of one of the RC parallel units. The other end of the RC parallel unit is grounded. The second input terminal of the second comparator is connected to the reference peak voltage acquisition module. The second comparator is used to determine whether the peak voltage of the first receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal according to the determination result.

[0028] The anode of the second diode is connected to the second receiving terminal, and the cathode of the second diode is connected to the first input terminal of the third comparator and one end of another RC parallel unit, the other end of which is grounded; the second input terminal of the third comparator is connected to the reference peak voltage acquisition module, and the third comparator is used to determine whether the peak voltage of the second receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal according to the determination result;

[0029] The first input terminal of the judgment unit is connected to the output terminal of the second comparator, and the second input terminal of the judgment unit is connected to the output terminal of the third comparator. The judgment unit is used to output the first comparison signal based on the output signals of the second comparator and the third comparator.

[0030] The second embodiment of this application provides a differential signal receiving circuit, including a first differential input terminal, a second differential input terminal, a differential signal comparator, a common-mode voltage detection circuit, a judgment circuit, and a differential signal amplitude detection circuit as described above;

[0031] The first differential input terminal and the second differential input terminal are used to receive differential signals;

[0032] The first input terminal and the second input terminal of the differential signal comparator are respectively connected to the first differential input terminal and the second differential input terminal to receive the differential signal. The differential signal comparator is used to generate a data signal based on the differential signal.

[0033] The first receiving end and the second receiving end of the differential signal amplitude detection circuit are respectively connected to the first differential input end and the second differential input end to receive the differential signal;

[0034] The common-mode voltage detection circuit is connected to the reference peak voltage acquisition module of the differential signal amplitude detection circuit to receive the input common-mode voltage. The common-mode voltage detection circuit is used to compare the input common-mode voltage with the reference common-mode voltage and output a second comparison signal according to the comparison result.

[0035] The judgment circuit is connected to the output terminal of the comparison module of the differential signal amplitude detection circuit and the output terminal of the common mode voltage detection circuit to receive the first comparison signal and the second comparison signal respectively. The judgment circuit is used to determine whether the differential signal is abnormal based on the first comparison signal and the second comparison signal, and outputs an indication signal to characterize whether the differential signal is abnormal.

[0036] As an optional implementation of the second embodiment, a data preservation circuit is further included. The data preservation circuit is connected to the output of the differential signal comparator and the output of the judgment circuit. The data preservation circuit is used to output a data preservation signal based on the data signal and the indication signal. When the indication signal indicates that the differential signal is normal, the data preservation circuit outputs the data signal as the data preservation signal. When the indication signal indicates that the differential signal is abnormal, the data preservation circuit keeps the data preservation signal in the same state.

[0037] The third embodiment of this application provides a method for detecting the amplitude of a differential signal, including:

[0038] Receive differential signals;

[0039] The input common-mode voltage and input peak voltage of the differential signal are obtained based on the differential signal, and the input peak voltage is related to the sum of half of the input common-mode voltage and the input differential voltage of the differential signal;

[0040] Obtain a reference peak voltage of the differential signal, the reference peak voltage being related to the sum of the input common-mode voltage and the reference differential threshold;

[0041] The input peak voltage is compared with the reference peak voltage, and a first comparison signal is output based on the comparison result.

[0042] As an optional implementation of the third embodiment, obtaining the reference peak voltage of the differential signal includes:

[0043] The reference difference threshold is preset;

[0044] The reference peak voltage is generated based on the reference differential threshold and the input common-mode voltage, such that the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold.

[0045] The fourth embodiment of this application provides a method for data preservation of differential signals, including:

[0046] Receive differential signals;

[0047] The input common-mode voltage and input peak voltage of the differential signal are obtained based on the differential signal, and the input peak voltage is related to the sum of half of the input common-mode voltage and the input differential voltage of the differential signal;

[0048] Obtain a reference peak voltage of the differential signal, the reference peak voltage being related to the sum of the input common-mode voltage and the reference differential threshold;

[0049] The input peak voltage is compared with the reference peak voltage, and a first comparison signal is output based on the comparison result;

[0050] The input common-mode voltage is compared with the reference common-mode voltage, and a second comparison signal is output based on the comparison result;

[0051] Based on the first comparison signal and the second comparison signal, determine whether the differential signal is abnormal, and generate an indication signal to characterize whether the differential signal is abnormal;

[0052] The corresponding data signal is generated based on the differential signal;

[0053] A data preservation signal is output based on the data signal and the indication signal; when the indication signal indicates that the differential signal is normal, the data signal is output as the data preservation signal; when the indication signal indicates that the differential signal is abnormal, the data preservation signal is kept in the same state.

[0054] As an optional implementation of the fourth embodiment, obtaining the reference peak voltage of the differential signal includes:

[0055] The reference difference threshold is preset;

[0056] The reference peak voltage is generated based on the reference differential threshold and the input common-mode voltage, such that the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold.

[0057] Compared with the prior art, this application has the following advantages:

[0058] 1. In the differential signal amplitude detection circuit of this application, the amplitude detection module acquires the input peak voltage of the differential signal, and the reference peak voltage acquisition module acquires the input common-mode voltage of the differential signal and acquires a reference peak voltage based on the input common-mode voltage. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal, and the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold of the differential signal. The comparison module compares the input peak voltage and the reference peak voltage to determine whether the amplitude of the differential signal meets the requirements, and outputs a first comparison signal based on the comparison result. Based on the first comparison signal, it can be determined whether the amplitude of the differential signal meets the requirements, thereby determining whether the differential signal is in an abnormal state of open circuit, floating, or short circuit. Therefore, the differential signal amplitude detection circuit of this application can identify and determine the abnormal state of open circuit, floating, or short circuit of the differential signal.

[0059] 2. In the differential signal receiving circuit of this application, the common-mode voltage detection circuit compares the input common-mode voltage of the differential signal with the reference common-mode voltage, and outputs a second comparison signal based on the comparison result; the judgment circuit combines the first comparison signal output by the differential signal amplitude detection circuit and the second comparison signal output by the common-mode voltage detection circuit to determine whether the differential signal is abnormal, which can more accurately determine whether the differential signal is abnormal.

[0060] 3. The differential signal receiving circuit also includes a data preservation circuit. This circuit generates a data preservation signal based on the indicator signal output from the judgment circuit and the data signal from the differential signal comparator. When the indicator signal indicates that the differential signal is normal, the data preservation circuit outputs a data signal as the data preservation signal, ensuring the normal operation of subsequent circuits. When the indicator signal indicates that the differential signal is abnormal, the data preservation circuit maintains the data preservation signal in the same state, allowing subsequent circuits to react quickly and execute corresponding actions, preventing damage or malfunction of subsequent circuits. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0062] Figure 1This is a schematic diagram of the circuit principle of a differential signal comparator.

[0063] Figure 2 This is a schematic diagram showing the relationship between the common-mode voltage, differential voltage, and amplitude voltage of a differential signal comparator.

[0064] Figure 3 This is a schematic diagram of the external resistor-type data protection circuit of an existing differential signal comparator.

[0065] Figure 4 This is a schematic diagram of the built-in data preservation circuit of an existing differential signal comparator.

[0066] Figure 5 This is a schematic diagram of the parallel data preservation circuit of an existing differential signal comparator.

[0067] Figure 6 This is a schematic diagram of a differential signal receiving circuit provided in one embodiment of this application.

[0068] Figure 7 This is a schematic diagram of the differential signal amplitude detection circuit provided in the embodiments of this application.

[0069] Figure 8 This is a schematic diagram of a differential signal receiving circuit provided in another embodiment of this application.

[0070] Figure 9 yes Figure 8 A schematic diagram of the circuit principle of the adjustment unit.

[0071] Figure 10 This is a schematic diagram of the circuit principle of the adjustment unit in another embodiment.

[0072] Figure 11 This is a schematic diagram of a differential signal receiving circuit provided in another embodiment of this application.

[0073] Figure 12 This is a schematic flowchart of the differential signal amplitude detection method provided in the embodiments of this application.

[0074] Figure 13 yes Figure 12 A schematic diagram of the specific process for step S30.

[0075] Figure 14 This is a flowchart illustrating the data preservation method for differential signals provided in the embodiments of this application.

[0076] Explanation of key component symbols: Terminating resistor Rt

[0077] Differential signal receiving circuit 1

[0078] Differential signal comparator 10

[0079] Differential signal amplitude detection circuit 20

[0080] Amplitude detection module 21

[0081] First diode D1

[0082] Second diode D2

[0083] RC parallel unit 210

[0084] Reference peak voltage acquisition module 22

[0085] Acquisition Unit 220

[0086] First resistor unit R1

[0087] Second resistor unit R2

[0088] Adjustment unit 221

[0089] Operational amplifier U1

[0090] Current source CS

[0091] Third resistor unit R3

[0092] Third diode D3

[0093] Comparison Module 23

[0094] First comparator U2

[0095] Second comparator U3

[0096] Third comparator U4

[0097] Judgment Unit U5

[0098] Common-mode voltage detection circuit 30

[0099] Fourth comparator U6

[0100] Fourth resistor unit R4

[0101] Judgment Circuit 40

[0102] Data preservation circuit 50

[0103] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0104] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0105] The terms "first" and "second," etc., used in the specification and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising," and any variations thereof, is intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to these processes, methods, products, or apparatuses.

[0106] For the three possible abnormal states of the signal at the receiver of an LVDS comparator (open circuit, floating, short circuit), the commonly used fault protection circuits include: external resistor fault protection circuit, in-path fault protection circuit, and parallel fault protection circuit.

[0107] Among them, such as Figure 3 As shown, the external resistor-based fault protection circuit consists of three external resistors Ra and Rb connected in series to the signal pins of the LVDS comparator's receiver, and a terminating resistor Rt. When the signal pins of the LVDS comparator's receiver are open or floating, a positive bias voltage is applied to the signal pins, causing the LVDS comparator to output a logic high level. The external resistor-based fault protection circuit has a simple structure and was widely used in early LVDS comparators. However, it still has several drawbacks: for systems with multiple LVDS comparators, the external resistor-based fault protection circuit requires additional external resistors; at the high data transmission rate of the LVDS comparator, the unbalanced receiver threshold voltage generated by the differential voltage VID bias can lead to significant duty cycle distortion and increased jitter, and it is not suitable for short-circuit faults at the LVDS input pins.

[0108] like Figure 4As shown, the path-integrated fault protection circuit consists of the internal resistors Rc, Rd, Re, and Rf of the LVDS comparator and the external terminating resistor Rt. Even if the signal pins at the receiver end of the LVDS comparator are open or short-circuited, the output of the LVDS comparator can still output a high logic level. However, it still has the following drawbacks: it does not have the flexibility of adjustable bias voltage, resulting in an unbalanced receiver threshold, degrading duty cycle performance and increasing jitter. Furthermore, the path-integrated noise margin is low, resulting in low noise immunity of the LVDS comparator.

[0109] In this context, noise margin can be understood as the difference between the carrier-to-noise ratio of the received signal and the carrier-to-noise ratio of the bit error rate. It reflects the system's ability to withstand additional noise, and the larger the noise margin, the stronger the system's noise immunity.

[0110] like Figure 5 As shown, the parallel fault protection circuit overcomes the main drawbacks of external resistor-based and path-embedded fault protection circuits. The parallel fault protection circuit detects the common-mode voltage at the LVDS input pin using a comparator; when the common-mode voltage is higher than the reference voltage, it outputs a high logic level. However, for multi-point or long-distance point-to-point applications, the common-mode load capacitance increases. When a fault occurs, the common-mode load capacitance needs to be charged, increasing the activation delay of the fault protection function. To achieve noise suppression of the input signal, a hysteresis circuit needs to be added to the comparator circuit. However, the hysteresis circuit increases inter-symbol interference on the signal path, thereby increasing the bit error rate at the receiver.

[0111] Clearly, the existing fault protection circuits have many shortcomings, as they can only detect one or two abnormal situations and have low detection accuracy.

[0112] In response, this application provides a differential signal receiving circuit that can identify three abnormal states that may occur in the signal at the receiving end of the differential signal comparator, and has high detection sensitivity.

[0113] like Figure 6 , Figure 8 and Figure 11 As shown, the differential signal receiving circuit 1 includes a first differential input terminal, a second differential input terminal, a differential signal comparator 10, a differential signal amplitude detection circuit 20, a common-mode voltage detection circuit 30, and a judgment circuit 40.

[0114] The first differential input terminal and the second differential input terminal are used to receive differential signals. The first input terminal and the second input terminal of the differential signal comparator 10 are respectively connected to the first differential input terminal and the second differential input terminal to receive differential signals. The differential signal comparator 10 is used to generate corresponding data signals based on the differential signals. For example... Figure 2 As shown, Figure 2 The diagram shows the signal waveforms of the differential signals received at the first and second input terminals of the differential signal comparator 10, as well as the data signal at its output terminal. The differential signals include the first signal VIN+ and the second signal VIN-. Vout is the data stream output from the differential signal comparator 10, i.e., the data signal. VH and VL are the highest and lowest amplitudes of the differential signals, respectively. VCM is the input common-mode voltage of the differential signals, which is the average value of the differential signal amplitudes, i.e., VCM = (VH + VL) / 2. VID is the input differential voltage of the differential signals, which is the difference in amplitudes of the differential signals, i.e., VID = VH - VL. Figure 2 As shown, the peak voltage of the differential signal can be obtained as: VCM + VID / 2.

[0115] In some embodiments, the differential signal comparator 10 may be an LVDS comparator. An external terminating resistor Rt is connected between the first and second input terminals of the LVDS comparator. Current flows through the terminating resistor Rt to generate a voltage difference between the first and second input terminals of the LVDS comparator, thereby generating a differential signal.

[0116] Please see Figure 7 The differential signal amplitude detection circuit 20 includes a first receiving end and a second receiving end, as well as an amplitude detection module 21, a reference peak voltage acquisition module 22, and a comparison module 23.

[0117] The amplitude detection module 21 is connected to the first receiving end and the second receiving end to obtain the input peak voltage of the differential signal. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal.

[0118] The reference peak voltage acquisition module 22 is also connected to the first receiver and the second receiver to acquire the reference peak voltage of the differential signal. The reference peak voltage is related to the sum of the input common-mode voltage of the differential signal and the reference differential threshold.

[0119] It is understood that in this application, the input differential voltage refers to the actual differential voltage of the differential signal (e.g., the actual differential voltage between the first signal VIN+ and the second signal VIN-, such as...). Figure 2 The reference differential threshold is the threshold voltage value of the differential voltage VID expected when the differential signal meets performance requirements (e.g., amplitude requirements). This reference differential threshold can be adjusted according to actual application needs; for example, it can be adjusted to 25mV, 50mV, 100mV, 150mV, 200mV, etc. Therefore, the reference peak voltage is the expected or reference value of the peak voltage preset according to the actual performance requirements of the differential signal.

[0120] The first input terminal of the comparison module 23 is connected to the output terminal of the amplitude detection module 21 to receive the input peak voltage, and the second input terminal of the comparison module 23 is connected to the output terminal of the reference peak voltage acquisition module 22 to receive the reference peak voltage. The comparison module 23 is used to compare the input peak voltage with the reference peak voltage and output a first comparison signal according to the comparison result. Since the input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal, and the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold of the differential signal, comparing the input peak voltage and the reference peak voltage is equivalent to comparing half of the input differential voltage with the reference differential threshold.

[0121] When the differential signal is normal, its input peak voltage meets the performance requirements, resulting in a sufficiently large input peak voltage that is greater than or equal to the reference peak voltage. However, when the differential signal is in any of the abnormal conditions of open circuit, floating, or short circuit, the amplitude of the differential signal is zero or insufficient, causing the input peak voltage acquired by the amplitude detection module to be less than the reference peak voltage. The comparison module 23 outputs a first comparison signal with different levels by comparing the magnitude of the input peak voltage and the reference peak voltage. For example, when the input peak voltage is greater than or equal to the reference peak voltage, the comparison module 23 outputs a low-level first comparison signal, while when the input peak voltage is less than the reference peak voltage, the comparison module 23 outputs a high-level first comparison signal, and vice versa.

[0122] Therefore, based on the level of the first comparison signal output by the differential signal amplitude detection circuit 20 of this application, it is possible to determine whether the amplitude of the differential signal meets the performance requirements, thereby determining whether the differential signal is abnormal.

[0123] Combination Figure 7 , Figure 8 and Figure 10 As shown, the reference peak voltage acquisition module 22 includes an acquisition unit 220 and an adjustment unit 221.

[0124] The acquisition unit 220 is connected to the first receiving end and the second receiving end to receive the differential signal. The acquisition unit 220 is used to acquire the input common-mode voltage based on the received differential signal.

[0125] The input terminal of the adjustment unit 221 is connected to the acquisition unit 220 to receive the input common-mode voltage, and the output terminal of the adjustment unit 221 is connected to the second input terminal of the comparison module 23. The adjustment unit 221 is used to adjust and output a reference peak voltage based on the input common-mode voltage and a reference differential threshold.

[0126] By setting the reference differential threshold through the adjustment unit 221, the reference differential threshold can be set according to the magnitude of the input differential voltage VID required for the actual application of the differential signal to be detected, thereby enabling the differential signal amplitude detection circuit 20 of this application to adapt to differential signals with different parameter requirements, so as to expand the application range of the differential signal amplitude detection circuit 20.

[0127] Combination Figure 8 and Figure 9 As shown, the acquisition unit 220 may include a first resistor unit R1 and a second resistor unit R2. The resistance values ​​of the first resistor unit R1 and the second resistor unit R2 are substantially the same. The first resistor unit R1 and the second resistor unit R2 are connected in series between the first receiving end and the second receiving end to receive the differential signal. The voltage at the connection point of the first resistor unit R1 and the second resistor unit R2 is the input common-mode voltage, that is, the input common-mode voltage of the differential signal can be obtained from the connection point between the first resistor unit R1 and the second resistor unit R2. By connecting the first receiving end and the second receiving end in series with the first resistor unit R1 and the second resistor unit R2 having the same resistance value, the voltage at the connection point of the first resistor unit R1 and the second resistor unit R2 can be the input common-mode voltage of the differential signal based on the voltage of the first receiving end and the second receiving end and the voltage division effect of the first resistor unit R1 and the second resistor unit R2. The first resistor unit R1 and the second resistor unit R2 can each be a single resistor, or at least one resistor connected in series, parallel, or series-parallel with other electronic components; this application does not specifically limit this. It can be understood that the first resistor unit R1 and the second resistor unit R2 are essentially the same, meaning that, without considering hardware errors, the resistance values ​​of the first resistor unit R1 and the second resistor unit R2 are the same.

[0128] The input terminal of the adjustment unit 221 can be connected to the connection point between the first resistor unit R1 and the second resistor unit R2 to receive the input common-mode voltage.

[0129] Furthermore, combined Figure 8 and Figure 9As shown, the adjustment unit 221 may include an operational amplifier U1, a current source CS, and a third resistor unit R3. The non-inverting input of the operational amplifier U1 is connected to the acquisition unit 220 to receive the input common-mode voltage. The inverting input of the operational amplifier U1 is connected to the output of the operational amplifier U1. The output of the operational amplifier U1 is connected to the first terminal of the third resistor unit R3, and the second terminal of the third resistor unit R3 is connected to the current source CS. The voltage difference across the third resistor unit R3 is the reference differential threshold, which is the voltage difference (ΔI*R) formed by the output current of the current source CS passing through the third resistor unit R3. The current value of the current source CS and / or the resistance value of the third resistor unit R3 are adjustable. Therefore, the reference differential threshold can be set by adjusting the output current of the current source CS and / or the resistance value of the third resistor unit R3. This allows the reference differential threshold to be adjusted according to actual application requirements, that is, the threshold voltage value of the expected input differential voltage VID (e.g., 25mV, 50mV, 100mV, 150mV, 200mV) to be set according to actual requirements.

[0130] The second end of the third resistor unit R3 is also connected to the output end of the adjustment unit 221. The voltage at the second end of the third resistor unit R3 is related to the sum of the input common-mode voltage and the reference differential threshold, which is the reference peak voltage. This allows the second input end of the comparison module 23 to receive the reference peak voltage. In other words, in this example, the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold. Since the input peak voltage is related to half of the input common-mode voltage and the input differential voltage, by appropriately setting the reference differential threshold, comparing the magnitudes of the input peak voltage and the reference peak voltage is equivalent to comparing half of the input differential voltage (VID / 2) and the reference differential threshold (ΔI*R). Therefore, based on the level state of the first comparison signal, it is also possible to determine whether the magnitude of the input differential voltage meets the requirements, and further determine whether there is an abnormality in the differential signal.

[0131] When operational amplifier U1 is operating, its non-inverting and inverting inputs are virtually short-circuited, and the inverting input is connected to its output. Therefore, the voltages at its non-inverting, inverting, and output terminals are all input common-mode voltages. Since the output current (ΔI) of the current source CS flows through the third resistor unit R3 and the output of operational amplifier U1, the reference peak voltage output from adjustment unit 221 to the second input terminal of comparison module 23 is related to VCM + ΔI*R, while the input peak voltage received by the first input terminal of comparison module 23 is related to VCM + VID / 2. Therefore, the difference between the input peak voltage received by comparison module 23 and the reference peak voltage is only related to ΔI*R and VID / 2, thus enabling the comparison of the input differential voltage and the reference differential threshold. Here, VID / 2 is half of the input differential voltage, and ΔI*R is the reference differential threshold.

[0132] Please continue reading. Figure 8 The amplitude detection module 21 may include a first diode D1, a second diode D2, and an RC parallel unit 210. The first diode D1 and the second diode D2 have substantially the same forward voltage. The anode of the first diode D1 is connected to the first receiving terminal, and the anode of the second diode D2 is connected to the second receiving terminal to receive differential signals. The cathodes of the first diode D1 and the second diode D2 are connected together and then connected to the first input terminal of the comparator module 23 to output the input peak voltage to the first input terminal of the comparator module 23. One end of the RC parallel unit 210 is connected to the first input terminal of the comparator module 23, and the other end of the RC parallel unit 210 is grounded.

[0133] Combination Figure 1 , Figure 8 and Figure 9 As shown, the transmitter generates a current in the corresponding direction based on the data. This current flows through the terminating resistor Rt between the first and second receivers, creating a voltage difference. This difference results in different voltage signals at the first and second receivers, causing the first diode D1 and the second diode D2 to either conduct or be cut off accordingly. When the voltage at the first receiver is greater than the voltage at the second receiver, the first diode D1 conducts, and the second diode D2 is cut off. When the voltage at the first receiver is less than the voltage at the second receiver, the first diode D1 is cut off, and the second diode D2 conducts. As the direction of the current generated by the transmitter alternates, the voltage difference between the first and second receivers also alternates (e.g., ...). Figure 2 (As shown).

[0134] At this time, the peak input voltage received by the first input terminal of the comparison module 23 is the sum of half of the input common-mode voltage and the input differential voltage minus the conduction voltage of the first diode D1 or the second diode D2, that is, VCM+VID / 2-Vd, where Vd is the conduction voltage of the first diode D1 and the second diode D2.

[0135] In some embodiments, to ensure the accuracy of the comparison module 23's comparison judgment between the input peak voltage and the reference peak voltage, such as... Figure 10 As shown, the adjustment unit 221 may also include a third diode D3, and the third diode D3 has substantially the same forward voltage Vd as the first diode D1 and the second diode D2. The second terminal of the third resistor unit R3 and the current source CS are connected to the output terminal of the adjustment unit 221 through the third diode D3, so that the reference peak voltage received by the comparison module 23 is the sum of the input common-mode voltage and the reference differential threshold voltage minus the forward voltage, i.e., VCM + ΔI*R - Vd.

[0136] As clearly seen above, the only differences between the peak input voltage (VCM + VID / 2 - Vd) at the first input terminal of the comparison module 23 and the reference peak voltage (VCM + ΔI*R - Vd) at the second input terminal are VID / 2 and ΔI*R. Therefore, it can compare the magnitude of the input differential voltage and the reference differential threshold, i.e., determine whether the input differential voltage is large enough. For example, when it is necessary to determine whether the input differential voltage VID of the differential signal meets the design requirement of 25mV, the reference differential threshold ΔI*R can be set to 12.5mV to determine whether the input differential voltage meets the design requirement. Of course, the specific value of the reference differential threshold ΔI*R is not limited to this and can be set according to the actual design requirements of the differential signal.

[0137] Of course, it is understood that the adjustment unit 221 may not include the third diode D3. In this case, the reference differential threshold can be set to be related to the forward voltage of the first diode D1 and the second diode D2. For example, the reference differential threshold can be made to be the threshold voltage of the expected differential voltage minus the forward voltage of the first diode D1 or the second diode D2 by directly adjusting the resistance value of the current source CS and / or the third resistor unit R3, thereby eliminating the influence of the forward voltage. Of course, in this application, the first diode D1 and the second diode D2 in the reference peak voltage acquisition module 22 and D3 in the adjustment unit 221 can also be replaced by other rectifier circuits, and are not limited to the diodes in the embodiments of this application.

[0138] In some specific examples, combined Figure 8 and Figure 10As shown, the comparison module 23 may include a first comparator U2, the first input terminal of which is connected to the connection point between the cathode of the first diode D1 and the cathode of the second diode D2 (this connection point is...). Figure 8 The first node P1 is shown to receive the input peak voltage. The second input terminal of the first comparator U2 is connected to the cathode of the third diode D3 (the connection point between the second terminal of the first comparator U2 and the third diode D3 is...). Figure 8 The second node P2 shown is used to receive the reference peak voltage. The first comparator U2 is used to determine whether the input peak voltage is greater than or equal to the reference peak voltage, thereby determining whether the input differential voltage is greater than or equal to the reference differential threshold.

[0139] Of course, the amplitude detection module 21 and the comparison module 23 are not limited to the specific examples described above. In some embodiments, such as Figure 11 As shown, the amplitude detection module 21 may include a first diode D1, a second diode D2 and two RC parallel units 210, and the comparison module 23 may include a second comparator U3, a third comparator U4 and a judgment unit U5. Figure 11 Specific examples relative to Figure 8 The main difference lies in the number and structure of the comparator and the RC parallel unit 210.

[0140] The first diode D1 and the second diode D2 have essentially the same forward voltage. The anode of the first diode D1 is connected to the first receiving terminal, and the cathode of the first diode D1 is connected to the first input terminal of the second comparator U3 and one end of one of the RC parallel units 210, the other end of which is grounded. The second input terminal of the second comparator U3 is connected to the reference peak voltage acquisition module 22 to receive the reference peak voltage. The second comparator U3 is used to compare whether the peak voltage of the first receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal based on the judgment result.

[0141] The anode of the second diode D2 is connected to the second receiving terminal, and the cathode of the second diode D2 is connected to the first input terminal of the third comparator U4 and one end of another RC parallel unit 210, the other end of which is grounded. The second input terminal of the third comparator U4 is also connected to the reference peak voltage acquisition module 22 to receive the reference peak voltage. The third comparator U4 is used to determine whether the peak voltage of the second receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal based on the determination result.

[0142] The outputs of the second comparator U3 and the third comparator U4 are connected to the first input and the second input of the judgment unit U5, respectively. The judgment unit U5 outputs the first comparison signal according to the output signals of the second comparator U3 and the third comparator U4.

[0143] Specifically, the judgment unit U5 can be configured as an AND gate, where the voltage difference between the first and second receiving terminals changes alternately (e.g., ...). Figure 2 As shown, the RC parallel unit 210 ensures that the peak voltages received at the first input terminals of the second comparator U3 and the third comparator U4 are in a stable and effective state. The capacitor C in the RC parallel unit 210 charges when there is a voltage signal at the first and second receiving terminals, enabling the first input terminals of the second comparator U3 and the third comparator U4 to receive the peak voltage. The resistor R resets the first input terminals of the second comparator U3 and the third comparator U4 when there is no voltage signal at the first and second receiving terminals.

[0144] When the differential signal is normal, the judgment results of the second comparator U3 and the third comparator U4 are both that the peak voltage is greater than or equal to the reference peak voltage. The state of the output judgment signal indicates that the peak voltage is greater than or equal to the reference peak voltage (e.g., the judgment signal is low level 0). Therefore, the first comparison signal output by the judgment unit U5 based on the state of the judgment signal is also a level state indicating that the differential signal is normal (e.g., the first comparison signal is low level 0). When the differential signal is abnormal, the judgment results of the second comparator U3 and the third comparator U4 are both that the peak voltage is less than the reference peak voltage. The state of the output judgment signal indicates that the peak voltage is less than the reference peak voltage (e.g., the judgment signal is high level 1). Therefore, the first comparison signal output by the judgment unit U5 based on the judgment signal is also a level state indicating that the differential signal is abnormal (e.g., the first comparison signal is high level 1).

[0145] Combination Figures 6 to 8 and Figure 11 As shown, the common-mode voltage detection circuit 30 is connected to the reference peak voltage acquisition module 22 to receive the input common-mode voltage, compare the input common-mode voltage with the reference common-mode voltage, and output a second comparison signal based on the comparison result. It can be understood that the reference common-mode voltage is set according to actual needs and is a reference value or expected value of the common-mode voltage of the differential signal comparator 10. The reference common-mode voltage can be provided to the common-mode voltage detection circuit 30 by an external power supply, circuit, control chip, etc.

[0146] The common-mode voltage detection circuit 30 is connected to the acquisition unit 220 of the reference peak voltage acquisition module 22 to receive the input common-mode voltage acquired by the acquisition unit 220.

[0147] Specifically, the common-mode voltage detection circuit 30 may include a fourth comparator U6. The first input terminal of the fourth comparator U6 is used to receive a reference common-mode voltage VREF, and the second input terminal of the fourth comparator U6 is connected to the acquisition unit 220 to receive the input common-mode voltage. The fourth comparator U6 is used to compare the magnitude of the reference common-mode voltage and the input common-mode voltage, and outputs a second comparison signal based on the comparison result. For example, when the input common-mode voltage is greater than or equal to the reference common-mode voltage, the second comparison signal output by the fourth comparator U6 is 1; when the input common-mode voltage is less than the reference common-mode voltage, the second comparison signal output by the fourth comparator U6 is 0, and vice versa (depending on the actual circuit). The reference common-mode voltage VREF can be set according to actual needs, and can also be provided to the first input terminal of the fourth comparator U6 by other voltage generation circuits. The reference common-mode voltage VREF is a reference value or expected value of the common-mode voltage of the differential signal, for example, it can be set to 0.3V, 0.4V, 0.5V, etc.

[0148] More specifically, the second input terminal of the fourth comparator U6 is connected to the junction between the first resistor unit R1 and the second resistor unit R2 to receive the input common-mode voltage. To improve the accuracy of the common-mode voltage detection circuit 30, one end of the fourth resistor unit R4 can also be connected to the second input terminal of the fourth comparator U6, and the other end of the fourth resistor unit R4 is grounded. When the differential signal is open or floating, the fourth resistor unit R4 pulls the second input terminal of the fourth comparator U6 down to ground, ensuring that the input common-mode voltage is less than the reference common-mode voltage when the differential signal is open or floating, thus improving the accuracy of the common-mode voltage detection circuit.

[0149] In some embodiments, the common-mode voltage detection circuit 30 may include two comparators. The first input of the first comparator receives a first reference value. The second input of the first comparator is connected to the first input of the second comparator and then connected between the first resistor unit R1 and the second resistor unit R2. The second input of the second comparator receives a second reference value. The first reference value is less than the second reference value, thus enabling the determination of whether the input common-mode voltage falls within the range between the first and second reference values ​​based on the comparison signals output by the two comparators. For example, the first reference value can be 0.3V, and the second reference value can be 0.5V, thereby enabling the determination of whether the input common-mode voltage falls between 0.3V and 0.5V.

[0150] The judgment circuit 40 is connected to the output terminals of the comparison module 23 and the common-mode voltage detection circuit 30 to receive the first comparison signal and the second comparison signal, respectively. The judgment circuit 40 is used to determine whether the differential signal is abnormal based on the first comparison signal and the second comparison signal, and outputs an indication signal to characterize whether the differential signal is abnormal.

[0151] like Figure 8and Figure 11 As shown, the judgment circuit 40 may include an inverter and an AND gate. The first input of the AND gate is connected to the output of the comparison module 23 through the inverter, and the second input of the AND gate is connected to the output of the common-mode voltage detection circuit 30. The AND gate outputs an indication signal based on the first comparison signal and the second comparison signal. Of course, the specific circuit form of the judgment circuit 40 in this application is not limited to this; it may also include only an AND gate, or be configured as an OR gate, comparator, etc.

[0152] The judgment circuit 40, by combining the first comparison signal and the second comparison signal, can more accurately identify whether there is an anomaly in the differential signal.

[0153] To better illustrate the principle of differential signal receiving circuit 1 in this application for detecting differential signal anomalies, Table 1 below shows... Figure 8 The differential signal receiving circuit 1 in the circuit receives differential signals at the first differential input terminal and the second differential input terminal under various conditions. The truth table for the first comparison signal of the differential signal amplitude detection circuit 20, the second comparison signal of the common-mode voltage detection circuit 30, and the indication signal of the judgment circuit 40 is as follows:

[0154] Table 1

[0155]

[0156]

[0157] In Table 1, low common-mode voltage refers to a situation where the input differential voltage of the differential signal is greater than the reference differential threshold, but the input common-mode voltage is less than the reference common-mode voltage; that is, the overall voltage of the differential signal decreases. Furthermore, the input of the differential signal comparator 10 also has a dead zone, which means that the differential signal does not exhibit periodic high or low level changes, such as remaining at a high or low level for an extended period.

[0158] Combined with Table 1, Figure 8 and Figure 10When the first and second differential input terminals are open-circuited or floating, meaning the differential signal is in an open-circuit or floating state, neither the first nor second receiving terminal of the differential signal amplitude detection circuit 20 receives a voltage signal. The RC parallel unit 210 pulls the first input terminal of the first comparator U2 low. The reference peak voltage received by the second input terminal of the first comparator U2 is ΔI*R-Vd. The voltage at the second input terminal of the first comparator U2 is greater than the voltage at the first input terminal, meaning the reference differential threshold ΔI*R is greater than half of the input differential voltage VID / 2. Therefore, the first comparator U2 outputs a high-level first comparison signal (state 1). The second input terminal of the fourth comparator U6 is pulled low by the fourth resistor unit R4, meaning the input common-mode voltage VCM detected by the fourth comparator U6 is low. The fourth comparator U6 determines that the input common-mode voltage VCM received by its second input terminal is less than the reference common-mode voltage VREF received by its first input terminal. Therefore, the fourth comparator U6 outputs a low-level second comparison signal (state 0). The first comparison signal becomes 0 after being inverted by the inverter. The AND gate in the judgment circuit 40 outputs a low-level indicator signal of 0 based on the inverted first and second comparison signals, indicating that the differential signal is abnormal.

[0159] When the first differential input terminal and the second differential input terminal are short-circuited, that is, the differential signal is in a short-circuit state, the voltages of the first receiving terminal and the second receiving terminal of the differential signal amplitude detection circuit 20 are the same (e.g., Vi). The voltage received at the first input terminal of the first comparator U2 is Vi-Vd, and the voltage received at its second input terminal is Vi+(ΔI*R-Vd). Therefore, the voltage at the second input terminal of the first comparator U2 is greater than the voltage at the first input terminal, which means that the reference differential threshold ΔI*R is greater than half of the input differential voltage VID / 2. Thus, the first comparison signal output by the first comparator U2 is a high level (1). The voltage received at the second input terminal of the fourth comparator U6 is Vi, which is greater than the reference common-mode voltage VREF received at its first input terminal. The second comparison result is that the input common-mode voltage is greater than the reference common-mode voltage. Therefore, the second comparison signal output by the fourth comparator U6 is also a high level (1). The first comparison signal becomes 0 after being inverted by the inverter. The AND gate in the judgment circuit 40 outputs a low-level indicator signal of 0 based on the inverted first and second comparison signals, indicating that the differential signal is abnormal.

[0160] When the common-mode voltage of the differential signal is low, the voltage received at the second input of the first comparator U2 is less than the voltage received at its first input. This means the reference differential threshold ΔI*R is less than half the input differential voltage, VID / 2. Therefore, the first comparator U2 outputs a low-level comparison signal (0). The second input of the fourth comparator U6 detects that the input common-mode voltage VCM is less than the reference common-mode voltage VREF. Consequently, the fourth comparator U6 also outputs a low-level comparison signal (0). The first comparison signal, after being inverted, becomes 1. The AND gate in the judgment circuit 40 outputs a low-level indicator signal (0) based on the inverted first and second comparison signals, indicating an abnormal differential signal.

[0161] When the differential signal is in the dead zone, the levels of the first and second differential input terminals remain unchanged for a long time. For example, the level of the second differential input terminal is lower than the level of the first differential input terminal for a long time. The peak input voltage received at the first input terminal of the first comparator U2 is greater than the reference peak voltage received at its second input terminal, and the first comparator U2 outputs a low-level first comparison signal (0). The common-mode voltage VCM received at the second input terminal of the fourth comparator U6 is greater than or equal to the reference common-mode voltage VREF at its first input terminal, and the second comparison signal output by the fourth comparator U6 is a high-level signal (1). The first comparison signal is inverted to 1. The AND gate in the judgment circuit 40 outputs a high-level indicator signal (1) based on the inverted first and second comparison signals, indicating that the differential signal is normal.

[0162] When the first and second differential input terminals are in normal condition and the received differential signal is also normal, although the levels of the first and second differential input terminals will periodically alternate, since the second input terminal of the fourth comparator U6 receives the differential signal through the series-connected first resistor unit R1 and second resistor unit R2, the voltage at the connection point of the first resistor unit R1 and second resistor unit R2 is the input common-mode voltage VCM and will not be affected by the periodic alternation of the levels of the first and second differential input terminals. The second comparison signal output by the fourth comparator U6 is a high-level state 1. Since the differential signal amplitude detection circuit 20 receives the differential signal through the first diode D1 and second diode D2, and outputs the input peak voltage through the connection point of the first diode D1 and second diode D2, the first comparison signal output by the first comparator U2 is a low-level state 0. Therefore, the AND gate in the judgment circuit 40 can still output an indication signal of a high-level state 1 based on the inverted first and second comparison signals, indicating that the differential signal is normal.

[0163] certainly, Figure 11 The principle of the specific example of the differential signal receiving circuit 1 shown is... Figure 8 Similarly, this will not be elaborated upon here.

[0164] Based on the above, the differential signal receiving circuit 1 in this application can detect not only three abnormal conditions of the differential signal—open circuit, floating, and short circuit—but also when the common-mode voltage of the received differential signal is low, and issue an indication signal indicating the abnormality. However, when the differential signal is in a signal dead zone, the differential signal receiving circuit 1 will not output an indication signal indicating the abnormality, thereby preventing misjudgment of the differential signal's state.

[0165] Please continue reading. Figure 8 The differential signal receiving circuit 1 may further include a data preservation circuit 50, which is connected to the output of the differential signal comparator 10 and the output of the judgment circuit 40. The data preservation circuit 50 outputs a data preservation signal based on the data signal output by the differential signal comparator 10 and the indication signal output by the judgment circuit 40. When the indication signal indicates that the differential signal is normal, the data preservation circuit 50 outputs a data signal as the data preservation signal. When the indication signal indicates that the differential signal is abnormal, the data preservation circuit 50 keeps the data preservation signal in the same state.

[0166] By setting up the data preservation circuit 50, when the differential signal is normal, the differential signal receiving circuit 1 allows the data signal from the differential signal comparator 10 to be output as a data preservation signal to the subsequent circuit, which has the same effect as directly connecting the output of the differential signal comparator 10 to the subsequent circuit. When the differential signal is abnormal, the data preservation signal output by the differential signal receiving circuit 1 remains at the same level, and the subsequent circuit can detect the differential signal abnormality based on the data preservation signal. Based on this, when the differential signal is normal, the subsequent circuit can receive the data signal as a data preservation signal and work normally; when the differential signal is abnormal, the subsequent circuit can detect the differential signal abnormality based on the data preservation signal that remains at the same level, thereby reacting quickly and executing corresponding actions to prevent the subsequent circuit from continuing to transmit the signal, which could lead to damage or malfunction of the subsequent circuit.

[0167] In some specific examples, the data preservation circuit 50 may include an AND gate. The first input of the AND gate is connected to the output of the judgment circuit 40 to receive an indication signal, and the second input of the AND gate is connected to the output of the differential signal comparator 10 to receive a data signal. When the indication signal is high (state 1), it indicates that the differential signal is normal, and the data preservation signal output by the AND gate is the same as the data signal, equivalent to outputting a normal data signal. When the indication signal is low (state 0), it indicates that the differential signal is abnormal, and regardless of how the data signal changes, the data preservation signal output by the AND gate remains low (state 0). Of course, the specific circuit structure of the data preservation circuit 50 in this application is not limited to this.

[0168] like Figure 12As shown, this application embodiment also provides a method for detecting the amplitude of a differential signal. In one or more specific examples, the method for detecting the amplitude of a differential signal can be based on the differential signal amplitude detection circuit 20 described above.

[0169] The amplitude detection method for differential signals in this application embodiment may include the following steps:

[0170] S 10, Receive differential signal.

[0171] S20. Obtain the input common-mode voltage and input peak voltage of the differential signal. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal.

[0172] S30. Obtain the reference peak voltage of the differential signal. The reference peak voltage is related to the sum of the input common-mode voltage of the differential signal and the reference differential threshold.

[0173] The reference peak voltage is obtained by receiving the differential signal.

[0174] S40. Compare the input peak voltage with the reference peak voltage, and output the first comparison signal based on the comparison result.

[0175] Specifically, when the differential signal is normal, the input differential voltage will be greater than or equal to the reference differential threshold, resulting in an input peak voltage greater than or equal to the reference peak voltage. When the differential signal is in an abnormal state such as open circuit, floating, or short circuit, the input differential voltage will be less than the reference differential threshold, resulting in an input peak voltage less than the reference peak voltage. Therefore, the presence of an abnormality in the differential signal can be determined by comparing the magnitudes of the input peak voltage and the reference peak voltage.

[0176] Please see Figure 13 To obtain the reference peak voltage of the differential signal, step S30 may include:

[0177] S31. Preset reference difference threshold.

[0178] S32. Generate a reference peak voltage based on the reference differential threshold and the input common-mode voltage, such that the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold.

[0179] The reference differential threshold can be adjusted and set according to the differential voltage value required for the differential signal to operate normally, thus enabling this application to adapt to abnormal state detection of differential signals with different parameter requirements. This is combined with the aforementioned differential signal amplitude detection circuit 20. Figures 8 to 10The explanation is as follows: The first input terminal of the second comparator U2 is connected to the junction between the cathodes of the first diode D1 and the second diode D2 to receive the input peak voltage; the second input terminal of the second comparator U2 is connected to the cathode of the third diode D3 to receive the reference peak voltage; wherein, the voltage received at the first input terminal of the second comparator U2, after passing through the first diode D1 or the second diode D2, should be the input peak voltage minus the forward voltage drop (VCM + VID / 2 - Vd); and after adjustment by the differential operational amplifier U1, current source CS and third resistor unit R3 in the adjustment unit 221, the voltage at the anode of the third diode D3 is adjusted to be the actual reference peak voltage VCM + ΔI*R. After passing through the third diode D3, the voltage received at the second input terminal of the second comparator U2 should be the actual reference peak voltage minus the forward voltage drop (VCM + ΔI*R - Vd), thereby eliminating the influence of the forward voltage drops of the first diode D1 and the second diode D2. Of course, it is understandable that... Figure 9 As shown, the third diode D3 can be omitted in the adjustment unit 221 to eliminate the influence of the forward voltage drop, and the voltage output to the second input terminal of the second comparator U2 can be directly adjusted by the adjustment unit 221 to eliminate the forward voltage drop; or the influence of the forward voltage drop can be eliminated by other rectifier circuits, or the first diode D1 and the second diode D2 can be omitted to prevent the input peak voltage received at the first input terminal of the second comparator U2 from needing to be subtracted from the forward voltage drop.

[0180] The specific implementation of the differential signal amplitude detection method in this application embodiment is detailed in the aforementioned differential signal amplitude detection circuit, and will not be repeated here.

[0181] like Figure 14 As shown, this application embodiment also provides a method for data preservation of differential signals. In one or more specific examples, the method for data preservation of differential signals of this application can be based on the differential signal receiving circuit 1 described above.

[0182] The data preservation method for differential signals in this application includes:

[0183] S 10, Receive differential signal.

[0184] S20. Obtain the input common-mode voltage and input peak voltage of the differential signal. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal.

[0185] S30. Obtain the reference peak voltage of the differential signal. The reference peak voltage is related to the sum of the input common-mode voltage of the differential signal and the reference differential threshold.

[0186] S40. Compare the input peak voltage with the reference peak voltage, and output the first comparison signal based on the comparison result.

[0187] S50. Compare the input common-mode voltage with the reference common-mode voltage, and output a second comparison signal based on the comparison result.

[0188] The reference common-mode voltage can be provided by an external power supply, circuit, control chip, etc.

[0189] S60. Determine whether the differential signal is abnormal based on the first comparison signal and the second comparison signal, and generate an indication signal to characterize whether the differential signal is abnormal.

[0190] S70. Generate the corresponding data signal based on the differential signal.

[0191] S80. Output a data preservation signal based on the data signal and the indication signal. When the indication signal indicates that the differential signal is normal, output the data signal as the data preservation signal. When the indication signal indicates that the differential signal is abnormal, keep the data preservation signal at the same level.

[0192] Steps S10 to S40 are the same as the aforementioned differential signal amplitude detection method, and their specific implementation is also the same as the aforementioned differential signal amplitude detection method.

[0193] In the differential signal data preservation method of this application embodiment, the input differential voltage and the reference differential threshold are compared by comparing the input peak voltage and the reference peak voltage. A first comparison signal is output based on the comparison result, and a second comparison signal is output based on the input common-mode voltage and the reference common-mode voltage. The first comparison signal and the second comparison signal are combined to generate an indication signal for characterizing whether the differential signal is abnormal. That is, the differential signal is judged to be abnormal by combining whether the input differential voltage and the input common-mode voltage meet the performance requirements of the differential signal.

[0194] Specifically, when the differential signal is normal, the input differential voltage will be greater than or equal to the reference differential threshold, and the input common-mode voltage will also be greater than or equal to the reference common-mode voltage. However, when the differential signal is abnormal, the input differential voltage will be less than the reference differential threshold, or the input common-mode voltage will be less than the reference common-mode voltage. Therefore, it is possible to determine whether the differential signal is abnormal based on the input differential voltage and the input common-mode voltage, thereby improving the accuracy of detecting whether the differential signal is abnormal.

[0195] Furthermore, when the differential signal is normal, the output data signal serves as a data preservation signal to the subsequent circuits, ensuring their normal operation. When the differential signal is abnormal, the data preservation signal remains in the same state, allowing subsequent circuits to detect the differential signal abnormality based on the data preservation signal.

[0196] The specific implementation of the differential signal data preservation method in this application embodiment is detailed in the aforementioned differential signal receiving circuit 1, and will not be repeated here.

[0197] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps may be performed in other orders or simultaneously.

[0198] In the embodiments provided in this application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0199] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0200] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Additionally, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. Note that the above are only preferred embodiments of this application and the technical principles used.

[0201] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A differential signal amplitude detection circuit for detecting the amplitude of a differential signal, characterized in that, The differential signal amplitude detection circuit includes: A first receiving end and a second receiving end, wherein the first receiving end and the second receiving end are used to receive the differential signal; An amplitude detection module is connected to the first receiving end and the second receiving end to obtain the input peak voltage of the differential signal. The input peak voltage is related to the sum of the input common-mode voltage and half of the input differential voltage of the differential signal. A reference peak voltage acquisition module, connected to the first receiving end and the second receiving end, acquires the input common-mode voltage of the differential signal, and acquires a reference peak voltage of the differential signal based on the input common-mode voltage. The reference peak voltage is related to the sum of the input common-mode voltage and a reference differential threshold of the differential signal. The comparison module has a first input terminal connected to the output terminal of the amplitude detection module to receive the input peak voltage; and a second input terminal connected to the output terminal of the reference peak voltage acquisition module to receive the reference peak voltage. The comparison module is used to compare the input peak voltage with the reference peak voltage and output a first comparison signal based on the comparison result.

2. The differential signal amplitude detection circuit as described in claim 1, characterized in that, The reference peak voltage acquisition module includes: An acquisition unit is connected to the first receiving end and the second receiving end to receive the differential signal and acquire the input common-mode voltage based on the differential signal. An adjustment unit is provided, the input terminal of which is connected to the acquisition unit to receive the input common-mode voltage, and the output terminal of which is connected to the second input terminal of the comparison module; the adjustment unit is used to adjust and obtain the reference peak voltage according to the input common-mode voltage and the reference differential threshold, and then output the reference peak voltage.

3. The differential signal amplitude detection circuit as described in claim 2, characterized in that, The acquisition unit includes a first resistor unit and a second resistor unit. The resistance values ​​of the first resistor unit and the second resistor unit are substantially the same. The first resistor unit and the second resistor unit are connected in series and then connected between the first receiving end and the second receiving end to receive the differential signal. The voltage at the connection point between the first resistor unit and the second resistor unit is the input common-mode voltage. as well as The input terminal of the adjustment unit is connected to the connection point between the first resistor unit and the second resistor unit to receive the input common-mode voltage.

4. The differential signal amplitude detection circuit as described in claim 2, characterized in that, The adjustment unit includes an operational amplifier, a current source, and a third resistor unit; The non-inverting input of the operational amplifier is connected to the acquisition unit to receive the input common-mode voltage. The inverting input of the operational amplifier is connected to the output of the operational amplifier. The output of the operational amplifier is connected to the first terminal of the third resistor unit. The second terminal of the third resistor unit is connected to the output of the current source and the adjustment unit to output the reference peak voltage to the second input of the comparison module. Wherein, the voltage difference across the third resistor unit is the reference differential threshold; the adjustment unit sets the reference differential threshold by adjusting the output current of the current source and / or the resistance value of the third resistor unit, and the voltage at the connection point between the current source and the third resistor unit is the sum of the input common-mode voltage and the reference differential threshold.

5. The differential signal amplitude detection circuit as described in claim 4, characterized in that, The amplitude detection module includes a first diode, a second diode, and an RC parallel unit; The first diode and the second diode have substantially the same forward voltage; the anode of the first diode is connected to the first receiving terminal, and the anode of the second diode is connected to the second receiving terminal, so as to receive the differential signal; The cathode of the first diode is connected together with the cathode of the second diode and connected to the first input terminal of the comparator module to output the input peak voltage to the first input terminal of the comparator module; One end of the RC parallel unit is connected to the first input terminal of the comparator module, and the other end of the RC parallel unit is grounded.

6. The differential signal amplitude detection circuit as described in claim 5, characterized in that, The adjustment unit further includes a third diode, and the second end of the third resistor unit and the current source are connected to the output end of the adjustment unit through the third diode; The forward voltage of the third diode is substantially the same as that of the first diode and the second diode, and the voltage at the output of the adjustment unit is the sum of the input common-mode voltage and the reference differential threshold minus the forward voltage.

7. The differential signal amplitude detection circuit as described in claim 6, characterized in that, The comparison module includes a first comparator, the first input terminal of which is connected to the cathode of the first diode and the cathode of the second diode to receive the input peak voltage; The second input terminal of the first comparator is connected to the cathode of the third diode to receive the reference peak voltage; Wherein, the input peak voltage is equal to the sum of the input common-mode voltage and half of the input differential voltage minus the turn-on voltage, and the reference peak voltage is equal to the sum of the input common-mode voltage and the reference differential threshold minus the turn-on voltage. The first comparator determines whether half of the input differential voltage is greater than or equal to the reference differential threshold by determining whether the input peak voltage is greater than or equal to the reference peak voltage.

8. The differential signal amplitude detection circuit as described in claim 4, characterized in that, The amplitude detection module includes a first diode, a second diode, and two RC parallel units; the comparison module includes a second comparator, a third comparator, and a judgment unit. The first diode and the second diode have essentially the same forward voltage. The anode of the first diode is connected to the first receiving terminal, and the cathode of the first diode is connected to the first input terminal of the second comparator and one end of one of the RC parallel units. The other end of the RC parallel unit is grounded. The second input terminal of the second comparator is connected to the reference peak voltage acquisition module. The second comparator is used to determine whether the peak voltage of the first receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal according to the determination result. The anode of the second diode is connected to the second receiving terminal, and the cathode of the second diode is connected to the first input terminal of the third comparator and one end of another RC parallel unit, the other end of which is grounded; the second input terminal of the third comparator is connected to the reference peak voltage acquisition module, and the third comparator is used to determine whether the peak voltage of the second receiving terminal is greater than or equal to the reference peak voltage, and outputs a signal according to the determination result; The first input terminal of the judgment unit is connected to the output terminal of the second comparator, and the second input terminal of the judgment unit is connected to the output terminal of the third comparator. The judgment unit is used to output the first comparison signal based on the output signals of the second comparator and the third comparator.

9. A differential signal receiving circuit, characterized in that, It includes a first differential input terminal, a second differential input terminal, a differential signal comparator, a common-mode voltage detection circuit, a judgment circuit, and a differential signal amplitude detection circuit as described in any one of claims 1 to 8; The first differential input terminal and the second differential input terminal are used to receive differential signals; The first input terminal and the second input terminal of the differential signal comparator are respectively connected to the first differential input terminal and the second differential input terminal to receive the differential signal. The differential signal comparator is used to generate a corresponding data signal based on the differential signal. The first receiving end and the second receiving end of the differential signal amplitude detection circuit are respectively connected to the first differential input end and the second differential input end to receive the differential signal; The common-mode voltage detection circuit is connected to the reference peak voltage acquisition module of the differential signal amplitude detection circuit to receive the input common-mode voltage. The common-mode voltage detection circuit is used to compare the input common-mode voltage with the reference common-mode voltage and output a second comparison signal according to the comparison result. The judgment circuit is connected to the output terminal of the comparison module of the differential signal amplitude detection circuit and the output terminal of the common mode voltage detection circuit to receive the first comparison signal and the second comparison signal respectively. The judgment circuit is used to determine whether the differential signal is abnormal based on the first comparison signal and the second comparison signal, and outputs an indication signal to characterize whether the differential signal is abnormal.

10. The differential signal receiving circuit as described in claim 9, characterized in that, It also includes a data preservation circuit, which is connected to the output of the differential signal comparator and the output of the judgment circuit. The data preservation circuit is used to output a data preservation signal based on the data signal and the indication signal. When the indication signal indicates that the differential signal is normal, the data preservation circuit outputs the data signal as the data preservation signal. When the indication signal indicates that the differential signal is abnormal, the data preservation circuit keeps the data preservation signal in the same state.

11. A method for detecting the amplitude of a differential signal, characterized in that, include: Receive differential signals; The input common-mode voltage and input peak voltage of the differential signal are obtained based on the differential signal, and the input peak voltage is related to the sum of half of the input common-mode voltage and the input differential voltage of the differential signal; Obtain a reference peak voltage of the differential signal, the reference peak voltage being related to the sum of the input common-mode voltage and the reference differential threshold; The input peak voltage is compared with the reference peak voltage, and a first comparison signal is output based on the comparison result.

12. The amplitude detection method as described in claim 11, characterized in that, The step of obtaining the reference peak voltage of the differential signal includes: The reference difference threshold is preset; The reference peak voltage is generated based on the reference differential threshold and the input common-mode voltage, such that the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold.

13. A method for data preservation of differential signals, characterized in that, include: Receive differential signals; The input common-mode voltage and input peak voltage of the differential signal are obtained based on the differential signal, and the input peak voltage is related to the sum of half of the input common-mode voltage and the input differential voltage of the differential signal; Obtain a reference peak voltage of the differential signal, the reference peak voltage being related to the sum of the input common-mode voltage and the reference differential threshold; The input peak voltage is compared with the reference peak voltage, and a first comparison signal is output based on the comparison result; The input common-mode voltage is compared with the reference common-mode voltage, and a second comparison signal is output based on the comparison result; Based on the first comparison signal and the second comparison signal, determine whether the differential signal is abnormal, and generate an indication signal to characterize whether the differential signal is abnormal; The corresponding data signal is generated based on the differential signal; A data preservation signal is output based on the data signal and the indication signal; when the indication signal indicates that the differential signal is normal, the data signal is output as the data preservation signal; when the indication signal indicates that the differential signal is abnormal, the data preservation signal is kept in the same state.

14. The data preservation method as described in claim 13, characterized in that, The step of obtaining the reference peak voltage of the differential signal includes: The reference difference threshold is preset; The reference peak voltage is generated based on the reference differential threshold and the input common-mode voltage, such that the reference peak voltage is related to the sum of the input common-mode voltage and the reference differential threshold.

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