A wafer level test fixture

Abstract

A kind of jig for wafer level testing, comprising: main body part, the main body part includes: first surface, in the testing state, the first surface is towards the wafer under test;Wherein, the first surface is provided with contact part, the contact part is adapted to the cutting lane of the wafer under test.The wafer is tested using the jig provided in the application, which can reduce the damage to the wafer during testing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more particularly to a fixture for wafer-level testing. Background Technology

[0002] With the increasingly widespread application of semiconductor devices, their production volume is constantly increasing, and their size is becoming smaller and smaller. These developments present new challenges for semiconductor device testing. To address these challenges, wafer-level testing methods have emerged. Wafer-level testing refers to performing packaging testing at the wafer level to achieve mass production and testing.

[0003] In existing technologies, wafers are easily damaged during functional testing. Therefore, how to reduce wafer damage during wafer testing is the technical problem that this invention aims to solve. Summary of the Invention

[0004] The technical problem solved by this invention is how to reduce damage to wafers during wafer testing.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a fixture for wafer-level testing, comprising: a main body, the main body including: a first surface, wherein, in a testing state, the first surface faces the wafer under test; wherein, the first surface is provided with a contact portion, the contact portion being adapted to the dicing track of the wafer under test.

[0006] Optionally, the shape of the contact portion is adapted to the shape of the cutting channel, and in the test state, the contact portion is in contact with the cutting channel.

[0007] Optionally, the contact portion protrudes relative to the first surface.

[0008] Optionally, the first surface has a mounting hole for mounting a lens.

[0009] Optionally, the planar shape of the contact portion is closed.

[0010] Optionally, the number of mounting holes is multiple, and the multiple mounting holes are located within the closed shape.

[0011] Optionally, the contact portion is integrally formed, or the contact portion includes multiple contact elements arranged in an array.

[0012] Optionally, each contact has a straight planar shape, and the width of the contact is less than or equal to the width of the dicing of the wafer being measured.

[0013] Optionally, the number of mounting holes is multiple, and the multiple mounting holes are arranged in a straight line.

[0014] Optionally, along the arrangement direction of the plurality of mounting holes, the contact portions are provided on both sides of each mounting hole.

[0015] Optionally, perpendicular to the arrangement direction of the plurality of mounting holes, the contact portion is provided on both sides of each mounting hole.

[0016] Optionally, the fixture further includes a base, and the main body further includes a second surface opposite to the first surface, the second surface being fixed to the base.

[0017] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0018] In this embodiment of the invention, the fixture includes a main body, with a first surface facing the wafer under test in the testing state. The first surface has a contact portion that mates with the dicing grooves of the wafer under test. By providing a contact portion that mates with the dicing grooves, the contact portion only contacts the dicing grooves during testing. Compared to existing technologies where the contact portion contacts the functional areas of the wafer, the fixture provided by this invention reduces damage to the chips on the wafer during testing and effectively protects the wafer.

[0019] Furthermore, the first surface of the main body has multiple mounting holes for mounting lenses, and the planar shape of the contact part is closed, with the multiple mounting holes located within the closed shape. This helps to reduce light leakage during testing, thereby improving the accuracy of the test results.

[0020] Furthermore, the contact portion protrudes relative to the first surface, which ensures that only the contact portion contacts the wafer under test during the test state, avoiding contact between the main body and other components other than the contact portion and the wafer under test, further helping to reduce damage to the chip during wafer testing. Attached Figure Description

[0021] Figure 1 This is a three-dimensional schematic diagram of a fixture used for wafer-level testing in the prior art;

[0022] Figure 2 Is using Figure 1 A schematic diagram of a fixture testing a wafer;

[0023] Figure 3 This is a three-dimensional schematic diagram of a fixture for wafer-level testing in an embodiment of the present invention;

[0024] Figure 4 yes Figure 3 A top view of a fixture used for wafer-level testing;

[0025] Figure 5 Is using Figure 3 and Figure 4 The diagram shows a fixture used for wafer-level testing testing a wafer. Detailed Implementation

[0026] As described in the background section, there is an urgent need for a test fixture that can reduce damage to the wafer during wafer testing.

[0027] In the prior art, when testing wafers, the testing fixtures are prone to coming into contact with the functional areas of the wafer, which can lead to damage to the functional areas.

[0028] Taking complementary metal-oxide-semiconductor (CMOS) image sensor chips as an example, in order to improve production and testing efficiency, wafer-level packaging is usually adopted, and then the wafer is tested.

[0029] Reference Figure 1 and Figure 2 , Figure 1 This is a three-dimensional structural diagram of a fixture used for wafer-level testing in the prior art. Figure 2 Is using Figure 1 The diagram shows a fixture used for testing wafers.

[0030] like Figure 1 As shown, Figure 1 The fixture shown has a contact portion 10. For example... Figure 2 As shown, using Figure 1 When the fixture in the middle tests the wafer, the contact portion 10 overlaps with the contact position 11 on the wafer and the functional area 12 on the wafer. In other words, in the test state, using... Figure 1 When the fixture shown is tested, the contact part 10 will come into contact with multiple chips on the wafer. If there are foreign objects such as dust on the contact part 10, they may cause damage to the chips when they come into contact with the wafer, thus affecting the product quality.

[0031] To address this technical problem, embodiments of the present invention provide a fixture for wafer-level testing. In this embodiment, the fixture includes a main body, with a first surface facing the wafer under test in the testing state. The first surface has a contact portion that mates with a dicing track on the wafer. By providing a contact portion that mates with the dicing track, the contact portion only contacts the dicing track during testing. Compared to existing technologies where the contact portion contacts the functional areas of the wafer, the fixture provided by this invention reduces damage to the chips on the wafer during testing, effectively protecting the wafer.

[0032] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] Reference Figure 3 , Figure 4 and Figure 5 , Figure 3 This is a three-dimensional schematic diagram of a fixture for wafer-level testing provided in an embodiment of this application. Figure 4 yes Figure 3 A top view of a fixture used for wafer-level testing. Figure 5 Is using Figure 3 A schematic diagram of the fixture used for testing the wafer. The following is a combination of... Figure 3 , Figure 4 and Figure 5 A non-limiting description is provided of a fixture for wafer-level testing in an embodiment of this application.

[0034] In the embodiments of this application, the fixture 3 for wafer-level testing may include: a main body 31 and a base 32.

[0035] It should be noted that in some embodiments of this application, the fixture 3 may not include the base 32, and this application does not limit this.

[0036] Furthermore, the wafer 4 under test, tested using the fixture 3, may include a functional region 41 and a dicing track 42. The functional region 41 may include multiple chips. These multiple chips may be CMOS image sensor chips or other semiconductor chips (e.g., capacitive fingerprint sensor chips), and this embodiment does not impose any limitations on this.

[0037] Multiple chips can be arranged in an array, with dicing channels 42 between adjacent chips. It can be understood that dicing channels 42 are non-functional areas of the wafer under test 4. After testing, the wafer under test 4 can be diced along dicing channels 42 to obtain multiple packaged chips. In other words, dicing channels 42 refer to the diced areas on the wafer under test 4.

[0038] Furthermore, the main body 31 includes a first surface and a second surface facing each other, wherein, in the test state, the first surface faces the wafer 4 under test, and the second surface faces away from the wafer 4 under test.

[0039] More specifically, when the fixture 3 includes a base, the second surface can be fixed to the base 32.

[0040] The test state refers to the state in which the wafer 4 under test is tested using the fixture 3.

[0041] Furthermore, in the embodiment of this application, the first surface of the main body 31 is provided with a contact portion 310, which is adapted to the dicing groove 42 of the wafer 4 being tested.

[0042] Specifically, the shape of the contact portion 310 is adapted to the shape of the dicing track 42, and in the test state, the contact portion 310 is in contact with the dicing track 42 of the wafer 4 under test. For example... Figure 5 As shown, the contact position 43 between the contact portion 310 and the wafer 4 under test is located on the dicing channel 42.

[0043] More specifically, the fact that the shape of the contact portion 310 matches the shape of the dicing track 42 means that, in the test state, the contact portion 310 only contacts the dicing track 42 and does not contact other areas outside the dicing track 42 (e.g., the functional area 41 of the wafer 4 under test). In other words, in the test state, the projection of the contact portion 310 onto the plane of the wafer 4 under test is entirely within the area of ​​the dicing track 42.

[0044] In a non-limiting example, the contact portion 310 may be made of any of the following materials: plastic, rubber, silicone, but is not limited to these.

[0045] With this approach, even if there are foreign objects such as dust on the contact portion 310 during the test, since the contact portion 310 only contacts the dicing channel 42, the foreign objects on the contact portion 310 will not have an adverse effect on the functional area 41 of the wafer under test 4 (e.g., pressure marks).

[0046] Therefore, compared with the prior art, in the solution of this application embodiment, the contact portion 310 is adapted to the dicing channel 42 of the wafer 4 under test, which can avoid damage to the chip in the functional area 41 due to the contact between the fixture 3 and the functional area 41 during the test.

[0047] Furthermore, in the embodiment of this application, the contact portion 310 may protrude relative to the first surface. This ensures that, during testing, only the contact portion 310 contacts the wafer 4 under test, avoiding contact between other components of the main body 31 besides the contact portion 310 and the wafer 4 under test, further reducing damage to the chip during wafer testing.

[0048] Furthermore, the fixture 3 may also have a housing (not shown) adapted to the main body 31. In the non-testing state, the housing can be fixed to the base 32, and the main body 31 can be accommodated within the enclosed area formed by the housing and the base 32. Before testing, the housing can be separated from the base 32 to expose the main body 31. This design minimizes the accumulation of dust and other foreign matter on the main body 31 during the storage and movement of the fixture 3.

[0049] In one embodiment of this application, the chip in functional area 41 is an image sensor chip, for example, a CMOS image sensor. Correspondingly, the fixture 3 is a fixture for testing the image sensor chip (for example, a fixture for supporting a lens), which can be used to test the imaging and other performance characteristics of the image sensor chip.

[0050] Specifically, the first surface of the main body 31 may have a mounting hole 311, which can be used to mount a lens (not shown).

[0051] More specifically, in the test state, a lens is installed inside the mounting hole 311.

[0052] In a specific implementation, the inner surface of the mounting hole 311 has a thread, which can be used to screw into the thread on the outside of the lens, thereby fixing the lens in the mounting hole 311.

[0053] It should be noted that the number of mounting holes 311 on the main body 31 is not limited in this application embodiment. In the test state, each mounting hole 311 is provided with one lens, and each lens corresponds to an image sensor chip on the wafer 4 under test.

[0054] In the test state, the front side of the tested wafer 4 is the photosensitive side, and the back side is the non-photosensitive side.

[0055] Specifically, in the test state, the photosensitive surface of the wafer 4 under test faces the first surface of the main body 31. Since the mounting hole 311 is located on the first surface of the main body and a lens is provided in the mounting hole 311, the photosensitive surface can face the lens during the test to simulate the actual use scenario of the image sensor.

[0056] More specifically, the photosensitive surface may be covered with glass, and in the test state, the fixture 3 is placed on the glass. At this time, the contact portion 310 contacts the area of ​​the glass corresponding to the cutting path 42.

[0057] Furthermore, the planar shape of the contact portion 310 can be closed, with multiple mounting holes 311 located within the closed shape. The planar shape of the contact portion 310 can refer to the shape of its projection onto the plane of the wafer 4 being measured.

[0058] In other words, the shape of the projection of the contact portion 310 onto the plane of the wafer 4 being measured is a closed shape, and the projections of the multiple mounting holes 311 are all located within the shape of the contact portion's projection. For example... Figure 4 As shown, multiple mounting holes 311 are all located within the closed shape formed by the contact portion 310.

[0059] During testing, since multiple mounting holes 311 are all located within the closed shape formed by the contact portion 310, when the contact portion 310 contacts the dicing channel 42, a sealed space is formed between the contact portion 310 and the wafer under test 4, and the photosensitive surfaces of the lens and the corresponding image sensor chip are both located within this sealed space. This approach minimizes light leakage during testing, thus improving the accuracy of the test results.

[0060] In one embodiment of this application, the contact portion 310 may be integrally formed.

[0061] In another embodiment of this application, the contact portion 310 may also include multiple contact elements (not shown in the figures).

[0062] In a specific implementation, multiple contacts can be arranged in an array. Among them, multiple contacts can be connected end to end to form a contact portion 310, so that the planar shape of the contact portion 310 is a closed shape.

[0063] In other embodiments of this application, the multiple contacts may also be separate from each other, and this embodiment does not limit this.

[0064] In a specific example, the planar shape of the contact can be straight, that is, the projection of the contact onto the plane of the measured wafer 4 can be straight.

[0065] In another specific example, the planar shape of the contact can be circular, that is, the projection of the contact onto the plane of the measured wafer 4 can be circular.

[0066] Furthermore, the width of the contact element can be less than or equal to the width of the cutting groove 42.

[0067] For example, if the planar shape of the contact is linear, the width of the contact can refer to the dimension of the contact perpendicular to its extension direction. If the planar shape of the contact is circular, the width of the contact can refer to the diameter of the contact. Since the width of the contact is less than or equal to the width of the dicing track 42, and the width of the dicing track 42 is less than or equal to the distance between two adjacent chips, in the test state, the contact portion 310 can only contact the dicing track 42 and not the chip.

[0068] like Figure 3 and Figure 4 As shown, in a specific implementation, the multiple mounting holes 311 can be arranged in a straight line. The arrangement direction of the mounting holes 311 can be denoted as the x-direction, and the perpendicular direction of the arrangement direction of the mounting holes 311 can be denoted as the y-direction. The plane formed by the x-direction and the y-direction is parallel to the first surface of the main body 31.

[0069] On the one hand, along the x-direction, contact portions 310 can be provided on both sides of the mounting hole 311. More specifically, along the x-direction, at least one contact element is provided on each side of each mounting hole 311.

[0070] On the other hand, along the y-direction, contact portions 310 may be provided on both sides of the mounting hole 311. More specifically, along the y-direction, at least one contact element is provided on each side of each mounting hole 311.

[0071] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0072] In this application's embodiments, "multiple" refers to two or more. The descriptions of "first," "second," etc., appearing in this application's embodiments are merely illustrative and for distinguishing the described objects; they do not indicate any order and do not imply a specific limitation on the number of devices in this application's embodiments, nor do they constitute any limitation on the embodiments of this application. Although the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A fixture for wafer-level testing, comprising: The main body is characterized in that the fixture is used for testing image sensor chips, and the main body includes: In the test state, the first side faces the wafer being tested; The first surface is provided with a contact portion, which is adapted to the dicing track of the wafer under test; wherein, the adaptation of the contact portion to the dicing track of the wafer under test means that, in the test state, the contact portion only contacts the dicing track and does not contact other areas outside the dicing track. The contact portion protrudes relative to the first surface; The first surface has a mounting hole for mounting a lens; The contact portion has a closed planar shape; there are multiple mounting holes located within the closed shape; when the contact portion contacts the dicing channel, a closed space is formed between the contact portion and the wafer being tested. The contact portion is integrally formed, or the contact portion includes multiple contact elements arranged in an array; Each contact has a straight planar shape, and the width of the contact is less than or equal to the width of the dicing of the wafer being measured.

2. The fixture for wafer-level testing according to claim 1, characterized in that, The number of mounting holes is multiple, and the multiple mounting holes are arranged in a straight line.

3. The fixture for wafer-level testing according to claim 2, characterized in that, Along the arrangement direction of the plurality of mounting holes, each mounting hole has a contact portion on both sides.

4. The fixture for wafer-level testing according to claim 3, characterized in that, Perpendicular to the arrangement direction of the plurality of mounting holes, each mounting hole has a contact portion on both sides.

5. The fixture for wafer-level testing according to claim 1, characterized in that, The fixture also includes: a base, The main body also includes a second surface opposite to the first surface, the second surface being fixed to the base.

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