Accurate ber reporting at crc termination

Abstract

The present disclosure relates to accurate BER reporting at CRC termination, in particular to a method and system for LDPC decoding. In the method and system, a LDPC codeword is decoded using a quasi-cyclic matrix. A first message of a variable node in a cyclic column of the quasi-cyclic matrix and a second message of a check node belonging to the cyclic column are calculated. A parity check syndrome is calculated using the calculated first message and second message. A bit error rate of a first pattern in which the parity check part of the codeword has no error and a bit error rate of a second pattern in which the parity check part of the codeword has an error are calculated.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a scheme for error bit reporting. Background Technology

[0002] The computing environment paradigm has shifted to ubiquitous computing systems that can be used anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops has increased rapidly. These portable electronic devices typically use memory systems with memory devices, also known as data storage devices. Data storage devices serve as either the main memory or secondary memory devices in portable electronic devices.

[0003] Typically, memory systems utilizing memory devices offer excellent stability, durability, high data access speeds, and low power consumption because they have no moving parts. Examples of memory systems with these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces such as Universal Flash Memory (UFS), and Solid State Drives (SSDs). Data integrity is critical for data storage devices and data transfer. In solid state memory (e.g., NAND flash memory) devices, information is stored in cells via varying charge levels. During write and read operations, programming errors and inter-cell charge leakage introduce noise, causing voltage distribution and levels to decrease over time. Generating accurate read voltages improves the reliability and lifespan of the memory device.

[0004] In data storage systems, it is crucial to utilize a suitable error recovery system to ensure near-perfect recovery of the original stored data. An error recovery system is a set of error correction and detection techniques that not only ensures perfect recovery of the original data but also determines which techniques are used to meet system requirements such as throughput and Quality of Service (QoS).

[0005] In fact, solid-state drives (SSDs) use multi-layer NAND flash memory devices for persistent storage. However, multi-layer NAND flash memory devices can be inherently unreliable and often require error correction codes (ECC) to improve data reliability, but at the cost of additional storage space for ECC parity bits. There is a need for error correction that can provide data protection with improved decoding performance. Summary of the Invention

[0006] Aspects of the present invention include a method and system for LDPC decoding.

[0007] In one aspect, an LDPC decoding method is provided, comprising: decoding an LDPC codeword into a user portion and a parity portion using a quasi-cyclic matrix comprising multiple cyclic columns. Decoding of the cyclic columns includes: a) calculating messages for variable nodes in the cyclic column and messages for check nodes belonging to the cyclic column; b) calculating a cyclic redundancy check (CRC) parity check and corrector using the calculated messages; c) determining, based on the CRC parity check and corrector, whether the user portion of the LDPC codeword has been correctly decoded and whether the parity portion of the LDPC codeword has errors; and d) calculating the bit error rate (BER) in a first mode and a second mode. The first mode corresponds to the user portion of the LDPC codeword being correctly decoded and the parity portion of the LDPC codeword having no errors, and the second mode corresponds to the user portion of the LDPC codeword being correctly decoded and the parity portion of the LDPC codeword having errors.

[0008] On the other hand, a system for LDPC decoding is provided. The system includes a data source and a controller configured to perform LDPC decoding on bit information from the data source. The controller is configured to: decode an LDPC codeword into a user portion and a parity portion using a quasi-cyclic matrix; compute a first message for variable nodes in a cyclic column of the quasi-cyclic matrix and a second message for parity nodes belonging to the cyclic column; compute a parity check and corrector using the computed first and second messages; and compute the bit error rate of a first mode in which the parity portion of the LDPC codeword has no errors and the bit error rate of a second mode in which the parity portion of the LDPC codeword has errors.

[0009] Other aspects of the invention will become apparent from the following description. Attached Figure Description

[0010] Figure 1 This is a block diagram showing the data processing system.

[0011] Figure 2 This is a block diagram showing the memory system.

[0012] Figure 3 This is a circuit diagram showing the memory blocks of a memory device.

[0013] Figure 4 It is a diagram showing the state distribution of different types of cells in a memory device.

[0014] Figure 5A This is a diagram illustrating an example of Gray coding for a multilayer cell (MLC).

[0015] Figure 5BThis is a diagram showing the state distribution of pages in a multi-layer cell (MLC).

[0016] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC).

[0017] Figure 6B This is a diagram showing the state distribution of pages in a three-layer cell (TLC).

[0018] Figure 7 This is a diagram illustrating the flow of an error recovery algorithm in a memory system.

[0019] Figure 8 This is a diagram illustrating a memory system according to an embodiment of the present invention.

[0020] Figure 9A The diagram illustrates the data write path of the SSD.

[0021] Figure 9B A matrix depicting the user or data portion and the parity portion associated with the user portion.

[0022] Figure 10 A schematic depiction of the encoder's computational diagram.

[0023] Figure 11 A quasi-cyclic matrix is ​​depicted according to an embodiment of the present invention.

[0024] Figure 12 A cyclic matrix is ​​depicted according to an embodiment of the present invention.

[0025] Figure 13 This is a flowchart illustrating the operation of a bit error rate module according to an embodiment of the present invention. Detailed Implementation

[0026] Various embodiments of the invention are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey the scope of the invention to those skilled in the art. Furthermore, references herein to “embodiment,” “another embodiment,” etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term “embodiment” as used herein does not necessarily refer to all embodiments. Throughout this disclosure, the same reference numerals refer to the same parts in the drawings and embodiments of the invention.

[0027] This invention can be embodied in various ways, including, for example, processes; devices; systems; computer program products implemented on a computer-readable storage medium; and / or processors, such as processors suitable for executing instructions stored in and / or provided by memory linked to the processor. In this specification, these embodiments or any other form in which the invention may take may be referred to as technology. Generally, the order of operation of the disclosed processes can be varied within the scope of this invention. Unless otherwise stated, components such as processors or memory described as suitable for performing tasks can be configured or otherwise programmed as general-purpose means or circuit components that perform tasks at a given time, or specific means, or circuit components manufactured or pre-configured or pre-programmed to perform tasks. As used herein, the term "processor," etc., refers to one or more means, circuits, and / or processing cores suitable for processing data such as computer program instructions.

[0028] The methods, processes, and / or operations described herein may be executed, for example, by code or instructions executable by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or may be any computer, processor, controller, or other signal processing device other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described herein, the code or instructions for implementing embodiments of the methods may convert a computer, processor, controller, or other signal processing device into a dedicated processor for performing any of the methods described herein.

[0029] If implemented at least in part in software, controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing devices may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device.

[0030] Detailed descriptions of various embodiments of the invention are provided below with reference to the accompanying drawings illustrating aspects of the invention. The invention has been described in conjunction with these embodiments, but is not limited to any particular embodiment. The invention includes numerous alternatives, modifications, and equivalents. To provide a thorough understanding of the invention, numerous specific details are set forth in the following description. These details are provided for illustrative purposes; the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0031] Semiconductor memory devices can be volatile or non-volatile. Volatile semiconductor memory devices perform read and write operations at high speeds, but the contents stored in them may be lost when power is off. Non-volatile semiconductor memory devices retain their stored contents even when power is off. Non-volatile semiconductor memory devices can be used to store content that must be retained regardless of whether power is applied.

[0032] With the increasing demand for high-capacity memory devices, multi-level cell (MLC) or multi-bit memory devices that store multiple bits of data per cell are becoming increasingly common. However, memory cells in MLC non-volatile memory devices must have threshold voltages corresponding to four or more distinguishable data states within a finite voltage window. To improve data integrity in non-volatile memory devices, the level and distribution of the read voltage used to distinguish data states can be adjusted throughout the lifetime of the memory device to have optimal values ​​during read operations and / or read attempts.

[0033] Figure 1 This is a block diagram illustrating a data processing system 2 according to an embodiment of the present invention.

[0034] Reference Figure 1 The data processing system 2 may include a host device 5 and a memory system 10. The memory system 10 may receive requests from the host device 5 and operate in response to the received requests. For example, the memory system 10 may store data to be accessed by the host device 5.

[0035] The host device 5 can be implemented using any of a variety of electronic devices. In many embodiments, for example, the host device 5 can be an electronic device such as a desktop computer, workstation, 3D television, smart television, digital audio recorder, digital audio player, digital picture recorder, digital picture player, and / or digital video recorder and digital video player. In many embodiments, for example, the host device 5 can be a portable electronic device such as a mobile phone, smartphone, e-book reader, MP3 player, portable multimedia player (PMP), and / or portable game console.

[0036] The memory system 10 can be implemented using any of a variety of storage devices such as solid-state drives (SSDs) and memory cards. In various embodiments, for example, the memory system 10 can be configured as a component of a variety of electronic devices such as: computers, ultra-mobile personal computers (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, wireless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable gaming devices, navigation devices, black boxes, digital cameras, digital multimedia broadcasting (DMB) players, 3D televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, digital video players, data center storage devices, devices capable of receiving and transmitting information in a wireless environment, radio frequency identification (RFID) devices, and a variety of electronic devices for home networks, a variety of electronic devices for computer networks, a variety of electronic devices for telematics networks, or a component of a computing system.

[0037] The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 may control the overall operation of the semiconductor memory device 200, including the bit error rate reporting operation detailed below.

[0038] The semiconductor memory device 200 can perform one or more erase, program, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive commands (CMD), addresses (ADDR), and data (DATA) via input / output lines. The semiconductor memory device 200 can receive power (PWR) via power lines and control signals (CTRL) via control lines. Depending on the design and configuration of the memory system 10, the control signal CTRL may include, for example, a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals.

[0039] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid-state drive (SSD). The SSD may include a storage device for storing data therein.

[0040] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device, such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated to configure PC cards, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), miniature versions of MMC (micro MMC), secure digital cards (SD cards), mini secure digital cards (mini SD cards), micro secure digital cards (micro SD cards), secure digital high-capacity (SDHC) cards, and / or universal flash memory (UFS).

[0041] Figure 2 This is a block diagram illustrating a memory system according to an embodiment of the present invention. For example, Figure 2 The memory system can be described Figure 1 The memory system 10 shown.

[0042] Reference Figure 2 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can respond to requests from a host device (e.g., from...). Figure 1 The host device 5 operates upon request and, in particular, stores data to be accessed by the host device.

[0043] The semiconductor memory device 200 can store data to be accessed by a host device.

[0044] The semiconductor memory device 200 can be implemented using volatile memory devices such as dynamic random access memory (DRAM) and / or static random access memory (SRAM) or non-volatile memory devices such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric random access memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM) and / or resistive RAM (RRAM).

[0045] The memory controller 100 can control the storage of data in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from a host device. The memory controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided from the host device into the semiconductor memory device 200.

[0046] The memory controller 100 may include a storage device 110 connected via a bus 160, a control component 120 (which may be implemented as a processor such as an intermediate processing unit (CPU)), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150.

[0047] Storage device 110 can be used as working memory for memory system 10 and memory controller 100, and storage device 110 can store data used to drive memory system 10 and memory controller 100. Storage device 10 can store data used to encode and / or decode data bits being transmitted / received. For example, when memory controller 100 controls the operation of semiconductor memory device 200, storage device 110 can store data used by memory controller 100 and semiconductor memory device 200 to perform operations such as read operations, write operations, programming operations, and erase operations, including encoding and decoding operations.

[0048] Storage device 110 can be implemented using volatile memory such as static random access memory (SRAM) or dynamic random access memory (DRAM). As described above, storage device 110 can store data used by the host device for read and write operations in semiconductor memory device 200. For storing data, storage device 110 may include program memory, data memory, write buffer, read buffer, mapping buffer, etc.

[0049] Control component 120 can control the general operation of memory system 10 in response to write or read requests from host device, and control write or read operations of semiconductor memory device 200. Control component 120 can drive firmware or other program instructions, which may be referred to as a flash translation layer (FTL), to control the general operation of memory system 10. For example, FTL can perform operations such as logical-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block disposal. L2P mapping is referred to as logical block addressing (LBA).

[0050] During a read operation, the ECC component 130 can detect and correct errors in the data read from the semiconductor memory device 200, as detailed below. In one embodiment, when the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but instead output an error correction failure signal indicating that the correction of the error bits has failed.

[0051] In various embodiments, ECC component 130 may perform error correction operations based on coding modulation such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). Therefore, ECC component 130 may include any and all circuitry, systems, or devices suitable for error correction operations. In one embodiment of the invention, a quasi-cyclic LDPC matrix (described in detail below) is used for data recovery and bit error reporting.

[0052] The host interface 140 can communicate with the host device through one or more of the following communication standards or interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0053] Memory interface 150 provides an interface between memory controller 100 and semiconductor memory device 200, allowing memory controller 100 to control semiconductor memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for semiconductor memory device 200 and process data under the control of control component 120. In one embodiment, when semiconductor memory device 200 is flash memory, such as NAND flash memory, memory interface 150 can generate control signals for flash memory and process data under the control of control component 120.

[0054] For example Figure 2 The illustrated semiconductor memory device 200 may include a memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer array 250 (which may be in the form of an array of page buffers), column decoder 260, and input / output (input / output) circuitry 270. The memory cell array 210 may include multiple memory blocks 211 capable of storing data. The voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and input / output circuitry 270 may form peripheral circuitry for the memory cell array 210. The peripheral circuitry may perform programming, reading, or erasing operations on the memory cell array 210. The control circuitry 220 may control the peripheral circuitry.

[0055] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0056] The line decoder 240 can communicate electrically with the voltage generation circuit 230 and a plurality of memory blocks 211. In response to a line address generated by the control circuit 220, the line decoder 240 can select at least one memory block among the plurality of memory blocks 211 and transmit the operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0057] Page buffer array 250 can be accessed via bit line BL ( Figure 3 (As shown) is connected to the memory cell array 210. The page buffer array 250 can precharge the bit line BL with a positive voltage during programming and read operations in response to the page buffer control signal generated by the control circuit 220, transfer data to and receive data from the selected memory block, or temporarily store the transferred data.

[0058] The column decoder 260 can transmit data to and receive data from the page buffer array 250, or it can transmit data to and receive data from the input / output circuit 270.

[0059] Input / output circuit 270 can input from external devices (e.g., Figure 1 The memory controller 100 receives commands and addresses and transmits them to the control circuit 220, which transmits data from an external device to the column decoder 260, or outputs data from the column decoder 260 to an external device.

[0060] The control circuit 220 can control the peripheral circuits in response to commands and addresses.

[0061] Figure 3 This is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, Figure 3 The storage block can be Figure 2 Any one of the storage blocks 211 in the memory cell array 210 shown.

[0062] Reference Figure 3 Storage block 211 may include multiple word lines WL0 to WLn-1, drain select line DSL, and source select line SSL connected to line decoder 240. These lines may be arranged in parallel and have multiple word lines between DSL and SSL.

[0063] The memory block 211 may further include multiple cell strings 221 respectively connected to bit lines BL0 to BLm-1. Each column of cell strings may include one or more drain select transistors (DSTs) and one or more source select transistors (SSTs). In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, multiple memory cells or memory cell transistors MC0 to MCn-1 may be connected in series between the select transistors DST and SST. Each of the memory cells may be formed as a multi-level cell. For example, each of the memory cells may be formed as a single-level cell (SLC) storing 1 bit of data. Each of the memory cells may be formed as a multi-level cell (MLC) storing 2 bits of data. Each of the memory cells may be formed as a three-level cell (TLC) storing 3 bits of data. Each of the memory cells may be formed as a four-level cell (QLC) storing 4 bits of data.

[0064] The source of each SST in a cell string can be connected to the common source line CSL, and the drain of each DST can be connected to the corresponding bit line. The gate of an SST in a cell string can be connected to SSL, and the gate of a DST in a cell string can be connected to DSL. The gates of memory cells in different cell strings can be connected to the corresponding word lines. That is, the gate of memory cell MC0 is connected to the corresponding word line WL0, the gate of memory cell MC1 is connected to the corresponding word line WL1, and so on. A group of memory cells connected to a specific word line can be called a physical page. Therefore, the number of physical pages in memory block 211 can correspond to the number of word lines.

[0065] Page buffer array 250 may include multiple page buffers 251 connected to bit lines BL0 to BLm-1. Page buffers 251 may operate in response to page buffer control signals. For example, page buffers 251 may temporarily store data received through bit lines BL0 to BLm-1 or sense the voltage or current of the bit lines during read or verification operations.

[0066] In various embodiments of the present invention, memory block 211 may include NAND flash memory cells. However, memory block 211 is not limited to this cell type, but may include NOR flash memory cells. Memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a 1-NAND flash memory with the controller embedded within the memory chip.

[0067] Figure 4 It is a diagram showing the state or programming voltage (PV) level distribution of different types of cells in a memory device.

[0068] Reference Figure 4Each memory cell can be implemented using a specific type of cell such as: a single-level cell (SLC) that stores 1 bit of data, a multi-level cell (MLC) that stores 2 bits of data, a three-level cell (TLC) that stores 3 bits of data, or a four-level cell (QLC) that stores 4 bits of data. Typically, all memory cells in a particular memory device belong to the same type, but this is not required.

[0069] An SLC can include two states, P0 and P1. P0 can represent the erase state, and P1 can represent the programming state. Because an SLC can be set to one of two different states, each SLC can be programmed or store one bit according to a set encoding method. An MLC can include four states, P0, P1, P2, and P3. Among these states, P0 can represent the erase state, and P1 through P3 can represent the programming state. Because an MLC can be set to one of four different states, each MLC can be programmed or store two bits according to a set encoding method. A TLC can include eight states, P0 through P7. Among these states, P0 can represent the erase state, and P1 through P7 can represent the programming state. Because a TLC can be set to one of eight different states, each TLC can be programmed or store three bits according to a set encoding method. A QLC can include sixteen states, P0 through P15. Among these states, P0 can represent the erase state, and P1 through P15 can represent the programming state. Because a QLC can be set to one of sixteen different states, each QLC can be programmed or store four bits according to a set encoding method.

[0070] Return to reference Figure 2 and Figure 3 The semiconductor memory device 200 may include multiple memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, such as... Figure 3As shown. Cells in each row are connected to word lines (e.g., WL0), and cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, data to be written ("1" or "0") is provided on the bit line while the word line is addressed. During a read operation, the word line is addressed again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. For example, the memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0071] Figure 5A This is a diagram illustrating an example of encoding a multilayer cell (MLC).

[0072] Reference Figure 5A The MLC can be programmed using a specified type of encoding. The MLC can have four programming states: erase state E (or PV0) and first programming states PV1 through third programming states PV3. Erase state E (or PV0) can correspond to "11". First programming state PV1 can correspond to "10". Second programming state PV2 can correspond to "00". Third programming state PV3 can correspond to "01".

[0073] In MLC, such as Figure 5B As shown, there are two types of pages: LSB pages and MSB pages. One or two thresholds can be applied to retrieve data from the MLC. For MSB pages, the single threshold is VT1. VT1 distinguishes between the first programming state PV1 and the second programming state PV2. For LSB pages, the two thresholds are threshold VT0 and threshold VT2. VT0 distinguishes between the erase state E and the first programming state PV1. VT2 distinguishes between the second programming state PV2 and the third programming state PV3.

[0074] Figure 6A This is a diagram illustrating an example of Gray encoding for a three-layer cell (TLC).

[0075] Reference Figure 6ATLCs can be programmed using Gray code. A TLC can have eight programming states, including an erase state E (or PV0) and first programming states PV1 through seventh programming states PV7. Eraser state E (or PV0) can correspond to "111". First programming state PV1 can correspond to "011". Second programming state PV2 can correspond to "001". Third programming state PV3 can correspond to "000". Fourth programming state PV4 can correspond to "010". Fifth programming state PV5 can correspond to "110". Sixth programming state PV6 can correspond to "100". Seventh programming state PV7 can correspond to "101".

[0076] In TLC, such as Figure 6B As shown, there are three types of pages: LSB pages, CSB pages, and MSB pages. Two or three thresholds can be applied to retrieve data from the TLC. For MSB pages, the two thresholds include threshold VT0, which distinguishes between erase state E and first programming state PV1, and threshold VT4, which distinguishes between fourth programming state PV4 and fifth programming state PV5. For CSB pages, the three thresholds include VT1, VT3, and VT5. VT1 distinguishes between first programming state PV1 and second programming state PV2. VT3 distinguishes between third programming state PV3 and fourth programming state PV4. VT5 distinguishes between fifth programming state PV5 and sixth programming state PV6. For LSB pages, the two thresholds include VT2 and VT6. VT2 distinguishes between second programming state PV2 and third programming state PV3. VT6 distinguishes between sixth programming state PV6 and seventh programming state PV7.

[0077] In such Figure 5A and Figure 6A After programming the memory array comprising multiple memory cells, when a read operation is performed on the memory array using a reference voltage such as a read threshold voltage (also referred to as a "read voltage level" or "read threshold"), the charge level of the memory cell (e.g., the threshold voltage level of the memory cell's transistor) is compared with one or more reference voltages to determine the state of each memory cell. For example, when a specific read threshold is applied to the memory array, memory cells with threshold voltage levels higher than the reference voltage are turned on and detected as "on" cells, while memory cells with threshold voltage levels lower than the reference voltage are turned off and detected as "off" cells. Therefore, each read threshold is set between adjacent threshold voltage distribution windows corresponding to different programming states, such that each read threshold can distinguish these programming states by turning the memory cell transistors on or off.

[0078] When performing a read operation on a memory cell in a data storage device using MLC technology, the threshold voltage level of the memory cell is compared to more than one read threshold level to determine the state of each memory cell. Distorted or overlapping threshold voltage distributions can lead to read errors. Ideal memory cell threshold voltage distributions can be severely distorted or overlapped due to factors such as program / erase (P / E) cycles, inter-cell interference, and / or data retention errors. For example, as program / erase cycles increase, the margin between adjacent threshold voltage distributions of different programming states decreases, eventually leading to overlapping distributions. Therefore, memory cells whose threshold voltages fall within the overlapping region of adjacent distributions may be read as having been programmed to values ​​different from the original target values, thus resulting in read errors. In many cases, such read errors can be managed by using error correction codes (ECC). A read operation using a set read threshold voltage fails when the number of bit errors exceeds the ECC error correction capability of the data storage device. The set read threshold voltage can be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage can be the read threshold voltage used in the last successful decoding, that is, the read voltage used in a successful read operation performed before the read retry operation. When a read operation using the set read threshold voltage fails, the control component 120 can control an error recovery algorithm, such as... Figure 7 The algorithm shown.

[0079] Reference Figure 7 The control component 120 may perform one or more read retry operations on memory cells using one or more read threshold voltages applied in a set order (S100). For example, the read threshold voltages may include N (e.g., N is 5 or 10) read threshold voltages (or read voltage levels), including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). The historical read threshold voltage may be the read threshold voltage used in the last successful decoding, i.e., the read voltage used in a successful read operation performed before the read retry operation. The control component 120 may perform read retry operations until a successful decoding associated with the corresponding read retry operation is determined.

[0080] When all read retry operations using the read threshold voltage fail, the control component 120 may perform additional recovery operations. For example, the additional recovery operations may include optimal read threshold voltage search (S200), soft decoding using error correction codes (ECC) (S300), and / or redundant array of independent disks (RAID) recovery (S400).

[0081] As mentioned above, data retrieved from a memory device (e.g., a NAND flash memory device) within a data storage device (e.g., a solid-state drive (SSD)) typically contains numerous bit errors due to various noise sources. To protect the data, it is encoded using an error correction code before being written to the memory device (i.e., before being written to the storage medium). A decoder can then use this error correction code to correct all bit errors. Figure 7 As indicated by "read retry," in one embodiment of the invention, when the number of bit errors exceeds the capacity of the error correction code, the data storage device can invoke a specific defense algorithm (e.g., a read retry operation) to read the storage medium multiple times with better parameters than the original read operation until the data can be recovered using the error correction code. In one embodiment of the invention, as detailed below, different read thresholds can be used to better read data pages.

[0082] For solid-state drives, one source of increased bit errors is the use of suboptimal read thresholds during read operations. One approach to estimating the optimal read threshold (e.g., the eBoost algorithm) involves performing multiple additional read operations on the same page using different read thresholds and estimating the optimal read threshold that minimizes bit errors in the retrieved data. These additional read operations can increase read operation latency and may degrade the Quality of Service (QoS) of the data storage device (or memory system).

[0083] Figure 8 This is a diagram illustrating a memory system 10 according to an embodiment of the present invention.

[0084] Reference Figure 8 The memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The semiconductor memory device 200 may include a plurality of memory cells (e.g., NAND flash memory cells) 210. Memory cells such as... Figure 3The array is shown in rows and columns. Cells in each row are connected to word lines (e.g., WL0), while cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided to the bit line when the word line is addressed. During a read operation, the word line is addressed again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share a memory cell belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, the multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, the multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0085] The memory controller 100 may include a read processor 810, a decoder 820, and an optimal read threshold determiner 830. Although the components of the memory controller 100 shown are implemented separately, these components may also be used... Figure 2 The control component 120 is implemented using internal components (i.e., firmware (FW)). The memory controller 100 and the semiconductor memory device 200 may include various other components, such as Figure 2 The components shown.

[0086] Encoding and Decoding Data

[0087] Data retrieved directly from a storage device (e.g., an SSD) and its data storage medium (e.g., NAND flash memory) often contains noise. To protect the data, it is encoded using error correction codes before being written to another medium. The encoder design is important for the read / write performance of the SSD and also for reading / writing data to other memory devices. In one embodiment of the invention, the ECC module provides feedback to the firmware (FW) on the bit error rate (the number of bit errors in the received sequence) as a measure of NAND flash memory quality.

[0088] In one embodiment of the invention, an inventive technique for reporting bit error rate (BER) is provided that does not cause additional latency and can be implemented in hardware at a very low cost (with a small number of additional gate counts).

[0089] In data storage systems (e.g., SSDs), ECC technology has been used to retrieve and correct data from noisy data stored on storage media (e.g., NAND flash memory). When retrieving stored data during a read operation, it is typically different from the original codewords; the difference is that it is a noisy version of the original codewords. During decoding, the noisy codewords are corrected, and the corrected data is returned to the host device 5.

[0090] Figure 9A The write data path in the SSD is shown. Cyclic Redundancy Check (CRC) is an error detection code commonly used in digital networks and storage devices to detect accidental alterations to the original data. Before storing data, the host data (u h )Add its CRC parity check (u=u h +u CRC After adding CRC parity check, the data is encoded using LDPC encoding, which also adds LDPC parity check. The extra parity bits help with decoding if unexpected errors occur. The encoded sequence (c), called the codeword, is as follows: Figure 9A As shown, it is stored in a storage medium such as memory cell array 210.

[0091] As described in U.S. Patent No. 9,256,487 (the entire contents of which are incorporated herein by reference), Low-Density Parity-Check (LDPC) coding was first proposed in the 1960s, but it did not become widely used until researchers began studying iterative coding and decoding techniques in the 1990s. As described in the '487 patent, LDPC codes are one of the few known error control coding techniques capable of transmitting information at rates close to the Shannon limit or channel capacity.

[0092] As described in '487 patent, an iterative decoder can use an iterative message-passing algorithm, such as a minimum-sum decoding algorithm, to decode LDPC codes. These algorithms can decode a received codeword using an iterative process, where each iteration includes two update steps. In the first update step, a message can be passed from some (or all) check nodes to some (or all) variable nodes, and in the second update step, the message can be passed from some (or all) variable nodes to some (or all) check nodes. Variable nodes can represent each position in the codeword u. Check nodes can represent each parity check equation.

[0093] like Figure 9A As shown, let c be an LDPC codeword, and let u be the user or data portion of the LDPC codeword (u = u h +u CRCLet p be the LDPC parity check part added to the user part, i.e., c = [up], and let H be the LDPC parity check matrix.

[0094] In theory, any codeword c should satisfy all parity check equations of the LDPC code. That is:

[0095] c·H T =0 (1)

[0096] If the LDPC code is systematic, then both the user part and the parity check part of the codeword and parity check matrix can be separated:

[0097] [up]×[H u H p ] T =0

[0098]

[0099] Therefore, the LDPC parity check (p) can be calculated as follows:

[0100]

[0101] make Let s be a partial corrector from the user portion. like Figure 10 As shown, the calculation in the encoder can be divided into two stages. The first stage calculates the partial corrector. The second stage calculates the parity check part of the LDPC codeword, p = sG. T The values ​​of the corrector and LDPC parity check are stored for decoding.

[0102] Quasi-cyclic LDPC codes

[0103] In one embodiment of the present invention, a matrix G is used to calculate the parity check component. T Is it like this? Figure 11 The quasi-cyclic matrix shown is 1100. More specifically, Figure 11 It describes the quasi-circular matrix G. T A schematic diagram of the structure of 1100. G T It consists of a circular matrix of size n×n. An m×m square matrix consisting of (here referred to as a cyclic column). The time slot is matrix G. T A region of 1100 can be filled by a cyclic matrix 1102. Figure 11 The fuzzy region 1104 in the matrix represents the region in matrix 1100 that has all zero values. It is a quasi-circular matrix G T The number of horizontal and vertical time slots that can be filled by the cyclic matrix 1102 in 1100. In the quasi-cyclic matrix G...T The CPC has There are 1000 time slots. Not all time slots are occupied by the cyclic matrix 1002.

[0104] Figure 11 The matrix G shown T 1100 has the special property that there exists a continuous cyclic column 1102 in adjacent columns sharing a row slot. Let R p Define row slots corresponding to row weights equal to 1, followed by contiguous shared row sets. For example, in Figure 11 In the middle, R p =[4, 0, 2, 1, 3]. Set r p express Figure 11 The path indicated by the black arrow (i.e., the row slot path) has the first entry "4" indicating the cyclic column 1102 "row 4", which is a row slot with only one cyclic matrix, so the row weight is 1.

[0105] Circular matrix This represents a cyclic shift of the identity matrix. In a cyclic matrix... In this context, i represents the horizontal time slot index, j represents the vertical time slot index, and k represents the circular right shift amount. For example, if k = 0, then C 0 It is the identity matrix. If the size of C is a 3×3 matrix, then C 1 like Figure 12 As shown.

[0106] DPC decoding algorithm

[0107] In one embodiment of the invention, in hardware (e.g., via an application-specific integrated circuit system), various message-passing algorithms that transmit messages between variable nodes and check nodes iteratively complete the LDPC decoding of quasi-cyclic codes. Here, as previously described, a variable node can represent each position in the codeword u, and a check node can represent each corrector (parity check equation). In one example of a message-passing algorithm, a message passed from a variable node VN to a check node CN can represent a probability that, given the observed value of the variable node and all values ​​passed from the check node to the variable node receiving the message to VN in the previous round, the VN receiving the message has a certain value. On the other hand, a message passed from a check node CN to a variable node VN can be a probability that, given all messages passed from variable nodes other than the variable node receiving the message to the check node CN in the previous round, the variable node VN receiving the message has a certain value. For example, assuming the size of the cyclic matrix is ​​m×m, each cyclic column contains m VNs, and each cyclic row contains m CNs.

[0108] In one embodiment of the invention, to improve decoding latency, in each iteration, messages for all variable nodes VN belonging to the same cyclic column are computed and sent in parallel. Messages are passed between VN and CN. That is, messages for all variable nodes VN belonging to the same cyclic column are computed and sent to the corresponding CN. Similarly, messages for all parity nodes CN belonging to the same cyclic column are processed in parallel. The messages passed between the variable nodes and parity nodes are typically real numbers representing the probability of what values ​​these nodes should have, thus providing a method for correcting noisy codewords. If the codeword change is correct, multiplying the corrected codeword by the parity check matrix should produce the previously stored corrector s = 0.

[0109] In the following embodiment, i (0≤i≤i) max () indicates the number of iterations. This indicates that variable node j decides to change its value during the i-th iteration and Assumption Where y can be the received noise channel input sequence of data bit values ​​retrieved from memory. Let Let d represent the corrector at iteration i, and let the calculated d (i) The corrector is cs (i) =||s (i) ||., let diff h (x, y) represents the Hamming distance between sequences x and y. The Hamming distance defines the number of bits required to change a binary value in order to produce another value. The traditional message-passing decoding algorithm works as follows:

[0110] Step 0: Let i = 0, calculate s (-1) And calculate Cyclic Redundancy Check (CRC) and Parity Check. Proceed to step 1;

[0111] Step 1: i = i + 1. If the maximum number of iterations is reached, stop decoding. Otherwise, proceed to Step 2.

[0112] Step 2: If decoding is successful, stop decoding. Otherwise, proceed to Step 3;

[0113] Step 3: Set ber = 0.

[0114] Step 4: For 1≤j≤n circ , where n circ It is a circular column.

[0115] Parallel computation of messages of VN in cyclic column j

[0116] Calculate the CN message corresponding to the cyclic column j (QC LDPC parallel message passing is standard message passing, but the CN message is modified).

[0117] ○ Calculate and update CRC parity check based on the changes in the user portion of the codeword generated by the computation message.

[0118] ○ Calculate and update the corrector s (i)

[0119] Update bit error rate

[0120] Proceed to step 1;

[0121] Decoding stops in one of the following modes:

[0122] Mode 0: Decoding failed: LDPC parity section invalid

[0123] First mode: Decoding successful: LDPC parity check part CS i =0 & CRC valid

[0124] Second mode: Successful CRC decoding: 0 <cs i &CRC valid

[0125] The BER calculated in step 3 of the above decoding algorithm is equal to the actual BER in the first mode.

[0126] Previous BER calculation schemes (as described above) could only accurately calculate the BER in the first mode. In other words, if the decoder could use cs (i) =0, indicating a successful CRC decoding of the codeword. The decoder can then process the decoded codeword y. 1 The difference in the number of bits between the input sequence y of the noise channel, for example, retrieved from a NAND storage device, is determined as the BER.

[0127] BER pseudocode of the present invention

[0128] make This is the corrector updated after processing the j-th cyclic column in the i-th decoding iteration. Let j... p For the index of the first parity cycle column, such as Figure 9B As shown, Figure 9B The j in the parity check part of the matrix is ​​shown. p First cycle column.

[0129] Let y be a noise sequence received from a channel (e.g., from a NAND memory device), let y u For example, y is the user or data portion. Figure 9BThe user portion is shown in the matrix. Let ss = [s1′, s2′] be two cycle-sized snapshots of the corrector. That is, ss is a copy of the two cycle rows of the original corrector. The decoding algorithm using the BER module of this invention is updated as follows:

[0130] Step 0: Let i = 0, calculate s (-1) And calculate CRC parity check. Proceed to step 1;

[0131] Step 1: i = i + 1. If the maximum number of iterations is reached, stop decoding. Otherwise, proceed to Step 2.

[0132] Step 2: If decoding is successful, stop decoding. Otherwise, proceed to Step 3;

[0133] Step 3: Set ber = 0.

[0134] Step 4: For 1≤j≤n circ , where n circ It is the column number in the circular column j, and the VN messages in the circular column j are computed in parallel.

[0135] ○ Calculate the message corresponding to CN in the circular column j.

[0136] ○ Calculate and update CRC parity check based on the changes in the user portion of the codeword generated by the computation message.

[0137] ○ Calculate and update the corrector s (i)

[0138] ○If j <j p :

[0139] ■

[0140] Otherwise, if j>j p :

[0141] ■Let parity index p j =(jj p -1)

[0142] ■r j (1) , This represents the index of the two cyclic rows corresponding to the parity snapshot of cyclic column j. For example, for the first parity cyclic column (p... j =0), the calibrator snapshot is s1′=S4, s2′=S0 (the fourth loop row and the first loop row of the calibrator are the calibrator snapshots of the first column of the parity check).

[0143] ■kj (1) k j (2) = Odd-even cyclic column p j The line time slot r j (1) r j (2) Circular shift

[0144] ■If p j =0, then otherwise

[0145] ■ Update hard decisions (s1′) (Circular shift). In each variable node j, the hard decision in each iteration is the variable node guess (decision) for the value of the j-th bit. This value is typically obtained by summing all incoming messages of the VN (including channel LLR and all CN messages).

[0146] ■ Update correction snapshot (s1′) (Circular shift). The corrector snapshot s2′ is the second row of the corrector corresponding to the current parity column at each iteration.

[0147] ■ Copy s1′=s2′.

[0148] ■Update Proceed to step 1;

[0149] BER performance

[0150] Even if the decoder is in second mode, meaning the user portion has been correctly decoded (valid CRC confirmation), some errors still exist in the parity check portion of the codeword (cs). i (≠0), the BER module of this invention is also capable of accurately calculating the BER (the difference in the number of bits between the decoded codeword and the noise channel input sequence). With valid CRC verification, the BER module of this invention can recalculate the correct parity check without using a complex encoder. In fact, since the BER module of this invention does not require the additional memory (registers) typically needed by encoders, it does not increase the number of silicon gates as required by encoders without a BER algorithm. Furthermore, since the BER module of this invention can calculate the parity check in parallel with decoding, it does not add any additional latency.

[0151] Figure 13This is a flowchart illustrating the operation of the BER module of the present invention. In 1301, the LDPC codeword is decoded using a quasi-cyclic matrix. In 1303, the first message of the variable nodes in the cyclic column of the quasi-cyclic matrix and the second message of the check nodes belonging to the cyclic column are calculated. In 1305, the calculated first and second messages are used to calculate the parity check and the corrector. In 1307, the bit error rate of a first mode where the parity check portion of the codeword has no errors and the bit error rate of a second mode where the parity check portion of the codeword has errors are calculated.

[0152] Figure 13 The operation of the BER module of the present invention, detailed in the description, provides an LDPC decoding method, comprising: decoding an LDPC codeword into a user portion and a parity portion using a quasi-cyclic matrix comprising multiple cyclic columns. Decoding of a specific cyclic column among the multiple cyclic columns includes: a) calculating the message of the variable node in the cyclic column and the message of the parity node belonging to the cyclic column; b) calculating a Cyclic Redundancy Check (CRC) parity check and corrector using the calculated messages; c) determining, based on the CRC parity check and corrector, whether the user portion of the codeword has been correctly decoded and whether the parity portion of the codeword has errors; and d) calculating the bit error rate (BER) in a first mode and a second mode. The first mode corresponds to the user portion of the codeword being correctly decoded and the parity portion of the codeword having no errors. The second mode corresponds to the user portion of the codeword being correctly decoded and the parity portion of the codeword having errors.

[0153] In this method, the quasi-cyclic matrix includes a square matrix of size m×m, which includes a square cyclic matrix of size n×n. The square cyclic matrix partially fills the row slots in the quasi-cyclic matrix, wherein the square cyclic matrix includes cyclic columns.

[0154] In this method, at least two square cyclic matrices of size n×n are arranged as consecutive cyclic columns in the same row slot of the quasi-cyclic matrix.

[0155] In this method, a square circular matrix comprising consecutive circular columns in a quasi-circular matrix defines a row path through the quasi-circular matrix, wherein the row path is defined by a row index r associated with each circular matrix in the row path. i Quantify it.

[0156] The calculation of the bit error rate (BER) in the second mode may include iterative processing of the cyclic columns in the alignment cyclic matrix. The iterative processing may include cyclic shifting of row slots in two cyclic size corrector snapshots of two consecutive cyclic columns.

[0157] This method can further determine the bit error rate at the start of the iterative process and update the bit error rate after an entry in the user portion of the LDPC codeword is changed to a bit. The method can further generate a corrector after the entry change. The method can further determine the successful decoding of the user portion and parity portion by calculating the Cyclic Redundancy Check (CRC) of the parity check in both the user portion and parity check portion. The method can further transmit the corrected data bit information to the host device after successful decoding of the user portion and parity check portion.

[0158] In one embodiment of the present invention, the BER algorithm can be combined with... Figure 2 The error correction code (ECC) component 130 is shown. The BER algorithm can be integrated into the control circuit 220.

[0159] In one embodiment of the present invention, a system for LDPC decoding is provided, comprising:

[0160] Data source (e.g., memory cell array 210); and

[0161] The controller (e.g., control circuit 220) is configured to perform LDPC decoding on the data bit information from the data source.

[0162] The controller is programmed as follows:

[0163] The LDPC codeword is decoded into a user part and a parity check part using a quasi-cyclic matrix;

[0164] Calculate the first message of the variable node in the cyclic column of the quasi-cyclic matrix and the second message of the check node belonging to the cyclic column;

[0165] Calculate the parity check and the corrector using the first and second messages; and

[0166] Calculate the bit error rate of the first mode of the LDPC codeword with no errors in the parity check section and the bit error rate of the second mode of the LDPC codeword with errors in the parity check section.

[0167] Here, in the system used for LDPC encoding, the quasi-cyclic matrix may include a square matrix of size m×m, which includes square cyclic matrices of size n×n that partially fill the row slots of the quasi-cyclic matrix, wherein the square cyclic matrices include cyclic columns. In one embodiment, at least two square cyclic matrices of size n×n are arranged as consecutive cyclic columns in the same row slot of the quasi-cyclic matrix (e.g., as shown in the figure). Figure 11(As shown). In one embodiment, a square circular matrix comprising consecutive circular columns in a quasi-circular matrix defines a row path through the quasi-circular matrix, wherein the row path is defined by a row index r associated with each circular matrix in the row path. i Quantify it.

[0168] Here, in this system for LDPC encoding, the controller can be programmed to perform iterative processing on cyclic columns in a cyclic matrix. In one embodiment, the iterative processing includes cyclic shifting of row slots in two cyclic-size corrector snapshots of two consecutive cyclic columns.

[0169] Here, in this system for LDPC encoding, the controller can be programmed to determine the bit error rate at the start of the iterative process and to update the bit error rate after the entries in the user portion of the LDPC codeword are changed to bits.

[0170] Here, in this system used for LDPC encoding, the controller can be programmed to generate a corrector after an entry changes.

[0171] Here, in this system for LDPC encoding, the controller can be programmed to determine successful decoding of the user portion and parity portion by calculating the cyclic redundancy check (CRC) of the parity check for the user portion and the parity portion. In one embodiment, the controller is programmed to transmit the corrected data bits to the host device after successful decoding of the user portion and the parity portion.

[0172] Although the foregoing embodiments have been shown and described in detail for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are exemplary and not restrictive. The invention is intended to cover all modifications and alternatives to the disclosed embodiments. Furthermore, the disclosed embodiments can be combined to form other embodiments.

[0173] In fact, embodiments and functional operations of the subject matter described in this patent application can be implemented in various systems, digital electronic circuits including the structures disclosed in this specification and their equivalents or combinations thereof, or in computer software, firmware, or hardware. Embodiments of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium, which are operated by a data processing device or control the operation of a data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition affecting machine-readable propagation signals, or combinations thereof. The terms "data processing unit" or "data processing device" encompass all devices, apparatuses, and machines for processing data (e.g., including programmable processors, computers, or multiple processors or computers). In addition to hardware, the device may also include code that creates an operating environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or combinations thereof.

[0174] Computer programs (also known as programs, software, software applications, scripts, or code) can be written in any programming language (including compiled or interpreted languages) and can be deployed in any form, including as standalone programs suitable for use in a computing environment, or as modules, components, subroutines, or other units. A computer program does not necessarily correspond to a file in a file system. A program can be stored as a portion of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), a single file dedicated to the program in question, or multiple coordination files (e.g., files storing portions of one or more modules, subroutines, or code). A computer program can be deployed to run on a single computer or on multiple computers located at one site or distributed across multiple sites and interconnected via a communications network.

[0175] The processes and logic flows described in this specification can be executed by one or more programmable processors that run one or more computer programs to perform functions by manipulating input data and generating data. The processes and logic flows can also be executed by special-purpose logic circuitry (e.g., FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits)), and the device can also be implemented as special-purpose logic circuitry (e.g., FPGAs or ASICs).

[0176] A processor suitable for running computer programs includes, for example, both general-purpose microprocessors and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, the processor receives instructions and data from read-only memory or random access memory, or both. The basic building blocks of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magnetic, magneto-optical, or optical discs) for storing data, or operatively coupled to receive data from or transfer data to one or more mass storage devices (e.g., magnetic, magneto-optical, or optical discs). However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices). The processor and memory may be supplemented by or incorporated into special-purpose logic circuitry.

[0177] While this patent application contains numerous details, these details should not be construed as limiting the scope of any invention or any claimable invention, but rather as a description of specific features that may be present in a particular embodiment of a particular invention. Certain features described in the context of individual embodiments in this patent application may also be implemented in combinations of individual embodiments. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any applicable sub-combinations. Furthermore, although the foregoing may describe features as functioning in certain combinations, in some cases one or more features of a combination may be excluded from the combination, and the combination may be for sub-combinations or variations thereof.

[0178] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential order, or requiring all of the operations shown, in order to achieve the desired effect. Furthermore, the separation of various system components in the embodiments described in this patent application should not be construed as requiring such separation in all embodiments.

[0179] This patent application describes only a few embodiments and examples, and other embodiments, improvements and variations can be made based on what is described and shown in this patent application.

Claims

1. An LDPC decoding method, comprising: The LDPC codeword is decoded into a user part and a parity part using a quasi-cyclic matrix that includes multiple cyclic columns; Decoding the cyclic columns among the plurality of cyclic columns includes: Calculate the messages of the variable nodes in the circular column and the messages of the check nodes belonging to the circular column; The computational message is used to calculate the cyclic redundancy check parity check, i.e., CRC parity check and the corrector; The first mode and the second mode are determined based on the CRC parity check and the corrector; and Calculate the bit error rate (BER) for the first mode and the second mode. The first mode corresponds to the case where the CRC parity check is valid and the parity factor has a specific value, indicating that the user portion of the LDPC codeword has been correctly decoded and the parity check portion of the LDPC codeword is error-free; and The second mode corresponds to the case where the CRC parity check is valid and the corrector does not have the specific value, which indicates that the user portion of the LDPC codeword has been correctly decoded but the parity check portion of the LDPC codeword has an error.

2. The method according to claim 1, wherein, The quasi-cyclic matrix includes a square matrix of size m×m, the square matrix includes a square cyclic matrix of size n×n, the square cyclic matrix partially fills the row slots of the quasi-cyclic matrix, and the square cyclic matrix includes the cyclic column.

3. The method according to claim 2, wherein, Arrange at least two square cyclic matrices of size n×n as consecutive cyclic columns on the same row slot of the quasi-cyclic matrix.

4. The method according to claim 3, wherein, The square circular matrix, including consecutive circular columns in the quasi-circular matrix, defines a row path through the quasi-circular matrix, the row path being defined by a row index r associated with each circular matrix in the row path. i Quantify it.

5. The method according to claim 3, wherein, The calculation of the bit error rate in the second mode includes iterative processing of the cyclic columns in the quasi-cyclic matrix.

6. The method according to claim 5, wherein, The iterative process includes a cyclic shift of row slots in two cyclic size corrector snapshots of the two consecutive cyclic columns.

7. The method of claim 5, further comprising: The bit error rate is determined at the start of the iterative process; as well as The bit error rate is updated after the entry in the user portion of the LDPC codeword is changed to a bit.

8. The method of claim 7, further comprising generating a corrector after the entry is changed.

9. The method of claim 1, further comprising determining successful decoding of the user portion and the parity portion by calculating a cyclic redundancy check of the parity of the user portion and the parity portion.

10. The method according to claim 9, wherein, After successful decoding of the user portion and the parity portion, the corrected data bit information is transmitted to the host device.

11. A system for LDPC decoding, comprising: Data source; as well as The controller performs LDPC decoding on the data bits from the data source. The controller mentioned above: The LDPC codeword is decoded into a user part and a parity check part using a quasi-cyclic matrix; Calculate the first message of the variable node in the cyclic column of the quasi-cyclic matrix and the second message of the check node belonging to the cyclic column; The first and second messages are used to calculate the Cyclic Redundancy Check (CRC) parity check and the corrector. The first mode and the second mode are determined based on the CRC parity check and the corrector; and Calculate the bit error rate (BER) for the first mode and the second mode. The first mode corresponds to the case where the CRC parity check is valid and the parity factor has a specific value, indicating that the user portion of the LDPC codeword has been correctly decoded and the parity check portion of the LDPC codeword is error-free; and The second mode corresponds to the case where the CRC parity check is valid and the corrector does not have the specific value, which indicates that the user portion of the LDPC codeword has been correctly decoded but the parity check portion of the LDPC codeword has an error.

12. The system of claim 11, wherein the quasi-cyclic matrix comprises a square matrix of size m×m, the square matrix comprises a square cyclic matrix of size n×n, the square cyclic matrix partially filling the row slots of the quasi-cyclic matrix, wherein the square cyclic matrix comprises the cyclic column.

13. The system according to claim 12, wherein, Arrange at least two square cyclic matrices of size n×n as consecutive cyclic columns on the same row slot of the quasi-cyclic matrix.

14. The system according to claim 13, wherein, The square circular matrix, including consecutive circular columns in the quasi-circular matrix, defines a row path through the quasi-circular matrix, wherein the row path is defined by a row index r associated with each circular matrix in the row path. i Quantify it.

15. The system according to claim 13, wherein, The controller is programmed to perform iterative processing on the cyclic columns in the quasi-cyclic matrix.

16. The system according to claim 15, wherein, The iterative process includes a cyclic shift of row slots in two cyclic size corrector snapshots of the two consecutive cyclic columns.

17. The system according to claim 15, wherein, The controller is programmed to: The bit error rate is determined at the start of the iterative process; and The bit error rate is updated after the entry in the user portion of the LDPC codeword is changed to a bit.

18. The system according to claim 17, wherein, The controller is programmed to generate a corrector after the entry is changed.

19. The system according to claim 11, wherein, The controller is programmed to determine successful decoding of the user portion and the parity portion by calculating the cyclic redundancy check of the parity of the user portion and the parity portion.

20. The system according to claim 19, wherein, The controller is programmed to transmit the corrected data bit information to the host device after successful decoding of the user portion and the parity portion.

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