FPGA-based 8B / 10B encoding and decoding IP core

Abstract

The application discloses an IP core of 8B / 10B encoding and decoding based on FPGA, which is used for interconnection communication between electronic devices on a spacecraft, and the IP core comprises: an encoding unit, which is used for clock matching of a received data packet under the control of a clock, encoding and serial-parallel conversion of control characters and data characters in the data packet according to an encoding rule, and entering a decoding unit; and the decoding unit, which is used for sampling processing of received serial data under the control of the clock, recovery of clock and data signals, synchronization code detection after serial-parallel conversion, decoding of the control characters and the data characters and output, and judgment of data validity and link transmission correctness. The IP core is realized based on logic, has the advantages of high flexibility, simple structure, easy development, high portability and less resource occupation, meets the reliability requirement of data transmission of the space device, and can significantly improve the transmission rate.

Description

Technical Field

[0001] This invention relates to the field of aviation data communication technology, and in particular to an FPGA-based 8B / 10B codec IP core. Background Technology

[0002] Onboard data bus technology is a key technology for realizing onboard information acquisition, transmission, sharing and processing. It is known as the "nerve center" of spacecraft and is an important key and supporting technology for space missions.

[0003] Currently, high-speed data transmission for interconnection between electronic devices on Chinese spacecraft primarily relies on point-to-point serial buses based on RS422 and LVDS levels. Conventional designs use a three-wire system to transmit clock, enable, and data signals separately; a single LVDS signal requires six cables, increasing satellite launch weight and cost. Employing 8B / 10B encoding technology to combine data and clock signals for transmission effectively reduces the number of cables required for high-speed point-to-point data transmission. 8B / 10B encoding effectively overcomes clock and data jitter issues during transmission, improving transmission efficiency. Furthermore, 8B / 10B encoding offers advantages such as DC balance, high conversion density, and redundant error detection, leading to its widespread adoption.

[0004] 8B / 10B encoding technology enables the conversion between 8-bit and 10-bit data. Transmitted data can be divided into two types: data characters and control characters. Data characters indicate that the characters to be transmitted are data information, while control characters indicate that the characters to be transmitted are control information. Control characters have functions such as establishing byte synchronization and indicating the start and end of data packets.

[0005] There are two main methods for implementing 8B / 10B encoding / decoding on FPGA. One is a lookup table-based method, which stores the mapping relationships between all possible data in memory according to encoding rules. When data to be encoded is input, encoding and decoding are performed directly according to the stored mapping relationships. This method is logically simple and easy to develop, but it consumes too much memory resources, increasing system power consumption and limiting system speed. The other method is based on logical relationships, implementing the encoding / decoding mapping relationships using logical operations. This method reduces resource consumption, but the logic is complex and also increases circuit power consumption.

[0006] Clock and Data Recovery (CDR) is the most crucial component of the 8B / 10B decoding module. There are three main CDR topologies: feedback phase tracking-based CDR, feedbackless oversampling-based CDR, and burst-mode-based CDR. Feedback phase tracking-based CDR is not suitable for FPGA design. Oversampling methods can be categorized into two types based on the sampling clock: time-domain oversampling and spatial oversampling. Time-domain oversampling directly uses a clock frequency that is n times the frequency of the transmitted data to oversample the data. In spaceborne 8B / 10B decoding technology based on single-wire LVDS, a 5x frequency oversampling method is mainly used to recover the clock and data. This method severely limits the data transmission rate, restricting it to the FPGA's operating frequency. In practice, the transmission rate of spaceborne single-wire LVDS is generally less than 50Mbps.

[0007] Currently, the implementation of 8B / 10B encoding and decoding for LVDS mainly relies on FPGA-based 8B / 10B encoding / decoding IP cores or external serial / deserialization chips, driver chips, and equalizer chips. The former is subject to copyright restrictions, resulting in drawbacks such as non-portability, opaque code, and high resource consumption, which imposes significant constraints on its application in aerospace missions. The latter requires additional hardware circuitry with multiple chips, increasing circuit board area and cost. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and propose an 8B / 10B encoding and decoding IP core based on FPGA.

[0009] To achieve the above objectives, this invention proposes an FPGA-based 8B / 10B codec IP core for interconnection and communication between electronic devices on spacecraft. The IP core includes:

[0010] The encoding unit is used to perform clock matching on the received data packets under the control of the clock. According to the encoding rules, the control characters and data characters in the data packets are encoded and converted from parallel to serial, and then enter the decoding unit.

[0011] The decoding unit is used to sample the received serial data under the control of the clock, recover the clock and data signals, perform synchronization code detection after serial-to-parallel conversion, decode the control characters and data characters respectively and output them, and determine the validity of the data and the correctness of the link transmission.

[0012] Preferably, the encoding unit includes: a transmitter input interface, a transmitter clock module, an 8B / 10B encoding module, and a parallel-to-serial conversion module, wherein,

[0013] The sending end input interface is used to receive the data packet to be sent, perform clock matching on it, and then send it to the encoding module;

[0014] The transmitting clock module is used to generate a clock based on the input of an external crystal oscillator, and the clock frequency is consistent with the 8B / 10B transmission rate.

[0015] The 8B / 10B encoding module is used to encode control characters and data characters from 8 bits to 10 bits according to the encoding rules;

[0016] The parallel-to-serial conversion module is used to convert parallel signals into serial signals and then output them via the LVDS interface.

[0017] Preferably, the transmitting input interface includes: an AXIS slave interface, a synchronization code input interface, an enable interface, and a reset interface; wherein, the AXIS slave interface receives the data packets to be sent according to the AXIS protocol, achieves timing matching, and transmits them to the 8B / 10B encoding module in the form of synchronization code + data packet bytes; the user can configure the synchronization code, the number of synchronization codes, and the transmission packet length through the configuration register. The transmission packet length is within 1024 bytes, more than 16 synchronization codes are transmitted between data packets, and the synchronization code is sent by default when the bus is idle.

[0018] Preferably, the processing procedure of the 8B / 10B encoding module includes:

[0019] When the character to be encoded is a data character, 5B / 6B encoding is performed first. The 6B encoding output is achieved based on the lower 2 bits of the previous 4B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially. Then, 3B / 4B encoding is performed. The 4B encoding output is achieved based on the lower 3 bits of the current 6B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially.

[0020] When the character to be encoded is a control character, 10B encoding output is achieved according to the input RD polarity state and mapping relationship, with priority decreasing sequentially.

[0021] Preferably, the 8B / 10B encoding module follows the polarity state changing principle and DC balance requirement during encoding, and uses a 2-bit register to record the polarity state, where "00" indicates that the current state is balanced, "01" indicates that the current state is RD-, and "11" indicates that the current state is RD+. When the polarity state changing contradicts the encoding DC balance requirement, the problem of five or more consecutive "0"s or "1"s is resolved first, and this is recorded for polarity compensation in the subsequent encoding process.

[0022] Preferably, the decoding unit includes: a receiver clock module, a clock and data recovery module, a serial-to-parallel conversion module, a synchronization code detection module, a 10B / 8B decoding module, and a receiver output interface, wherein,

[0023] The receiving end clock module is used to generate a four-phase clock with the same frequency based on the input of an external crystal oscillator: 0°, 90°, 180°, and 270°, with the clock frequency consistent with the 8B / 10B transmission rate;

[0024] The clock and data recovery module is used to sample and process the received coded signal to recover the clock and data signals; it is also used to eliminate the cumulative error caused by sampling clock deviation and jitter by repositioning the optimal sampling phase when a control word flag is received from the 10B / 8B decoding module.

[0025] The serial-to-parallel conversion module is used to convert the recovered data signal into a serial-to-parallel signal;

[0026] The synchronization code detection module is used to detect the start of the boundary of the serial-to-parallel converted data signal and perform data alignment.

[0027] The 10B / 8B decoding module is used to receive data packets and decode control characters and data characters from 10 bits to 8 bits according to the decoding rules. It is also used to generate a control word flag at the end of each data packet reception and transmit it to the clock and data recovery module.

[0028] The receiver output interface is used to output the decoded control characters and data characters, and to provide valid and error flag signals, thereby determining the validity of the received data and the correctness of the link transmission.

[0029] Preferably, the processing procedure of the clock and data recovery module specifically includes:

[0030] Based on the same-frequency multi-phase oversampling method, the received data is sampled using a four-phase clock, and the optimal phase is determined by the synchronization code as the recovery clock to recover the data.

[0031] Preferably, a synchronization code detection submodule and a shift submodule are used; wherein,

[0032] The synchronization code detection submodule first stores two sets of 10-bit data, and then checks whether the stored data contains the 10-bit encoding of the synchronization code. If it does, the start of the character boundary is found, the decoding flag register is enabled, the decoding flag bit is made valid, and the data boundary is located.

[0033] The shifting submodule aligns and divides the received data according to the positioning pair to ensure correct data decoding.

[0034] Preferably, the 10B / 8B decoding module performs the following processing when the decoding flag is valid:

[0035] Step 1) Determine if the high 6 bits of the data to be decoded are "001111" or "110000". If yes, the data is a control character. After decoding the control character, proceed to step 4); otherwise, proceed to step 2).

[0036] Step 2) Determine if the lower 4 bits of the data to be decoded are "1000" or "0111". If yes, proceed to step 3); otherwise, the data is a data character. After decoding the data character, proceed to step 4.

[0037] Step 3) Determine whether the high 6 bits of the data to be decoded are "111010", "110110", "101110", "011110", "000101", "001001", "010001", or "100001". If yes, the data is a control character. After decoding the control character, proceed to step 4). Otherwise, the data is a data character. After decoding the data character, proceed to step 4).

[0038] Step 4) Output decoding, end.

[0039] Preferred,

[0040] The output of the receiving end output interface includes: output decoded bytes, control character decoding error flag, data character decoding error flag, character valid flag, control word flag, and data word flag; wherein...

[0041] The control character decoding error flag and the data character decoding error flag are used to determine whether the link transmission is normal; the control word flag or data word flag and the character validity flag are used to determine whether the data is valid.

[0042] Compared with the prior art, the advantages of the present invention are:

[0043] 1. The FPGA-based 8B / 10B codec IP core of the present invention is implemented in logic, with the lookup table stored in the Verilog source file. It has low resource consumption, high portability, and can be ported to FPGA, ASIC or SOC chips.

[0044] 2. The FPGA-based 8B / 10B codec IP core interface design of the present invention is reasonable. The clock, synchronization code and other configurations can be changed according to requirements, which has the advantage of high flexibility and meets the reliability requirements of data transmission in aerospace equipment.

[0045] 3. The FPGA-based 8B / 10B codec IP core of the present invention is implemented in a modular manner, with high cohesion and low coupling between modules, and has the characteristics of simple structure and easy development;

[0046] 4. The FPGA-based 8B / 10B codec IP core of the present invention uses a four-phase sampling method to realize clock and data recovery, and uses synchronization code to update the optimal phase in real time, so that the transmission rate is not limited by the FPGA operating frequency. Compared with the frequency oversampling method, the transmission rate can be significantly improved. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the FPGA-based 8B / 10B codec IP core of the present invention;

[0048] Figure 2 This is a schematic diagram of the functional module connection of the IP core encoding unit of the FPGA-based 8B / 10B encoding and decoding system of the present invention.

[0049] Figure 3 This is a schematic diagram of the functional module connection of the FPGA-based 8B / 10B codec IP core decoding unit of the present invention;

[0050] Figure 4 This is a schematic diagram of the input interface state machine of the FPGA-based 8B / 10B codec IP core of the present invention;

[0051] Figure 5 This is a schematic diagram of the clock and data recovery module of the FPGA-based 8B / 10B codec IP core of the present invention;

[0052] Figure 6 This is a schematic diagram of the channel selection process of the 10B / 8B decoding unit of the FPGA-based 8B / 10B encoding and decoding IP core of the present invention. Detailed Implementation

[0053] This invention proposes an FPGA-based 8B / 10B encoding / decoding IP core for interconnection and communication between electronic devices on spacecraft. The IP core includes an encoding unit and a decoding unit.

[0054] 1) Encoding unit, used to perform clock matching on the received data packets under the control of the clock, and to encode and convert the control characters and data characters in the data packets according to the encoding rules before entering the decoding unit;

[0055] The encoding unit includes: a transmitter input interface, a transmitter clock module, an 8B / 10B encoding module, and a parallel-to-serial conversion module.

[0056] The sending end input interface is used to receive the data packet to be sent, perform clock matching on it, and then send it to the encoding module;

[0057] The transmitting clock module is used to generate a clock based on the input of an external crystal oscillator, and the clock frequency is consistent with the 8B / 10B transmission rate.

[0058] The 8B / 10B encoding module is used to encode control characters and data characters from 8 bits to 10 bits according to the encoding rules;

[0059] The parallel-to-serial conversion module is used to convert parallel signals into serial signals and then output them via the LVDS interface.

[0060] Preferably, the transmitting input interface includes: an AXIS slave interface, a synchronization code input interface, an enable interface, and a reset interface; wherein, the AXIS slave interface receives the data packets to be sent according to the AXIS protocol, achieves timing matching, and transmits them to the 8B / 10B encoding module in the form of synchronization code + data packet bytes; the user can configure the synchronization code, the number of synchronization codes, and the transmission packet length through the configuration register. The transmission packet length is within 1024 bytes, more than 16 synchronization codes are transmitted between data packets, and the synchronization code is sent by default when the bus is idle.

[0061] The decoding unit includes: a receiver clock module, a clock and data recovery module, a serial-to-parallel conversion module, a synchronization code detection module, a 10B / 8B decoding module, and a receiver output interface.

[0062] The receiving end clock module is used to generate a four-phase clock with the same frequency based on the input of an external crystal oscillator: 0°, 90°, 180°, and 270°, with the clock frequency consistent with the 8B / 10B transmission rate;

[0063] The clock and data recovery module is used to sample and process the received coded signal to recover the clock and data signals.

[0064] The serial-to-parallel conversion module is used to convert the recovered data signal into a serial-to-parallel signal;

[0065] The synchronization code detection module is used to detect the start of the boundary of the serial-to-parallel converted data signal and perform data alignment.

[0066] The 10B / 8B decoding module is used to decode control characters and data characters according to the decoding rules. At the end of each data packet reception, the optimal sampling phase is repositioned to eliminate the cumulative error caused by sampling clock deviation and jitter.

[0067] The receiver output interface is used to output the decoded control characters and data characters, and to provide valid and error flag signals, thereby determining the validity of the received data and the correctness of the link transmission. The output of the receiver output interface includes: output decoded bytes, control character decoding error flags, data character decoding error flags, character valid flags, and control word / data word flags; wherein,

[0068] The control character decoding error flag and the data character decoding error flag are used to determine whether the link transmission is normal; the character validity flag and the control word / data word flag are used to determine whether the data is valid.

[0069] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0070] Example

[0071] like Figure 1 As shown, an FPGA-based 8B / 10B encoding / decoding IP core includes a transmitter input interface (1), a transmitter clock module (2), an 8B / 10B encoding module (3), a parallel-to-serial conversion module (4), a receiver clock module (5), a clock and data recovery module (6), a serial-to-parallel conversion module (7), a synchronization code detection module (8), a 10B / 8B decoding module (9), and a receiver output interface (10); wherein,

[0072] The transmitting end input interface (1) is connected to the 8B / 10B encoding module (3), the transmitting end clock module (2) is connected to the 8B / 10B encoding module (3) and the parallel-to-serial conversion module (4), and the 8B / 10B encoding module (3) is connected to the parallel-to-serial conversion module (4); the receiving end clock module (5) is connected to the clock and data recovery module (6), the serial-to-parallel conversion module (7), the synchronization code detection module (8), and the 10B / 8B decoding module (9), and the clock and data recovery module (6) is connected to the serial-to-parallel conversion module (7), then to the synchronization code detection module (8), then to the 10B / 8B decoding module (9), and then to the receiving end output interface (10), and the 10B / 8B decoding module (9) is connected to the clock and data recovery module (6).

[0073] like Figure 2 As shown, the encoding section of an FPGA-based 8B / 10B codec IP core includes four functional units: a transmitter input interface, a transmitter clock module, an 8B / 10B encoding module, and a parallel-to-serial conversion module. Their functions are as follows:

[0074] 1. The transmitting clock module uses the FPGA's clock management unit to generate a single-phase clock for other functional modules, and the generated locked latch signal is used to reset other functional modules.

[0075] 2. Data packets to be sent enter the encoding section from the input interface in byte-by-byte units. The input interface uses a state machine to convert them into timing-matched bytes to be encoded for output. Its state bubble diagram is shown below. Figure 4 As shown, the steps are as follows:

[0076] Step 1: Enter the initial state of state machine s0, send a set of synchronization codes, and disable the axi_ready signal;

[0077] Step 2: Enter the s1 waiting state and count 9 clock cycles;

[0078] Step 3: Repeat steps 1 and 2 to send the predetermined number of synchronization codes;

[0079] Step 4: Enter state machine s2 to read the state. When the axi_valid signal is valid, the axi_ready signal is enabled, and one byte of data packet is received.

[0080] Step 5: Enter the S1 waiting state, count 9 clock cycles, and disable the axi_ready signal;

[0081] Step 6: Repeat steps 4 and 5 until the data packet content is completely read. At this point, the axi_last signal is enabled.

[0082] Step 7: Enter the s3 termination state of the state machine.

[0083] 3. Input interface settings include the synchronization code register K_reg, synchronization code length register K_length, and packet length register D_length; the default synchronization code is K28.5; K_length defaults to 16, with a value ranging from 16 to 255; D_length defaults to 1024, with a value ranging from 1 to 16383. Users can configure these settings according to the frame structure and transmission requirements.

[0084] 4. After the data to be encoded enters the encoding module, the channel is selected based on the signal tk to determine whether it enters d_encoder.

[0085]

[0086] 5. If the character to be encoded is a data character, first perform 5B / 6B encoding, and then implement 6B encoding output based on the lower 2 bits of the previous byte's 4B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially; then perform 3B / 4B encoding, and implement 4B encoding output based on the lower 3 bits of the current byte's 6B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially.

[0087] 6. If the character to be encoded is a control character, 10B encoding output is achieved according to the input RD polarity state and mapping relationship, with priority decreasing sequentially.

[0088] 7. The parallel-to-serial conversion module uses a counter and logical right shift to output the low-order bits of 10B data sequentially, with the interface being de_data.

[0089] like Figure 3 As shown, the decoding section of an FPGA-based 8B / 10B codec IP core includes six functional units: a receiver clock module, a clock and data recovery module, a serial-to-parallel conversion module, a synchronization code detection module, a 10B / 8B decoding module, and a receiver output interface. Their functions are as follows:

[0090] 1. The receiving clock module uses the FPGA's clock management unit to generate a four-phase clock at the same frequency: 0°, 90°, 180°, and 270°. The four-phase clock is used for the CDR module, while other functional modules only use the 0° clock. The generated locked latch signal is used to reset all functional modules.

[0091] 2. The CDR module uses four clock channels to sample the single-ended received signal four times within one symbol cycle, recording the sampling results in registers a, b, c, and d. At the rising edge of the clock at the 0° phase of the next cycle, the four sampling results are recorded in register data_reg[3:0]. Then, data_reg_w[7:0] stores the eight sampling results from the current and previous cycles. The sampling results are as follows: Figure 5 As shown, the optimal phase is determined by the sampling results to recover the data. Theoretically, the optimal phase for data recovery remains unchanged. However, due to clock deviations and jitter, the optimal sampling phase changes. The optimal phase is then re-detected using a synchronization code to eliminate accumulated errors. The principle for detecting the optimal phase is as follows:

[0092] When the system is in its initial state after reset, the clock signal is locked and no cumulative error has occurred. Based on the sampled data stored in data_reg_w[7:0], the data edge can be directly determined, and the optimal phase and recovered data are provided. Then, when the decoder_8b10b module continuously detects the synchronization code, the optimal phase is updated. At this time, the rk_flag signal is enabled, rk_flag_cnt starts counting, and the cdr module enters the state machine for detecting the optimal sampling position. Based on the sampled value, the current optimal sampling position is determined, and the corresponding clock sampled value is selected for serial-to-parallel conversion. Adjusting the optimal sampling position requires 2 bytes of time; therefore, the synchronization code used for positioning needs to be greater than 2 bytes.

[0093] 3. The serial-to-parallel conversion module uses a counter and logical left shift to output 10-bit signals in parallel. For each set of parallel signals output, the valid signal enables the signal for one clock cycle.

[0094] 4. The synchronization code detection module first stores two sets of 10-bit data, and then enters the synchronization code detection unit to check whether the 20-bit data stored contains the 10-bit encoding of the synchronization code. If it does, the start of the character boundary is found, the enable decoding flag register is updated and this position is used for positioning, and the shift unit aligns and divides the subsequently received data according to this positioning before outputting it.

[0095] 5. After the data to be decoded enters the decoder_8b10b module, the channel selection process begins when the decoding enable flag is activated. The decision process is as follows: Figure 6 As shown, the judgment method is as follows:

[0096] Step 1: Check if the high 6 bits are "001111" or "110000". If so, it is a control character and enters the k_decoder unit; otherwise, proceed to Step 2.

[0097] Step 2: Check if the lower 4 bits are "1000" or "0111". If not, it is a data character and enters the d_decoder unit. If it is, proceed to Step 3.

[0098] Step 3: Check if the high 6 bits of the data are "111010", "110110", "101110", "011110", "000101", "001001", "010001", or "100001". If so, it is a control character and enters the k_decoder unit; otherwise, it is a data character and enters the d_decoder unit.

[0099] 6. During decoding, valid character flags and error flags are generated and output to the host computer via the output interface. The user layer can monitor the error status at any time to ensure the reliability of data transmission. If an error status is indicated, measures such as resetting, retransmission, or adjusting the frame structure can be taken.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An FPGA-based 8B / 10B codec IP core for interconnection and communication between electronic devices on a spacecraft, characterized in that, The IP core includes: The encoding unit is used to perform clock matching on the received data packets under the control of the clock. According to the encoding rules, the control characters and data characters in the data packets are encoded and converted from parallel to serial, and then enter the decoding unit. The decoding unit, under clock control, samples the received serial data, recovers the clock and data signals, performs synchronization code detection after serial-to-parallel conversion, decodes control characters and data characters respectively, and outputs the results. It also determines data validity and link transmission correctness. The decoding unit includes: a receiver clock module, a clock and data recovery module, a serial-to-parallel conversion module, a synchronization code detection module, a 10B / 8B decoding module, and a receiver output interface. The receiving end clock module is used to generate a four-phase clock with the same frequency based on the input of an external crystal oscillator: 0°, 90°, 180°, and 270°, with the clock frequency consistent with the 8B / 10B transmission rate; The clock and data recovery module is used to sample and process the received coded signal to recover the clock and data signals; it is also used to eliminate the cumulative error caused by sampling clock deviation and jitter by repositioning the optimal sampling phase when a control word flag is received from the 10B / 8B decoding module. The serial-to-parallel conversion module is used to convert the recovered data signal into a serial-to-parallel signal; The synchronization code detection module is used to detect the start of the boundary of the serial-to-parallel converted data signal and to perform data alignment. The 10B / 8B decoding module is used to receive data packets and decode control characters and data characters from 10 bits to 8 bits according to the decoding rules. It is also used to generate a control word flag at the end of each data packet reception and transmit it to the clock and data recovery module. The receiver output interface is used to output the decoded control characters and data characters, and to provide valid and error flag signals, thereby determining the validity of the received data and the correctness of the link transmission. The processing procedure of the clock and data recovery module specifically includes: Based on the same-frequency multi-phase oversampling method, the received data is sampled using a four-phase clock, and the optimal phase is determined by the synchronization code as the recovery clock to recover the data. The synchronization code detection module includes a synchronization code detection submodule and a shift submodule; wherein... The synchronization code detection submodule first stores two sets of 10-bit data, and then checks whether the stored data contains the 10-bit encoding of the synchronization code. If it does, the start of the character boundary is found, the decoding flag register is enabled, the decoding flag bit is made valid, and the data boundary is located. The shifting submodule aligns and divides the received data according to the positioning pair to ensure correct data decoding.

2. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 1, characterized in that, The encoding unit includes: a transmitter input interface, a transmitter clock module, an 8B / 10B encoding module, and a parallel-to-serial conversion module, wherein... The sending end input interface is used to receive the data packet to be sent, perform clock matching on it, and then send it to the encoding module; The transmitting clock module is used to generate a clock based on the input of an external crystal oscillator, and the clock frequency is consistent with the 8B / 10B transmission rate. The 8B / 10B encoding module is used to encode control characters and data characters from 8 bits to 10 bits according to the encoding rules; The parallel-to-serial conversion module is used to convert parallel signals into serial signals and then output them via the LVDS interface.

3. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 2, characterized in that, The transmitting input interface includes: an AXIS slave interface, a synchronization code input interface, an enable interface, and a reset interface. The AXIS slave interface receives data packets to be transmitted according to the AXIS protocol, achieves timing matching, and transmits them to the 8B / 10B encoding module in the form of synchronization code + data packet bytes. The user can configure the synchronization code, the number of synchronization codes, and the transmission packet length through the configuration register. The transmission packet length is within 1024 bytes, and more than 16 synchronization codes are transmitted between data packets. Synchronization codes are sent by default when the bus is idle.

4. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 2, characterized in that, The processing procedure of the 8B / 10B encoding module includes: When the character to be encoded is a data character, 5B / 6B encoding is performed first. The 6B encoding output is achieved based on the lower 2 bits of the previous 4B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially. Then, 3B / 4B encoding is performed. The 4B encoding output is achieved based on the lower 3 bits of the current 6B encoding, the input RD polarity state, and the mapping relationship, with the priority decreasing sequentially. When the character to be encoded is a control character, 10B encoding output is achieved according to the input RD polarity state and mapping relationship, with priority decreasing sequentially.

5. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 2, characterized in that, The 8B / 10B encoding module follows the principle of polarity state changing and DC balance requirements during encoding. It uses a 2-bit register to record the polarity state, where "00" indicates that the current state is balanced, "01" indicates that the current state is RD-, and "11" indicates that the current state is RD+. When the polarity state changing contradicts the encoding DC balance requirements, the problem of five or more consecutive "0"s or "1"s is resolved first and recorded. Polarity compensation is then performed in the subsequent encoding process.

6. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 1, characterized in that, When the decoding flag is valid, the 10B / 8B decoding module performs the following processing: Step 1) Determine if the high 6 bits of the data to be decoded are "001111" or "110000". If yes, the data is a control character. After decoding the control character, proceed to step 4. Otherwise, proceed to step 2. Step 2) Determine if the lower 4 bits of the data to be decoded are "1000" or "0111". If yes, proceed to Step 3; otherwise, the data is a data character. After decoding the data character, proceed to Step 4. Step 3) Determine if the high 6 bits of the data to be decoded are "111010", "110110", "101110", "011110", "000101", "001001", "010001", or "100001". If yes, the data is a control character, and after decoding the control character, proceed to step 4). Otherwise, the data is a data character, and after decoding the data character, proceed to step 4). Step 4) Output the decoded output and end.

7. The FPGA-based 8B / 10B encoding / decoding IP core according to claim 1, characterized in that, The output of the receiving end output interface includes: output decoded bytes, control character decoding error flag, data character decoding error flag, character valid flag, control word flag, and data word flag; wherein... The control character decoding error flag and the data character decoding error flag are used to determine whether the link transmission is normal; the control word flag or data word flag and the character validity flag are used to determine whether the data is valid.

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