Pre-silicon verification circuit, method, apparatus, and medium
By adding delay units and two-stage synchronizers in the pre-EDA simulation stage, and adjusting the delay units to enable them sequentially, the potential asynchronous problem in signal transmission across clock domains was solved, enabling early detection and resolution of asynchronous problems and avoiding project delays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KTMICRO ELECTRONICS
- Filing Date
- 2023-07-27
- Publication Date
- 2026-07-14
AI Technical Summary
Existing technologies struggle to effectively detect potential asynchronous issues when signals are transmitted across clock domains, leading to delays caused by the discovery of asynchronous problems at the end of the project.
In the pre-EDA simulation stage, by adding delay units and two-stage synchronizers, and adjusting the delay units to enable them sequentially, the post-EDA simulation behavior is simulated to discover potential asynchronous problems.
Identifying and resolving asynchronous issues early in the project prevented delays at the end of the project, thus improving the reliability and efficiency of the design.
Smart Images
Figure CN116956784B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a verification circuit, method, device and medium based on pre-simulation. Background Technology
[0002] When a signal is transmitted from one clock domain to another asynchronous clock domain, metastability may occur. Metastability not only leads to logical misjudgments, but when it propagates to subsequent combinational logic circuits, it can cascade down, causing the entire system to malfunction. In existing technologies, the CDC (Clock Domain Crossing) method can use the TCL (Tool Command Language) scripting language and analysis tools to identify all asynchronous paths in the entire design, allowing designers to analyze and check whether all asynchronous paths have been synchronized. However, this offers little help to verification personnel, who still need to verify the correctness of the synchronization processing. For some potentially difficult-to-detect asynchronous problems, even if synchronization has been implemented during the design phase, issues may still exist in the actual chip. Summary of the Invention
[0003] In view of this, the present invention provides a verification circuit, method, device, and medium based on pre-simulation. Addressing asynchronous paths in the system, it simulates post-EDA simulation behavior by adjusting timing paths during the pre-simulation stage of EDA (Electronic Design Automation), thereby uncovering potential asynchronous problems in the asynchronous processing process. This allows for resolution early in the project, avoiding project delays caused by discovering asynchronous problems at the end. The present invention provides the following technical solution:
[0004] In a first aspect, the present invention proposes a verification circuit based on pre-simulation, including a judgment module and at least one verification sub-circuit;
[0005] Each of the verification sub-circuits includes a first flip-flop, a delay unit, and a two-stage synchronizer connected in sequence;
[0006] Each of the first flip-flops is provided with a first clock by a first clock domain, and each of the two-stage synchronizers is provided with a second clock by a second clock domain. The first clock and the second clock have different frequencies or phases.
[0007] The cross-clock domain signal includes at least one cross-clock domain sub-signal. The verification sub-circuit is used to allow each cross-clock domain sub-signal to flow sequentially through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal.
[0008] The judgment module is used to determine whether the sequential insertion of delays into all cross-clock domain sub-signals meets the preset functional requirements. If it does, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
[0009] In one embodiment, when the cross-clock domain signal includes M cross-clock domain sub-signals and the number of verification sub-circuits is M, where M≥2, an M-round delay processing flow is executed. The i-th round delay processing flow is as follows: the delay unit of the i-th verification sub-circuit performs delay processing on the i-th cross-clock domain sub-signal, and after the two-stage synchronizer of the i-th verification sub-circuit performs synchronization processing, a first synchronization signal is obtained.
[0010] The delay unit of the j-th verification sub-circuit delays the j-th cross-clock domain sub-signal. After the two-stage synchronizer of the j-th verification sub-circuit performs synchronization processing, the second synchronization signal is obtained, j≠i, and j∈[1,M].
[0011] In one embodiment, when M≥2, the first synchronization signal and the second synchronization signal of the i-th round are used as the i-th group of synchronization signals;
[0012] Determine whether all M groups of synchronization signals meet the preset functional requirements. If they do, then there is no asynchronous problem; otherwise, there is an asynchronous problem.
[0013] In one embodiment, each of the two-stage synchronizers includes a second flip-flop and a third flip-flop; the second flip-flop is electrically connected to the corresponding delay unit and the third flip-flop, respectively.
[0014] In one embodiment, the first trigger receives and latches the cross-clock domain sub-signal; the first trigger outputs the cross-clock domain sub-signal to the delay unit; the delay unit sets the delay of the cross-clock domain sub-signal and outputs it to the two-stage synchronizer; the two-stage synchronizer receives the cross-clock domain sub-signal, performs synchronization processing on the cross-clock domain sub-signal, and outputs a synchronization signal.
[0015] In one embodiment, the preset functional requirement is the requirement for the combinational logic circuit to function normally according to its design function.
[0016] Secondly, the present invention proposes a verification method based on pre-simulation, the method comprising: inputting a cross-clock domain signal, the cross-clock domain signal comprising at least one cross-clock domain sub-signal, each of the cross-clock domain sub-signals sequentially flowing through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal;
[0017] Determine whether the sequential insertion of delays into all cross-clock domain sub-signals meets the preset functional requirements. If it does, then there is no asynchronous problem; otherwise, there is an asynchronous problem.
[0018] In one embodiment, when the cross-clock domain signal includes M cross-clock domain sub-signals, M≥2, each of the cross-clock domain sub-signals flows sequentially through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal, including: executing M rounds of delay processing, wherein the i-th round of delay processing is: after delay processing and synchronization processing of the i-th cross-clock domain sub-signal, a first synchronization signal is obtained;
[0019] After delaying and synchronizing the j-th cross-clock domain sub-signal, the second synchronization signal is obtained, where j ≠ i and j ∈ [1, M].
[0020] Thirdly, the present invention proposes an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the computer program executes the pre-simulation-based verification method described in Embodiment 2 of the present invention when it is run on the processor.
[0021] Fourthly, the present invention proposes a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the pre-simulation-based verification method described in Embodiment 2 of the present invention.
[0022] The present invention discloses a verification circuit, method, device, and medium based on pre-simulation. By adding delay units at the front end of a two-stage synchronizer and adjusting the delay units so that each delay unit is enabled in turn, the pre-simulation stage of EDA can be used to simulate the post-simulation behavior of EDA. This allows asynchronous problems to be reproduced in the pre-simulation stage, and potential asynchronous problems in the asynchronous processing process can be discovered so that they can be solved in the early stage of the project, avoiding the delay caused by the discovery of asynchronous problems at the end of the project.
[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A schematic diagram of a pre-simulation-based verification circuit provided in an embodiment of this application is shown.
[0026] Figure 2A flowchart illustrating a pre-simulation-based verification method provided in an embodiment of this application is shown.
[0027] Figure 3 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.
[0028] Explanation of key component symbols:
[0029] 100 - Verification circuit based on pre-simulation; 101 - Verification sub-circuit; 1011 - First flip-flop; 1012 - Delay unit; 1013 - Two-stage synchronizer; 102 - Judgment module; 300 - Electronic device; 301 - Transceiver; 302 - Processor; 303 - Memory. Detailed Implementation
[0030] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0031] It should be noted that when an element is said to be "fixed" to another element, it can be directly on the other element or there may be an intervening element. When an element is said to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is said to be "directly" on another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.
[0032] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the template description is for the purpose of describing particular embodiments only and is not intended to limit the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0035] Example 1
[0036] This application provides a verification circuit based on pre-simulation. For details, please refer to... Figure 1 .
[0037] The pre-simulation-based verification circuit 100 includes a judgment module 102 and at least one verification sub-circuit 101. Each verification sub-circuit 101 includes a first flip-flop 1011, a delay unit 1012, and a two-stage synchronizer 1013 connected in sequence. Each first flip-flop 1011 is provided with a first clock by a first clock domain, and each two-stage synchronizer 1013 is provided with a second clock by a second clock domain. The first clock and the second clock have different frequencies or phases. The cross-clock domain signal includes at least one cross-clock domain sub-signal. The verification sub-circuit 101 is used to allow each cross-clock domain sub-signal to flow sequentially through the first flip-flop 1011, the delay unit 1012, and the two-stage synchronizer 1013 corresponding to the verification sub-circuit 101 to obtain a synchronization signal. The judgment module 102 is used to judge whether all cross-clock domain sub-signals, after being sequentially inserted with delays, meet the preset functional requirements. If they do, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
[0038] In this embodiment, the first trigger 1011 is used to receive, store and transmit cross-clock domain sub-signals; the delay unit 1012 is used to delay the cross-clock domain sub-signals; and the two-stage synchronizer 1013 is used to synchronize the cross-clock domain sub-signals to eliminate metastability.
[0039] It's important to note that metastability refers to a flip-flop's inability to reach a definite state within a specified time period. When a signal is transmitted from the first clock domain to the second clock domain, it needs to pass through one or more cascaded flip-flops for synchronization. During this transmission, if the signal changes near the second clock sampling point, and the duration of this change does not meet the setup and / or hold times of the subsequent flip-flops (i.e., within the second clock domain), the subsequent flip-flops will be in an unstable state. In this unstable state, the output value of the flip-flop will continuously change over a period of time before stabilizing. When the metastable signal propagates to subsequent combinational logic circuits, it will cause a cascading effect, leading to the entire system malfunctioning. For example, a cross-clock domain signal 0, after experiencing metastability and reaching stability, has a stable value of 1. This erroneous signal, when transmitted to subsequent combinational logic circuits, may cause asynchronous problems, resulting in the entire circuit malfunctioning. To solve the metastability problem, two stages of synchronizers 1013 are typically used in the second clock domain to eliminate metastability.
[0040] Furthermore, in the chip verification process, the pre-EDA simulation stage mainly performs functional verification, while the post-EDA simulation stage mainly performs timing verification. Metastability issues are difficult to detect in the pre-EDA simulation stage. Therefore, in this embodiment, a delay unit 1012 is added during the transmission of each cross-clock domain sub-signal. By adjusting each delay unit 1012, each delay unit 1012 is enabled sequentially, adjusting the timing path of each cross-clock domain sub-signal, thereby simulating the post-EDA simulation behavior to discover potential asynchronous issues. The specific process of discovering potential asynchronous issues is described below.
[0041] In one embodiment, when the cross-clock domain signal includes M cross-clock domain sub-signals and the number of verification sub-circuits 101 is M, where M≥2, an M-round delay processing procedure is executed. The i-th round delay processing procedure is as follows: the delay unit 1012 of the i-th verification sub-circuit 101 performs delay processing on the i-th cross-clock domain sub-signal, and after the two-stage synchronizer 1013 of the i-th verification sub-circuit 101 performs synchronization processing, a first synchronization signal is obtained; the delay unit 1012 of the j-th verification sub-circuit 101 performs delay processing on the j-th cross-clock domain sub-signal, and after the two-stage synchronizer 1013 of the j-th verification sub-circuit 101 performs synchronization processing, a second synchronization signal is obtained, where j≠i and j∈[1,M].
[0042] In this embodiment, when the cross-clock domain signal includes multiple cross-clock domain sub-signals, for example, when two cross-clock domain sub-signals Sigal_1 and Signal_2 are transmitted from the first clock domain to the second clock domain, Signal_1 flows sequentially through the first flip-flop 1011, the delay unit 1012, and the two-stage synchronizer 1013 in the first verification sub-circuit 101, and Signal_2 flows sequentially through the first flip-flop 1011, the delay unit 1012, and the two-stage synchronizer 1013 in the second verification sub-circuit 101. The delay unit 1012 in the first and second verification sub-circuit 101 is adjusted so that the time when Signal_1 and Signal_2 are transmitted to their respective two-stage synchronizers 1013 is a fixed phase difference, that is, one arrives first and the other arrives later; firstly The delay unit 1012 is adjusted so that Signal_1 arrives first at its corresponding two-stage synchronizer 1013 and, after synchronization processing by the two-stage synchronizer 1013, obtains the first synchronization signal. Signal_2 arrives later at its corresponding two-stage synchronizer 1013 and, after synchronization processing by the two-stage synchronizer 1013, obtains the second synchronization signal. The first and second synchronization signals form the first set of synchronization signals. The delay unit 1012 is then adjusted again so that Signal_2 arrives first at its corresponding two-stage synchronizer 1013 and, after synchronization processing by the two-stage synchronizer 1013, obtains the first synchronization signal. Signal_1 arrives later at its corresponding two-stage synchronizer 1013 and, after synchronization processing by the two-stage synchronizer 1013, obtains the second synchronization signal. The first and second synchronization signals form the second set of synchronization signals. The judgment module 102 sequentially judges whether the preset functional requirements are met based on the first and second sets of synchronization signals.
[0043] This method can be extended to cases involving multiple cross-clock domain sub-signals. By adjusting the delay unit 1012, each delay unit 1012 can be enabled in turn to obtain multiple sets of synchronization signals. The judgment module 102 can then make judgments based on the multiple sets of synchronization signals in turn.
[0044] In one embodiment, when M≥2, the first synchronization signal and the second synchronization signal of the i-th round are taken as the i-th group of synchronization signals; it is determined whether all M groups of synchronization signals meet the preset functional requirements. If they do, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
[0045] The preset functional requirement is that multiple synchronization signals enable subsequent combinational logic circuits to function normally according to the design intent. For example, when there are two cross-clock domain sub-signals Sigal_1 and Signal_2, after processing by their respective synchronizers, two synchronization signals Signal_11 and Signal_21 are obtained. According to the design intent, setting Signal_11 to 1 in the input judgment module 102 will enable the subsequent combinational logic circuits to function normally according to the design intent. If the two sets of synchronization signals obtained after adjusting the delay unit 1012 both satisfy the preset condition of setting Signal_11 to 1 as determined by the judgment module 102, that is, both sets of synchronization signals satisfy the preset functional requirement, it can be determined that there will be no asynchronous problem during the transmission of Signal_1 and Signal_2 signals from the first clock domain to the second clock domain. Conversely, if any set of synchronization signals does not meet the preset functional requirement, it can be determined that there will be an asynchronous problem during the transmission of Signal_1 and Signal_2 signals from the first clock domain to the second clock domain.
[0046] In one embodiment, each of the two-stage synchronizers 1013 includes a second flip-flop and a third flip-flop; the second flip-flop is electrically connected to the corresponding delay unit 1012 and the third flip-flop, respectively.
[0047] In this embodiment, the first terminal of the second trigger is electrically connected to the delay unit 1012, the second terminal is electrically connected to the first terminal of the third trigger, and the second terminal of the third trigger is electrically connected to the judgment module 102.
[0048] The first flip-flop 1011 is provided with a first flip-flop 1011 input terminal, a first flip-flop 1011 output terminal, and a first flip-flop 1011 clock terminal; the second flip-flop is provided with a second flip-flop input terminal, a second flip-flop output terminal, and a second flip-flop clock terminal; the third flip-flop is provided with a third flip-flop input terminal, a third flip-flop output terminal, and a third flip-flop clock terminal.
[0049] The signal output terminal of the first flip-flop 1011 is connected to the signal input terminal of the second flip-flop, and the signal output terminal of the second flip-flop is connected to the signal input terminal of the third flip-flop. The clock in the first clock domain provides the first clock to the first flip-flop 1011 through the clock terminal of the first flip-flop 1011, and the clock in the second clock domain provides the second clock to the second flip-flop and the third flip-flop through the clock terminals of the second flip-flop and the third flip-flop, respectively.
[0050] In one embodiment, the first trigger 1011 receives and latches the cross-clock domain sub-signal; the first trigger 1011 outputs the cross-clock domain sub-signal to the delay unit 1012; the delay unit 1012 sets the delay of the cross-clock domain sub-signal and outputs it to the two-stage synchronizer 1013; the two-stage synchronizer 1013 receives the cross-clock domain sub-signal, performs synchronization processing on the cross-clock domain sub-signal, and outputs a synchronization signal.
[0051] In this embodiment, when the clock signal edge arrives, the trigger reads and latches the current input cross-clock domain sub-signal value and outputs the signal.
[0052] In one embodiment, the preset functional requirement is the requirement for the combinational logic circuit to function normally according to its design function.
[0053] In this embodiment, the preset function is the function implemented according to the design intent. In order for the subsequent combinational logic circuit to implement this function, a logic signal needs to be input. If the synchronization signal obtained after the cross-clock domain sub-signal is processed meets the requirements of the input signal of the subsequent combinational logic circuit, then the preset function requirement is met.
[0054] After synchronization processing, multiple cross-clock domain sub-signals are input to the judgment module 102. When the judgment signal in the judgment module 102 is set to 1, if the multiple cross-clock domain sub-signals within the corresponding time period meet the requirements of the input signals of the subsequent combinational logic circuit, it can be determined that there is no asynchronous problem in the cross-clock domain signal transmission process. If the multiple cross-clock domain sub-signals within the corresponding time period do not meet the requirements of the input signals of the subsequent combinational logic circuit, it can be determined that there is an asynchronous problem in the cross-clock domain signal transmission process.
[0055] The pre-simulation verification circuit provided in this embodiment of the invention includes a judgment module and at least one verification sub-circuit. Each verification sub-circuit includes a first flip-flop, a delay unit, and a two-stage synchronizer connected in sequence. Each first flip-flop receives a first clock from a first clock domain, and each two-stage synchronizer receives a second clock from a second clock domain. The first clock and the second clock have different frequencies or phases. The cross-clock domain signal includes at least one cross-clock domain sub-signal. The verification sub-circuit is used to ensure that each cross-clock domain sub-signal flows sequentially through the first flip-flop, delay unit, and two-stage synchronizer of the corresponding verification sub-circuit to obtain a synchronization signal. The judgment module is used to determine whether all cross-clock domain sub-signals, after being sequentially inserted with delays, meet the preset functional requirements. If they do, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem. In this embodiment of the invention, by adding a delay unit at the front end of the two-stage synchronizer and adjusting the delay unit so that each delay unit is enabled sequentially, the behavior of EDA post-simulation is simulated in the EDA pre-simulation stage. This reproduces asynchronous problems in the pre-simulation stage, uncovers potential asynchronous problems in the asynchronous processing process, and facilitates their resolution in the early stages of the project, avoiding project delays caused by discovering asynchronous problems only at the end of the project.
[0056] Example 2
[0057] Furthermore, this application provides a pre-simulation-based verification method, which is applied to the pre-simulation-based verification circuit 100 provided in Embodiment 1.
[0058] For details, please see Figure 2 The pre-simulation-based verification method includes:
[0059] Step S201: Input a cross-clock domain signal, which includes at least one cross-clock domain sub-signal. Each cross-clock domain sub-signal flows sequentially through the first flip-flop 1011, the delay unit 1012, and the two-stage synchronizer 1013 corresponding to the verification sub-circuit 101 to obtain a synchronization signal.
[0060] In one embodiment, when the cross-clock domain signal includes M cross-clock domain sub-signals, M≥2, each cross-clock domain sub-signal sequentially flows through the first flip-flop 1011, the delay unit 1012, and the two-stage synchronizer 1013 corresponding to the verification sub-circuit 101 to obtain a synchronization signal, including: executing M rounds of delay processing, wherein the i-th round of delay processing is: after delay processing and synchronization processing of the i-th cross-clock domain sub-signal, a first synchronization signal is obtained; after delay processing and synchronization processing of the j-th cross-clock domain sub-signal, a second synchronization signal is obtained, j≠i, and j∈[1,M].
[0061] Step S202: Determine whether all cross-clock domain sub-signals that are sequentially inserted with delays meet the preset functional requirements. If they do, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
[0062] It should be noted that the pre-simulation-based verification method is applied to the pre-simulation-based verification circuit 100 provided in Example 1, and can realize the corresponding function of the pre-simulation-based verification circuit. To avoid duplication, no restrictions are made here.
[0063] The pre-simulation verification method provided in this invention involves inputting a cross-clock domain signal, which includes at least one cross-clock domain sub-signal. Each cross-clock domain sub-signal sequentially flows through a first flip-flop, a delay unit, and a two-stage synchronizer in its corresponding verification sub-circuit to obtain a synchronization signal. The method then determines whether each cross-clock domain sub-signal, after being sequentially delayed, meets preset functional requirements. If it does, it is determined that there is no asynchronous problem; otherwise, it is determined that an asynchronous problem exists. This invention, by adding a delay unit at the front end of the two-stage synchronizer and adjusting the delay unit so that each delay unit is sequentially enabled, simulates EDA post-simulation behavior during the EDA pre-simulation stage. This reproduces asynchronous problems during the pre-simulation stage, uncovering potential asynchronous problems in the asynchronous processing process, allowing for early-stage project resolution and preventing project delays caused by discovering asynchronous problems at the end of the project.
[0064] Example 3
[0065] Furthermore, this application provides an electronic device including a memory and a processor. The memory stores a computer program, which executes the pre-simulation-based verification method provided in Embodiment 2 when the computer program is run on the processor.
[0066] For details, please see Figure 3 The electronic device 300 includes a transceiver 301, a bus interface, and a processor 302. The processor 302 is configured to: input a cross-clock domain signal, the cross-clock domain signal including at least one cross-clock domain sub-signal, each of the cross-clock domain sub-signals sequentially flowing through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal; and determine whether all cross-clock domain sub-signals, after being sequentially inserted with delays, meet preset functional requirements. If they do, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
[0067] In one embodiment, the processor 302 is further configured to execute an M-round delay processing flow when the cross-clock domain signal includes M cross-clock domain sub-signals, M≥2, wherein the i-th round delay processing flow is as follows: after delay processing and synchronization processing of the i-th cross-clock domain sub-signal, a first synchronization signal is obtained; after delay processing and synchronization processing of the j-th cross-clock domain sub-signal, a second synchronization signal is obtained, j≠i, and j∈[1,M].
[0068] In this embodiment of the invention, the electronic device 300 further includes a memory 303. Figure 3 In this context, the bus architecture can include any number of interconnected buses and bridges, specifically linking various circuits together, represented by one or more processors (processor 302) and memory (memory 303). The bus architecture can also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. The bus interface provides an interface. The transceiver 301 can be multiple elements, including transmitters and receivers, providing a unit for communicating with various other devices over a transmission medium. The processor 302 is responsible for managing the bus architecture and general processing, and the memory 303 can store data used by the processor 302 during operation.
[0069] The electronic device 300 provided in this embodiment of the invention can execute the pre-simulation-based verification method provided in Embodiment 2. To avoid repetition, it will not be described again.
[0070] The pre-simulation verification method provided in this invention involves inputting a cross-clock domain signal, which includes at least one cross-clock domain sub-signal. Each cross-clock domain sub-signal sequentially flows through a first flip-flop, a delay unit, and a two-stage synchronizer in its corresponding verification sub-circuit to obtain a synchronization signal. The method then determines whether each cross-clock domain sub-signal, after being sequentially delayed, meets preset functional requirements. If it does, it is determined that there is no asynchronous problem; otherwise, it is determined that an asynchronous problem exists. This invention, by adding a delay unit at the front end of the two-stage synchronizer and adjusting the delay unit so that each delay unit is sequentially enabled, simulates EDA post-simulation behavior during the EDA pre-simulation stage. This reproduces asynchronous problems during the pre-simulation stage, uncovering potential asynchronous problems in the asynchronous processing process, allowing for early-stage project resolution and preventing project delays caused by discovering asynchronous problems at the end of the project.
[0071] Example 4
[0072] Furthermore, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the pre-simulation-based verification method described in embodiment 2 of this application.
[0073] In this embodiment, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.
[0074] The computer-readable storage medium provided in this embodiment can implement the pre-simulation-based verification method provided in Embodiment 2. To avoid repetition, it will not be described again here.
[0075] In all examples shown and described herein, any specific values should be interpreted as merely exemplary and not as limitations; therefore, other examples of exemplary embodiments may have different values.
[0076] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0077] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.
Claims
1. A verification circuit based on pre-simulation, characterized in that, Includes a judgment module and at least one verification sub-circuit; Each of the verification sub-circuits includes a first flip-flop, a delay unit, and a two-stage synchronizer connected in sequence; Each of the first flip-flops is provided with a first clock by a first clock domain, and each of the two-stage synchronizers is provided with a second clock by a second clock domain. The first clock and the second clock have different frequencies or phases. The cross-clock domain signal includes at least one cross-clock domain sub-signal. The verification sub-circuit is used to allow each cross-clock domain sub-signal to flow sequentially through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal. The judgment module is used to determine whether the sequential insertion of delays into all cross-clock domain sub-signals meets the preset functional requirements. If it does, it is determined that there is no asynchronous problem; otherwise, it is determined that there is an asynchronous problem.
2. The verification circuit based on pre-simulation according to claim 1, characterized in that, When the cross-clock domain signal includes M cross-clock domain sub-signals and the number of verification sub-circuits is M, where M≥2, an M-round delay processing flow is executed. The i-th round delay processing flow is as follows: the delay unit of the i-th verification sub-circuit performs delay processing on the i-th cross-clock domain sub-signal, and after the two-stage synchronizer of the i-th verification sub-circuit performs synchronization processing, the first synchronization signal is obtained. The delay unit of the j-th verification sub-circuit delays the j-th cross-clock domain sub-signal. After the two-stage synchronizer of the j-th verification sub-circuit performs synchronization processing, the second synchronization signal is obtained, j≠i, and j∈[1,M].
3. The pre-simulation-based verification circuit according to claim 2, characterized in that, When M≥2, the first synchronization signal and the second synchronization signal of the i-th round are used as the i-th group of synchronization signals; Determine whether all M groups of synchronization signals meet the preset functional requirements. If they do, then there is no asynchronous problem; otherwise, there is an asynchronous problem.
4. The verification circuit based on pre-simulation according to claim 1, characterized in that, Each of the two-stage synchronizers includes a second flip-flop and a third flip-flop; The second trigger is electrically connected to the corresponding delay unit and the third trigger, respectively.
5. The verification circuit based on pre-simulation according to claim 4, characterized in that, The first trigger receives and latches the cross-clock domain sub-signal; The first trigger outputs the cross-clock domain sub-signal to the delay unit; The delay unit outputs the cross-clock domain sub-signal to the two-stage synchronizer after setting the delay. The two-stage synchronizer receives the cross-clock domain sub-signal, performs synchronization processing on the cross-clock domain sub-signal, and outputs a synchronization signal.
6. The verification circuit based on pre-simulation according to claim 1, characterized in that, The preset functional requirements are the requirements for the combinational logic circuit to function normally according to its design.
7. A pre-simulation-based verification method, applied to the pre-simulation-based verification circuit according to any one of claims 1-6, characterized in that, The method includes: An input cross-clock domain signal is provided, which includes at least one cross-clock domain sub-signal. Each cross-clock domain sub-signal flows sequentially through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal. Determine whether the sequential insertion of delays into all cross-clock domain sub-signals meets the preset functional requirements. If it does, then there is no asynchronous problem; otherwise, there is an asynchronous problem.
8. The verification method based on pre-simulation according to claim 7, characterized in that, When the cross-clock domain signal includes M cross-clock domain sub-signals, M≥2, each of the cross-clock domain sub-signals sequentially flows through the first flip-flop, the delay unit, and the two-stage synchronizer corresponding to the verification sub-circuit to obtain a synchronization signal, including: The process involves executing M rounds of delay processing, where the i-th round of delay processing is as follows: after delaying and synchronizing the i-th cross-clock domain sub-signal, the first synchronization signal is obtained. After delaying and synchronizing the j-th cross-clock domain sub-signal, the second synchronization signal is obtained, where j ≠ i and j ∈ [1, M].
9. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program that, when run on the processor, executes the pre-simulation-based verification method according to any one of claims 7-8.
10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the pre-simulation-based verification method as described in any one of claims 7-8.