An IBIS Verilog-A model simulation overclocking optimization method

Abstract

The present application relates to a kind of IBIS Verilog-A model simulation frequency optimization method, for simulating output waveform, comprising: (1) the relationship between output end waveform and variable in Verilog-A program is derived using KCL equation;(2) for all the variables in Verilog-A that contribute to output waveform, the sufficient condition of output waveform is derived;(3) monotonicity between variable and output waveform is derived;(4) when simulation encounters frequency problem, the value of variable is adjusted to adjust output waveform;(5) by testing a large number of input waveforms, and record the value of adjustment, find the law of adjustment value and input waveform;(6) step (5) relationship is realized by Verilog-A code.The present application adjusts the value of variable to adjust simulation output waveform, thereby the optimization method for improving the accuracy when frequency.

Description

Technical Field

[0001] This invention relates to the field of device model optimization technology, and in particular to an IBIS Verilog-A model simulation overclocking optimization method. Background Technology

[0002] An IBIS (Input / Output Buffer Information Specification) is a descriptive document used for simulation. It describes the electrical characteristics of the input and output ports of a device based on the behavior of the component, without involving the internal structure or process parameters of the device, and does not expose intellectual property rights.

[0003] Verilog-A is a hardware description language for analog circuits. It can describe not only analog circuits but also model devices. With the continuous development of technological capabilities, Verilog-A's contribution to device-level and system-level modeling is becoming increasingly important.

[0004] However, the accuracy of the IBIS model built using Verilog-A decreases at high frequencies, falling far short of the accuracy of the highest-precision transistor-level models. This is because when the input signal frequency is too high, the changes in the variables contributing to the simulation output in the Verilog-A program cannot keep up with the rate of change of the input signal. Summary of the Invention

[0005] To address the overclocking issues present in existing IBIS Verilog-A models, this invention aims to provide a simulation optimization method to improve simulation accuracy. This invention optimizes the simulation output waveform by adjusting the values ​​of variables, thereby enhancing overclocking accuracy.

[0006] The technical solution of this invention is as follows:

[0007] An IBIS Verilog-A model simulation overclocking optimization method, used to simulate output waveforms, includes:

[0008] (1) Use the KCL equation to derive the relationship between the output waveform and the variables in the Verilog-A program;

[0009] (2) Using the formula in step (1), derive the sufficient conditions for the output waveform for all variables in Verilog-A that contribute to the output waveform.

[0010] (3) Using the formula in step (1), derive the monotonicity relationship between the variable and the output waveform;

[0011] (4) After steps (1), (2) and (3), when an overclocking problem is encountered in the simulation, the output waveform is adjusted by adjusting the value of the variable.

[0012] (5) By testing a large number of input waveforms and recording the adjusted values, the relationship between the adjusted values ​​and the input waveforms can be found;

[0013] (6) Implement the relationship in step (5) using Verilog-A code.

[0014] According to a preferred embodiment of the present invention, deriving the relationship between the output waveform and variables in the Verilog-A program using the KCL equation includes:

[0015] The KCL equation is shown in equation (I):

[0016] I(pc) + I(pu) - I(pd) - I(gc) = I out (I)

[0017] The IBIS model includes a pull-up transistor PU, a pull-down transistor PD, a power clamp diode PC, and a ground clamp diode GC; Pad is the output terminal, PU_ref is the pull-up reference potential, PD_ref is the pull-down reference potential, PC_ref is the power reference potential, and GC_ref is the ground reference potential; pc represents the branch from PC_ref to Pad, and I(pc) is the current in this branch; pu represents the branch from PU_ref to Pad, and I(pu) is the current in this branch; pd represents the branch from Pad to PD_ref, and I(pd) is the current in this branch; gc represents the branch from Pad to GC_ref, and I(gc) is the current in this branch; I out This represents the current from Pad to ground;

[0018] Let I1, I2, I3, and I4 represent the entries in $table_model within I(pc), I(pu), I(pd), and I(gc), respectively.

[0019] I1=$table_model(V(pc),Vpc_data,Ipc_data,”LL”),

[0020] I2=$table_model(V(pu),Vpu_data,Ipu_data,”LL”),

[0021] I3=$table_model(V(pd),Vpd_data,Ipd_data,”LL”),

[0022] I4=$table_model(V(gc),Vgc_data,Igc_data,”LL”).

[0023] `$table_model()` is a table lookup function in Verilog-A; `V(pc)` is the voltage of the `pc` branch, `Vpc_data` is the voltage data point of the `pc` branch in the IBIS file, and `Ipc_data` is the current data point of the `pc` branch in the IBIS file; `V(pu)` is the voltage of the `pu` branch, `Vpu_data` is the voltage data point of the `pu` branch in the IBIS file, and `Ipu_data` is the current data point of the `pu` branch in the IBIS file; `V(pd)` is the voltage of the `pd` branch, `Vpd_data` is the voltage data point of the `pd` branch in the IBIS file, and `Ipd_data` is the current data point of the `pd` branch in the IBIS file; `V(gc)` is the voltage of the `gc` branch, `Vgc_data` is the voltage data point of the `gc` branch in the IBIS file, and `Igc_data` is the current data point of the `gc` branch in the IBIS file;

[0024] Equations (II), (III), (IV), and (V) are approximately derived as follows:

[0025] I1≈k1V(pc) (II)

[0026] I2≈k2V(pu) (III)

[0027] I3≈k3V(pd) (IV)

[0028] I4≈k4V(gc) (V)

[0029] In equations (II), (III), (IV), and (V), k1≈0, k2<0, k3>0, k2+k3≈0, and k4≈0;

[0030] The relationship between the output waveform and the variables in the Verilog-A program is derived from the KCL equations, as shown in equations (VI) and (VII):

[0031] When C>0

[0032] When C=0

[0033] Where x = total_kpu, y = total_kpd, z = V(pad); total_kpu refers to the current coefficient of the pu branch, total_kpd refers to the current coefficient of the pd branch; V(Pad) refers to the voltage at the output terminal Pad.

[0034] C=ccomp_pc+ccomp_pu+ccomp_pd+ccomp_gc, k=k2=-k3<0;

[0035] ccomp_pc is the equivalent capacitance of the compensation capacitor to the pc branch, ccomp_pu is the equivalent capacitance of the compensation capacitor to the pu branch, ccomp_pd is the equivalent capacitance of the compensation capacitor to the pd branch, and ccomp_gc is the equivalent capacitance of the compensation capacitor to the gc branch.

[0036] According to a preferred embodiment of the present invention, using the formula in step (1), sufficient conditions for the output waveform are derived for all variables in Verilog-A that contribute to the output waveform; including:

[0037] In equations (VI) and (VII), if we assume that the value of x+y remains approximately constant, then the image of z is approximately the same as the image of x; if we set the images of x and y and make their sum approximately constant, then the waveform of z can be derived.

[0038] According to a preferred embodiment of the present invention, the monotonicity relationship between the variable and the output waveform is derived using the formula in step (1); including:

[0039] From equations (VI) and (VII), we can deduce that z is an increasing function of x and a decreasing function of y.

[0040] According to a preferred embodiment of the present invention, when an overclocking problem is encountered in the simulation, adjusting the output waveform by adjusting the values ​​of variables means that the output waveform is adjusted by adjusting the values ​​of x and y.

[0041] Further preferred methods use transistor-level simulation results as a benchmark;

[0042] If the simulation result of the IBIS Verilog-A model is greater than the baseline, then in the Verilog-A program, multiply total_kpu by a positive number α less than 1, i.e., total_kpu = α * total_kpu, 0 < α < 1; or add a positive number β to total_kpd, i.e., total_kpd = total_kpd + β, β > 0, so that the simulation result of the IBIS Verilog-A model becomes smaller and closer to the baseline value;

[0043] If the simulation result value of the IBIS Verilog-A model is less than the baseline, add a positive number α to total_kpu in the Verilog-A program, i.e., total_kpu=total_kpu+α, α>0; or multiply total_kpd by a positive number β less than 1, i.e., total_kpd=β*total_kpd, to increase the value of the simulation result of the IBIS Verilog-A model to approach the baseline value.

[0044] According to a preferred embodiment of the present invention, by testing a large number of input waveforms and recording the adjusted values ​​α and β, the relationship between the adjusted values ​​and the input waveforms is found, including:

[0045] For each different waveform W i , corresponding to different α i ,β i For i = 1, 2, ..., n, use either of the following two methods:

[0046] The first method: use a function f to fit the data, i.e., α i =f1(W i ), β i =f2(W i );

[0047] The second method: using W i As independent variables, respectively with α i ,β i To find α and β, use the $table_model() function in Verilog-A to create a table of dependent variables.

[0048] According to a preferred embodiment of the present invention, in step (5), it is determined whether the accuracy has improved. The accuracy index is the normalized mean square error (NMSE), as shown in equation (VIII):

[0049]

[0050] Where z(n) represents the nth data point of the IBIS Verilog-A model simulation result, z0(n) represents the nth data point of the transistor model, N represents the total number of data points, and NMSE is in decibels (dB).

[0051] If the accuracy is improved, proceed to step (6); otherwise, return to step (4) to continue making adjustments.

[0052] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of an IBIS Verilog-A model simulation overclocking optimization method.

[0053] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of an IBIS Verilog-A model simulation overclocking optimization method.

[0054] The beneficial effects of this invention are as follows:

[0055] 1. This invention corrects the gap between IBIS Verilog-A model simulation and the highest accuracy transistor-level model during overclocking, thereby improving the accuracy of IBIS Verilog-A model simulation.

[0056] 2. The modifications made in this invention are written into the IBIS Verilog-A model in Verilog-A language, and are automatically corrected during simulation without the need for manual operation each time. Attached Figure Description

[0057] Figure 1 This is a flowchart of the IBIS Verilog-A model simulation overclocking optimization method provided by the present invention.

[0058] Figure 2 This is a schematic diagram of the IBIS model to which this invention is based.

[0059] Figure 3 This is a schematic diagram of the output waveform of the IBIS model targeted by this invention.

[0060] Figure 4 This is a schematic diagram showing the comparison of the effects of the overclocking optimization method before and after simulation using the IBIS Verilog-A model in this invention. Detailed Implementation

[0061] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0062] Example 1

[0063] An IBIS Verilog-A model simulation overclocking optimization method, such as Figure 1 As shown, the output waveform used for simulation includes:

[0064] Step 101: Use the KCL equation to derive the relationship between the output waveform and the variables in the Verilog-A program;

[0065] Step 102: Using the formula in Step 101, derive the sufficient conditions for the output waveform for all variables in Verilog-A that contribute to the output waveform.

[0066] Step 103: Using the formula in Step 101, derive the monotonicity relationship between the variables and the output waveform;

[0067] Step 104: After steps 101, 102 and 103, when an overclocking problem is encountered in the simulation, the output waveform is adjusted by adjusting the values ​​of variables, thereby improving the simulation accuracy.

[0068] Step 105: Determine if the accuracy has improved;

[0069] Step 106: By testing a large number of input waveforms and recording the adjusted values, find the relationship between the adjusted values ​​and the input waveforms; implement the relationship between the adjusted values ​​and the input waveforms using Verilog-A code.

[0070] Example 2

[0071] The difference between the IBIS Verilog-A model simulation overclocking optimization method described in Example 1 and the method described in Example 1 is as follows:

[0072] The relationship between the output waveform and variables in the Verilog-A program is derived using the Kirchhoff-Chain (KCL) equations, including:

[0073] The KCL equation is shown in equation (I):

[0074] I(pc) + I(pu) - I(pd) - I(gc) = I out (I)

[0075] like Figure 2 As shown, the arrows indicate the reference direction of the current in the respective branch. The IBIS model includes a pull-up transistor PU, a pull-down transistor PD, a power clamping diode PC, and a ground clamping diode GC; Pad is the output terminal, PU_ref is the pull-up reference potential, PD_ref is the pull-down reference potential, PC_ref is the power reference potential, and GC_ref is the ground reference potential; pc represents the branch from PC_ref to Pad, and I(pc) is the current in this branch; pu represents the branch from PU_ref to Pad, and I(pu) is the current in this branch; pd represents the branch from Pad to PD_ref, and I(pd) is the current in this branch; gc represents the branch from Pad to GC_ref, and I(gc) is the current in this branch; I out This represents the current from Pad to ground; the reference directions for each current are as follows: Figure 2 As shown.

[0076] After debugging, I out 10 -20 The order of magnitude is A, therefore, we take I. out ≈0;

[0077] I(pc)<+-$table_model(V(pc),Vpc_data,Ipc_data,"LL")+ccomp_pc*ddt(V(pc));

[0078] I(pu)<+-total_kpu*$table_model(V(pu),Vpu_data,Ipu_data,"LL")+ccomp_pu*ddt(V(pu));

[0079] I(pd)<+total_kpd*$table_model(V(pd),Vpd_data,Ipd_data,"LL")+ccomp_pd*ddt(V(pd));

[0080] I(gc)<+$table_model(V(gc),Vgc_data,Igc_data,"LL")+ccomp_gc*ddt(V(gc));

[0081] The above four equations are statements in Verilog-A, representing the relationship between four currents and their branch voltages, respectively.

[0082] Where, <+ is the symbol for assigning values ​​to voltage or current in Verilog-A, $table_model() is the table lookup function in Verilog-A, and ddt() is the operator for time differentiation in Verilog-A.

[0083] total_kpu is the current coefficient of the pu branch, and total_kpd is the current coefficient of the pd branch.

[0084] V(pc) is the voltage of the pc branch, Vpc_data is the voltage data point of the pc branch in the IBIS file, and Ipc_data is the current data point of the pc branch in the IBIS file.

[0085] V(pu) is the voltage of the pu branch, Vpu_data is the voltage data point of the pu branch in the IBIS file, and Ipu_data is the current data point of the pu branch in the IBIS file.

[0086] V(pd) is the voltage of the pd branch, Vpd_data is the voltage data point of the pd branch in the IBIS file, and Ipd_data is the current data point of the pd branch in the IBIS file.

[0087] V(gc) is the voltage of the gc branch, Vgc_data is the voltage data point of the gc branch in the IBIS file, and Igc_data is the current data point of the gc branch in the IBIS file.

[0088] ccomp_pc is the equivalent capacitance of the compensation capacitor to the pc branch, ccomp_pu is the equivalent capacitance of the compensation capacitor to the pu branch, ccomp_pd is the equivalent capacitance of the compensation capacitor to the pd branch, and ccomp_gc is the equivalent capacitance of the compensation capacitor to the gc branch.

[0089] $table_model(x,X,Y,”LL”) represents a table with X as the independent variable and Y as the dependent variable, showing the value of Y when X = x, while “LL” indicates the linear interpolation and linear extrapolation methods.

[0090] Let I1, I2, I3, and I4 represent the entries in $table_model within I(pc), I(pu), I(pd), and I(gc), respectively.

[0091] I1=$table_model(V(pc),Vpc_data,Ipc_data,”LL”),

[0092] I2=$table_model(V(pu),Vpu_data,Ipu_data,”LL”),

[0093] I3=$table_model(V(pd),Vpd_data,Ipd_data,”LL”),

[0094] I4=$table_model(V(gc),Vgc_data,Igc_data,”LL”).

[0095] `$table_model()` is a table lookup function in Verilog-A; `V(pc)` is the voltage of the `pc` branch, `Vpc_data` is the voltage data point of the `pc` branch in the IBIS file, and `Ipc_data` is the current data point of the `pc` branch in the IBIS file; `V(pu)` is the voltage of the `pu` branch, `Vpu_data` is the voltage data point of the `pu` branch in the IBIS file, and `Ipu_data` is the current data point of the `pu` branch in the IBIS file; `V(pd)` is the voltage of the `pd` branch, `Vpd_data` is the voltage data point of the `pd` branch in the IBIS file, and `Ipd_data` is the current data point of the `pd` branch in the IBIS file; `V(gc)` is the voltage of the `gc` branch, `Vgc_data` is the voltage data point of the `gc` branch in the IBIS file, and `Igc_data` is the current data point of the `gc` branch in the IBIS file;

[0096] Equations (II), (III), (IV), and (V) are approximately derived as follows:

[0097] I1≈k1V(pc) (II)

[0098] I2≈k2V(pu) (III)

[0099] I3≈k3V(pd) (IV)

[0100] I4≈k4V(gc) (V)

[0101] In equations (II), (III), (IV), and (V), k1≈0, k2<0, k3>0, k2+k3≈0, and k4≈0;

[0102] The relationship between the output waveform and the variables in the Verilog-A program is derived from the KCL equations, as shown in equations (VI) and (VII):

[0103] When C>0

[0104] When C=0

[0105] Where x = total_kpu, y = total_kpd, z = V(pad); total_kpu refers to the current coefficient of the pu branch, total_kpd refers to the current coefficient of the pd branch; V(Pad) refers to the voltage at the output terminal Pad.

[0106] C=ccomp_pc+ccomp_pu+ccomp_pd+ccomp_gc, k=k2=-k3<0;

[0107] ccomp_pc is the equivalent capacitance of the compensation capacitor to the pc branch, ccomp_pu is the equivalent capacitance of the compensation capacitor to the pu branch, ccomp_pd is the equivalent capacitance of the compensation capacitor to the pd branch, and ccomp_gc is the equivalent capacitance of the compensation capacitor to the gc branch.

[0108] Using the formula in step 101, derive sufficient conditions for the output waveform for all variables in Verilog-A that contribute to the output waveform; including:

[0109] In equations (VI) and (VII), if we assume that the value of x+y remains approximately constant, then the image of z is approximately the same as the image of x; if we set the images of x and y and make their sum approximately constant, then the waveform of z can be derived.

[0110] For example, Figure 3 As shown:

[0111] 0≤t≤t1,x=1,y=0,z=1;

[0112] t1≤t≤t2, x↓, y↑, z↑;

[0113] t2≤t≤t3, x↑, y↓, z↑;

[0114] t3≤t≤t4, x↓, y↑, z↓;

[0115] t≥t4, x=0, y=1, z=0.

[0116] (1)z has (a) image.

[0117] (2) x has image (b), and y has image (c).

[0118] It can be proven that (2) is a sufficient but not necessary condition for (1).

[0119] Using the formula in step 101, derive the monotonicity relationship between the variable and the output waveform; including:

[0120] From equations (VI) and (VII), we can deduce that z is an increasing function of x and a decreasing function of y.

[0121] When encountering overclocking issues in simulation, adjusting the output waveform by adjusting the values ​​of variables means adjusting the output waveform by adjusting the values ​​of x and y.

[0122] Based on transistor-level simulation results;

[0123] If the simulation result of the IBIS Verilog-A model is greater than the baseline, then in the Verilog-A program, multiply total_kpu by a positive number α less than 1, i.e., total_kpu = α * total_kpu, 0 < α < 1; or add a positive number β to total_kpd, i.e., total_kpd = total_kpd + β, β > 0, so that the simulation result of the IBIS Verilog-A model becomes smaller and closer to the baseline value;

[0124] If the simulation result value of the IBIS Verilog-A model is less than the baseline, add a positive number α to total_kpu in the Verilog-A program, i.e., total_kpu=total_kpu+α, α>0; or multiply total_kpd by a positive number β less than 1, i.e., total_kpd=β*total_kpd, to increase the value of the simulation result of the IBIS Verilog-A model to approach the baseline value.

[0125] By testing a large number of input waveforms and recording the adjusted values ​​α and β, the relationship between the adjusted values ​​and the input waveforms is found, including:

[0126] For each different waveform W i , corresponding to different αi ,β i For i = 1, 2, ..., n, use either of the following two methods:

[0127] The first method: use a function f to fit the data, i.e., α i =f1(W i ), β i =f2(W i );

[0128] The second method: using W i As independent variables, respectively with α i ,β i To find α and β, use the $table_model() function in Verilog-A to create a table of dependent variables.

[0129] In step 105, it is determined whether the accuracy has improved. The accuracy index is the normalized mean square error (NMSE), and the smaller the value, the higher the accuracy. As shown in equation (VIII):

[0130]

[0131] Where z(n) represents the nth data point of the IBIS Verilog-A model simulation result, z0(n) represents the nth data point of the transistor model, N represents the total number of data points, and NMSE is in decibels (dB).

[0132] If the accuracy is improved, proceed to step 106; otherwise, return to step 104 to continue making adjustments.

[0133] In step 106, based on the relationship between the adjusted amount and the input waveform, write the corresponding Verilog-A code.

[0134] Figure 4 This is a schematic diagram comparing the effects of the overclocking optimization method before and after simulation using the IBIS Verilog-A model in this invention. It can be seen that this invention improves the accuracy of the IBIS Verilog-A model simulation.

[0135] Example 3

[0136] A computer device includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the IBIS Verilog-A model simulation overclocking optimization method described in Embodiment 1 or 2.

[0137] Example 4

[0138] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the IBIS Verilog-A model simulation overclocking optimization method described in Embodiment 1 or 2.

Claims

1. A method for overclocking optimization using an IBIS Verilog-A model for simulating output waveforms, characterized in that, include: (1) Use the KCL equation to derive the relationship between the output waveform and the variables in the Verilog-A program; (2) Using the formula in step (1), derive the sufficient conditions for the output waveform for all variables in Verilog-A that contribute to the output waveform. (3) Using the formula in step (1), derive the monotonicity relationship between the variable and the output waveform; include: From the formula ( ),Mode( It can be deduced that z is an increasing function of x and a decreasing function of y. The relationship between the output waveform and the variables in the Verilog-A program is derived from the KCL equation, as shown in equation ( ),Mode( As shown in the image: When C>0 ; ( ) When C=0 ; ( ) in, , , Total_kpu refers to the current coefficient of the pu branch, and total_kpd refers to the current coefficient of the pd branch; V(Pad) refers to the voltage at the output terminal Pad. ， ； ccomp_pc is the equivalent capacitance of the compensation capacitor to the pc branch, ccomp_pu is the equivalent capacitance of the compensation capacitor to the pu branch, ccomp_pd is the equivalent capacitance of the compensation capacitor to the pd branch, and ccomp_gc is the equivalent capacitance of the compensation capacitor to the gc branch. (4) After steps (1), (2) and (3), when encountering overclocking problems in the simulation, the output waveform is adjusted by adjusting the values ​​of variables; this means: adjusting the output waveform by adjusting the values ​​of x and y; based on the simulation results at the transistor level. If the simulation result of the IBIS Verilog-A model is greater than the baseline, then multiply total_kpu by a positive number less than 1 in the Verilog-A program. That is, total_kpu= ,0< Or add a positive number to total_kpd. That is, total_kpd = total_kpd + , This reduces the simulation results of the IBIS Verilog-A model to be smaller and closer to the baseline value; If the simulation result of the IBIS Verilog-A model is less than the baseline, add a positive number to total_kpu in the Verilog-A program. That is, total_kpu = total_kpu + , Alternatively, multiply total_kpd by a positive number less than 1. That is, total_kpd= This increases the value of the simulation results of the IBIS Verilog-A model to approach the baseline value; (5) By testing a large number of input waveforms and recording the adjusted values, the relationship between the adjusted values ​​and the input waveforms can be found; (6) Implement the relationship in step (5) using Verilog-A code.

2. The IBIS Verilog-A model simulation overclocking optimization method according to claim 1, characterized in that, The relationship between the output waveform and variables in the Verilog-A program is derived using the Kirchhoff-Chain (KCL) equations, including: The KCL equation is as follows ( As shown in the image: （ ） The IBIS model includes a pull-up transistor PU, a pull-down transistor PD, a power clamping diode PC, and a ground clamping diode GC; Pad is the output terminal, PU_ref is the pull-up reference potential, PD_ref is the pull-down reference potential, PC_ref is the power reference potential, and GC_ref is the ground reference potential; pc represents the branch from PC_ref to Pad, and I(pc) is the current in this branch; pu represents the branch from PU_ref to Pad, and I(pu) is the current in this branch; pd represents the branch from Pad to PD_ref, and I(pd) is the current in this branch; gc represents the branch from Pad to GC_ref, and I(gc) is the current in this branch. This represents the current from Pad to ground; remember , , , They are respectively , , , In the $table_model section, note: , , , . `$table_model()` is a table lookup function in Verilog-A; `V(pc)` is the voltage of the `pc` branch, `Vpc_data` is the voltage data point of the `pc` branch in the IBIS file, and `Ipc_data` is the current data point of the `pc` branch in the IBIS file; `V(pu)` is the voltage of the `pu` branch, `Vpu_data` is the voltage data point of the `pu` branch in the IBIS file, and `Ipu_data` is the current data point of the `pu` branch in the IBIS file; `V(pd)` is the voltage of the `pd` branch, `Vpd_data` is the voltage data point of the `pd` branch in the IBIS file, and `Ipd_data` is the current data point of the `pd` branch in the IBIS file; `V(gc)` is the voltage of the `gc` branch, `Vgc_data` is the voltage data point of the `gc` branch in the IBIS file, and `Igc_data` is the current data point of the `gc` branch in the IBIS file; The approximate formula is ( ),Mode( ),Mode( ),Mode( ): （ ） （ ） （ ） （ ） Mode( ),Mode( ),Mode( ),Mode( )middle, , , , , .

3. The IBIS Verilog-A model simulation overclocking optimization method according to claim 2, characterized in that, Using the formula in step (1), derive sufficient conditions for the output waveform for all variables in Verilog-A that contribute to the output waveform; including: Mode( ),Mode( In the equation, if we assume that the value of x+y remains approximately constant, then the image of z is approximately the same as the image of x; if we set the images of x and y and keep their sum approximately constant, then we can derive the waveform of z.

4. The IBIS Verilog-A model simulation overclocking optimization method according to claim 1, characterized in that, By testing a large number of input waveforms and recording the values ​​of the adjustments made. Find the relationship between the adjusted value and the input waveform, including: For each different waveform Corresponding to different For i = 1, 2, ..., n, use either of the following two methods: The first method: use a function f to fit the data, i.e. , ; The second method: As independent variables, respectively with , To create a table of dependent variables, use the `$table_model()` function in Verilog-A to look up the data. .

5. The IBIS Verilog-A model simulation overclocking optimization method according to any one of claims 1-4, characterized in that, In step (5), it is determined whether the accuracy has improved. The accuracy index is the normalized mean square error (NMSE), as shown in equation ( ). As shown in the image: （ ） Where z(n) represents the nth data point in the simulation results of the IBIS Verilog-A model. The nth data point represents the transistor model, where N represents the total number of data points, and NMSE is in decibels (dB). If the accuracy is improved, proceed to step (6); otherwise, return to step (4) to continue making adjustments.

6. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the IBIS Verilog-A model simulation overclocking optimization method according to any one of claims 1-5.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the IBIS Verilog-A model simulation overclocking optimization method according to any one of claims 1-5.

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