An in-memory computing circuit based on a reusable booth multiplication unit

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to an in-memory computing circuit based on a reusable Booth multiplication unit. Two transistors are added on the basis of a conventional 6T-SRAM storage unit, local computing data lines are controlled to perform multi-row data multiplexing, a Booth encoder is added to encode data in the local computing data lines, a Booth decoder and a product generation circuit are used to complete 8-bit data multiplication, and finally, an adder tree is used to accumulate various multiplication results, so that multiplication and accumulation operations of multiple groups of data in an SRAM storage array are completed. The application realizes efficient 8-bit in-memory computing of SRAM, has the characteristics of large storage density and high flexibility, can perform read and write operations at the same time of in-memory computing operations, and is suitable for data-intensive applications, such as neural networks, which require large-scale matrix operations.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically an in-memory computing circuit based on a reusable Booth multiplication unit. Background Technology

[0002] In recent years, the field of artificial intelligence has developed rapidly, with the parameters of various models constantly increasing, leading to ever-higher requirements for hardware computing power. In fields such as image, video, and audio processing, various artificial intelligence models have demonstrated different advantages, but all of them have high requirements for computing speed.

[0003] However, the development speed of hardware computing power is gradually lagging behind the development speed of algorithms. Taking large-scale convolutional neural networks as an example, due to the large number of weights in convolutional and fully connected layers requiring numerous convolution operations, these operations are typically mapped to matrix operations. Large-scale matrix operations not only place high demands on the computing power of traditional von Neumann architectures, but the resulting massive data movement also severely impacts the power consumption and speed of the entire system. Especially in the field of edge computing, although IoT devices are empowered by AI, their small size and insufficient power consumption and computing power are insufficient to support large-scale computing. Many functions can only be implemented by sending computational data to the cloud, where the cloud server processes the data and sends it back. This computing method has high latency, making it difficult to meet the needs of fields such as smart cars that require real-time data processing.

[0004] SRAM in-memory computing circuits are currently a popular solution for data-intensive applications. While performing multiplication operations within the storage cells improves speed, the additional computing units also significantly increase the area required, posing a challenge to the area constraints of edge computing device chips. Controlling the data in the SRAM storage circuits to perform multi-row multiplexing calculations can effectively address this challenge. It also allows more data to be stored locally, further reducing data movement and thus lowering system power consumption. Summary of the Invention

[0005] To address the issues of large area overhead and low storage density in current SRAM in-memory computing circuits, this invention proposes an in-memory computing circuit based on reusable Booth multiplication units. Through innovative unit and structural designs, it achieves in-memory computing functions that can be performed simultaneously with read and write operations while increasing storage density.

[0006] The technical solution of this invention is:

[0007] An in-memory computing circuit based on reusable Booth multiplication units is disclosed. The in-memory computing circuit includes reusable Booth multiplication units, an adder tree, and a sensitive amplifier. Each reusable Booth multiplication unit includes an SRAM memory array, a Booth encoder, a Booth decoder, and a product generation circuit.

[0008] The storage array has two signal lines, WL and SL, connected to each row of 8-transistor SRAM (8T-SRAM) memory cells. The WL signal line is the read / write operation word line, used to select a specific row during write and read operations. The SL signal line is the in-memory computation selection line, used to select data in a specific row and send it to the local computation data line during in-memory computation mode. Each column of memory cells is connected to two signal lines, BL and BLB, which are read / write operation bit lines used to load data into each SRAM during write and read operations. Furthermore, every 8 rows of memory cells in the same column are connected to two signal lines, LCL and LCLB, which are local computation data lines in in-memory computation mode, used to sample the selected SRAM data for Booth multiplication encoding.

[0009] The in-memory computing circuit has SRAM mode, in-memory computing mode, and hybrid mode: In SRAM mode, a sensitive amplifier output is used, and the BL and BLB signal lines are used as the differential inputs of the sensitive amplifier; In in-memory computing mode, the data of the selected row of SRAM is first encoded by Booth multiplication, and then the Booth decoder decodes the generated encoding and input to generate a partial product PP. Then, the product generation circuit combines multiple partial products into a multiplication result POUT, and finally, the adder tree accumulates the 8 multiplication results to generate the final output OUT; Hybrid mode is when SRAM mode and in-memory computing mode are activated simultaneously, but the control of the WL and SL signal lines is required to ensure that the memory cells in the same row are not in SRAM mode and in-memory computing mode at the same time. In this mode, data can be read or written while performing in-memory computing.

[0010] Specifically, the in-memory computing circuit includes eight reusable Booth multiplication units and an adder tree. Each reusable Booth multiplication unit includes an 8x8 memory array, a Booth encoder, four Booth decoders, and a product generation circuit. In in-memory computing mode, each output signal line LCLB of the memory array is connected to the corresponding input signal line CL of the Booth encoder via an inverter. Similarly, each LCL line is connected to the corresponding CLB via the same inverter. The adder tree has eight 16-bit input ports and one 19-bit output port OUT. Each input port corresponds to the output result POUT of one reusable Booth multiplication unit.

[0011] Specifically, the SRAM in the memory array is an 8-transistor memory cell, including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The sources of the first and second PMOS transistors are connected to the power supply. The drain of the first PMOS transistor is connected to the gates of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the drain of the third NMOS transistor, and the source of the fifth NMOS transistor. The drain of the second PMOS transistor is connected to the gates of the first PMOS transistor, the gate of the first NMOS transistor, the drain of the second NMOS transistor, and the source of the fourth NMOS transistor. The drain of the NMOS transistor and the source of the sixth NMOS transistor; the sources of the first and second NMOS transistors are grounded; the substrates of all PMOS transistors are connected to the power supply, and the substrates of all NMOS transistors are grounded; the gate of the third NMOS transistor is connected to the read / write operation word line WL, and its source is connected to the read / write operation bit line BL; the gate of the fourth NMOS transistor is connected to the read / write operation word line WL, and its source is connected to the reverse read / write operation bit line BLB; the gate of the fifth NMOS transistor is connected to the in-memory compute select line SL, and its drain is connected to the in-memory compute mode local compute data line LCL; the gate of the sixth NMOS transistor is connected to the in-memory compute select line SL, and its drain is connected to the in-memory compute mode local compute data line LCLB.

[0012] Specifically, the Booth encoder uses radix-4 Booth encoding. One Booth encoder consists of four encoder units. From the most significant bit to the least significant bit, their inputs correspond to the most significant bits of CL and CLB, respectively. Notably, the least significant bit input of Encoder0 is fixed at 0 and 1. Each encoder unit encodes the value in three consecutive memory cells, generating four control signals: NEG, SF, ZERO, and COR. NEG and SF also have inverted outputs to facilitate decoding. For an 8-bit data stored in eight memory cells in a row, four sets of four-bit control signals will ultimately be generated.

[0013] Specifically, each Booth decoder consists of 9 decoder units. Each decoder corresponds to one input data bit from the least significant bit to the most significant bit (IN) of the 8-bit input data. It is important to note that the inputs of the 7th and 8th decoder units are both the most significant bit (IN) of the 8-bit input data. <7> The nine decoders of the same Booth decoder correspond to the control signals of one encoder. For example, the 0th Booth decoder generates a partial product PP0 based on the control signal of Encoder 0 and the input IN0. The Booth encoder can generate a 9-bit partial product based on the 8-bit data in the storage unit and the 8-bit input data.

[0014] Specifically, the product generation circuit includes several half-adders and full adders. The specific circuit structure is not required in this invention; only its circuit function is described. The input to the product generation circuit is four 9-bit partial products PP3, PP2, PP1, and PP0 generated by four Booth decoders, along with the corresponding compensation signal COR<3:0>. The partial products are shifted and added according to their bit positions; for example, PP1 needs to be shifted 2 bits from PP0. Ultimately, this achieves the multiplication operation between the 8-bit data in the storage array and the input 8-bit data. This multiplication operation supports signed numbers, and all data is represented using two's complement.

[0015] Specifically, the adder tree consists of three levels of adders. The first level consists of four 16-bit adders, whose inputs are the multiplication results POUT0 to POUT7 of eight reusable Booth multiplication units, producing four 17-bit outputs. The accumulation combination method is that units 0-7 are combined sequentially with two adjacent inputs. The second level consists of two 17-bit adders, producing two 18-bit sums, and the accumulation combination method is the same as the first level. The third level uses one 18-bit adder to produce one 19-bit sum as the final output.

[0016] The beneficial effects of this invention are as follows: By modifying the basic SRAM storage unit and adding a Booth encoder, Booth decoder, and product generation circuit to construct a reusable Booth multiplication unit, basic multiplication operations are realized. An adder tree is then added to achieve multiplication accumulation operations. By controlling the input of local computation data lines, the reuse of the multiplication unit within the storage unit is achieved, while also enabling flexible control of storage array read / write operations and in-memory computation operations. It features high storage density and high flexibility, making it suitable for data-intensive applications requiring large-scale matrix operations, such as neural networks. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of an in-memory computing circuit based on a reusable Booth multiplication unit proposed in this invention.

[0018] Figure 2 This is a schematic diagram of an 8T-SRAM memory cell structure.

[0019] Figure 3 This is a schematic diagram of the Booth encoder structure.

[0020] Figure 4 This is a schematic diagram of the Booth decoder structure. Detailed Implementation

[0021] The present invention will now be described in detail with reference to the accompanying drawings.

[0022] Figure 1This is a schematic diagram of an in-memory computation circuit based on reusable Booth multiplication units proposed in this invention. The circuit includes eight reusable Booth multiplication units. Each reusable Booth multiplication unit includes an 8x8 SRAM memory array, a Booth encoder, four Booth decoders, and a product generation circuit. Each row of the memory array shares two control signal lines, WL and SL, and each column shares two bit lines, BL and BLB, and two local computation data lines, LCL and LCLB. The bit lines are directly connected to the input of the sensitive amplifier, and the computation data lines are connected to an inverter and then to the input of the Booth encoder. Each reusable Booth multiplication unit corresponds to an 8-bit input data IN<7:0> and a 16-bit multiplication result output PUT<15:0>. It is important to note that different reusable Booth multiplication units share the same set of control signals SL<7:0>, i.e., SL... <0> When the level is high, all reusable Booth multiplication units will select the memory cell in row 0 for in-memory calculation. Different reusable Booth multiplication units are independent of each other, and only the BL and BLB bit lines of the same column of SRAM are connected to realize the read and write functions of the traditional SRAM memory array.

[0023] Figure 2 This is a schematic diagram of an 8T-SRAM memory cell structure. The first and second PMOS sources are connected to the power supply. The first and second NMOS sources are grounded. The drain of the first PMOS is connected to the gate of the second PMOS, the drain of the first NMOS, the gate of the second NMOS, the drain of the third NMOS, and the source of the fifth NMOS (denoted as node Q). The gate of the first PMOS is connected to the drain of the second PMOS, the gate of the first NMOS, the drain of the second NMOS, the drain of the fourth NMOS, and the source of the sixth NMOS (denoted as node QB). The gates of the third and fourth NMOS are connected to the word line WL. The source of the third NMOS is connected to BL, and the source of the fourth NMOS is connected to BLB. The gates of the fifth and sixth NMOS are connected to SL, and the drains of the fifth and sixth NMOS are connected to LCL and LCLB, respectively.

[0024] In the in-memory computing circuit based on a reusable Booth multiplication unit proposed in this invention, the substrate terminals of all NMOS transistors are connected to ground (GND), and the substrate terminals of all PMOS transistors are connected to the power supply (VDD).

[0025] To enable the reuse of storage cells for multiplication calculation cells, this invention adds two NMOS turn-on control transistors (i.e., the fifth and sixth NMOS transistors) to the traditional 6T-SRAM. Every eight rows of storage cells in the same column are connected to the corresponding LCL and LCLB, and the SL signal controls the selection of one row of data to be sampled each cycle. Since read / write operations and calculation operations have separate turn-on control transistors, read / write operations can be performed on a row of storage cells that are not under calculation operation, thereby achieving flexible control of storage array read / write operations and in-memory calculation operations.

[0026] To achieve efficient multiplication, this invention employs radix-4 Booth multiplication to reduce the number of partial products. A Booth encoder encodes the data in eight storage units of a row, then decodes the encoded data and input data to generate four partial products. Finally, a product generation circuit combines these four partial products into the final multiplication result. The specific encoding and decoding principles will be explained in detail later.

[0027] To achieve multiplication and accumulation operations with multiple data sets, this invention utilizes an adder tree to accumulate the multiplication results of eight reusable Booth multiplication units in parallel. To achieve accumulation operations with even more data sets, additional accumulation circuitry can be added to this invention.

[0028] The following is combined Figure 1 , Figure 2 , Figure 3 and Figure 4 The working principle of the circuit of this invention is explained in detail below:

[0029] 1. SRAM mode:

[0030] (1) Maintain operation:

[0031] During the data retention period in the memory cell, the word line WL remains low. At this time, both the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off, and the bit lines BL and BLB do not affect memory nodes Q or QB. The latch structure consisting of the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1, and the second NMOS transistor MN2 latches the data in memory nodes Q and QB.

[0032] (2) Write operation:

[0033] Assume that before the write operation, the storage node Q of the 8-transistor memory cell is at a low level and QB is at a high level, meaning the stored data is '0'. When writing data '1', the write operation word line WL is pulled high to select the cell, and the data '1' to be written is loaded onto the write bit line, i.e., BL is high and BLB is low. BL pulls up node Q through the third NMOS transistor MN3, and BLB pulls down node QB through the fourth NMOS transistor MN4, breaking the latch structure feedback loop, and the data '1' is written to the memory cell. Writing data '0' follows the same process.

[0034] (3) Read operation

[0035] Assume that before the read operation, the storage node Q is low and QB is high, meaning the stored data is '0'. At the start of the read operation, bit lines BL and BLB are pre-charged to high, and word line WL is then pulled high. The third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned on, and the first NMOS transistor is turned on because QB is high. At this time, BL is pulled low through the first NMOS transistor MN2 and the third NMOS transistor, while BLB remains unchanged, completing the reading of '0'. Reading data '1' follows the same process. The voltage changes in BL and BLB are amplified by the connected sensitive amplifier, ultimately completing the data reading.

[0036] In SRAM mode, the SL control signal line is always low during hold, write, and read operations, and both the fifth and sixth NMOS transistors are turned off. If all memory cells in the entire circuit are in SRAM mode, then the in-memory computing circuit is considered to be in SRAM mode.

[0037] 2. In-memory computing mode:

[0038] (1) Data selection

[0039] The data stored in the memory cell is '0', that is, Q node is '0' and QB node is '1'. During calculation, it represents '0'. The same applies when the stored data is '1'. In in-memory calculation mode, the word line WL remains low, and the third and fourth NMOS transistors are both turned off. If none of the memory cells in the entire circuit are in SRAM mode, then the in-memory calculation circuit is considered to be in in-memory calculation mode.

[0040] For a reusable Booth multiplication unit, if you want to select the data in row 0 to multiply with the input, then SL <0> When pulled high, SL<7:1> remains low. At this time, the fifth and sixth NMOS transistors in the 8 SRAMs of row 0 are turned on, while the fifth and sixth NMOS transistors in the remaining 7 SRAMs are turned off. The local computation data lines LCL and LCLB acquire the values ​​of the Q and QB nodes of the corresponding column SRAMs, respectively. LCL and LCLB are then connected to the corresponding Booth encoder input lines CLB and CL after passing through an inverter. The data selection of the 8 multiplexed Booth multiplication units remains synchronized, meaning that data from the same row is selected in each cycle.

[0041] (2) Booth encoding

[0042] Figure 3 This is a schematic diagram of a Booth encoder, containing four encoding units. The input to Encoder3 is the highest three bits of CL and CLB, and its encoded output is also the highest bit of the corresponding control signal, decreasing sequentially according to the encoding unit number. For Encoder0, its lowest bit input is 0 and 1, independent of CL and CLB; this is a necessary extension operation for 8-bit data using radix-4 Booth encoding. Each encoding unit uses standard CMOS logic. Due to the differential inputs of CL and CLB, two XOR gates save two inverters. The specific encoding rule truth table is shown in Table 1.

[0043] Table 1 Truth Table of Booth Encoding Rules

[0044] According to Table 1 and Figure 3 The decoding logic can be summarized as follows:

[0045] NEG i =CL 2i+1

[0046]

[0047]

[0048]

[0049] (3) Booth decoding

[0050] Figure 4This is a schematic diagram of a Booth decoder. Each Booth decoder contains 9 decoding units, controlled by the encoding result generated by the same Booth encoder. The 8th decoding unit is used for the extension of the shift operation (±2X), so its input, along with the 7th decoding unit, is the highest bit IN of the input data. <7> The inputs and outputs of other decoding units correspond bit-by-bit. Since the total number of decoding units is significantly greater than that of encoding units, to reduce area and power consumption, the XOR gates and data selectors in the decoding units do not use standard CMOS logic but rather transmission gate logic. Adjacent decoding units are interconnected via NY and NYN gates, using two transmission gates to select whether to shift the data. The ZERO signal at the output is controlled by a NOR gate, which improves the decoding speed for the 0X case. Figure 4 The decoding logic can be summarized as follows:

[0051]

[0052] NYNi j =NYi j-1

[0053]

[0054] (4) Multiplication and addition

[0055] The product generation circuit is responsible for combining the four partial product results PP0, PP1, PP2, PP3 and the corresponding compensation signal COR. <0> COR <1> COR <2> COR <3> The multiplication operation between the 8-bit data in the storage unit and the input 8-bit data is completed by adding the corresponding bits, and the multiplication result POUT is generated.

[0056]

[0057] The adder tree is responsible for accumulating the multiplication outputs of 8 reusable Booth multiplication units within the same cycle to generate the final multiplication accumulation result OUT.

[0058]

[0059] In the above formula, IN i W represents the input data of the i-th reusable Booth multiplication unit. i This represents the data selected by the i-th reusable Booth multiplication unit. That is, within one cycle, eight 8-bit inputs and 8-bit weights are multiplied and accumulated. By concatenating more columns, matrix-vector multiplication can be achieved. By accumulating over multiple cycles, larger-scale matrix multiplication operations can be performed.

[0060] 3. Mixed Mode:

[0061] The SRAM mode and in-memory computation mode described above are defined for a specific row of memory cells. Hybrid mode refers to a circuit where some cells are in SRAM mode and others in in-memory computation mode; that is, the circuit is in hybrid mode as long as not all memory cells are in either SRAM or in-memory computation mode. For a given SRAM cell, the SL and WL signals will not be high simultaneously to ensure the stability of read / write operations and in-memory computation operations. Since 8 rows of memory cells share one computation unit, normal read / write operations can be performed on memory cell rows not selected for in-memory computation without affecting cells currently undergoing in-memory computation. Therefore, from the perspective of the entire circuit, data can be read and written to memory cells simultaneously during in-memory computation, greatly improving system flexibility.

[0062] In summary, this invention proposes an in-memory computing circuit based on reusable Booth multiplication units, which achieves matrix-vector multiplication operations by improving the storage units and overall structure. Compared with traditional structures, this invention reduces data movement by Booth encoding of data in the storage units, performing Booth multiplication operations around the storage array, and then using an adder tree to complete the multiplication accumulation operation. Compared with existing in-memory computing structures, this invention improves the circuit's storage density by reusing computing units across multiple rows of storage units, while simultaneously achieving parallelism between circuit-level read / write operations and in-memory computing operations, thus enhancing the circuit's flexibility.

Claims

1. An in-memory computing circuit based on a reusable Booth multiplication unit, characterized in that, Includes reusable Booth multiplier units, adder trees, and sensitive amplifiers; The number of reusable Booth multiplication units is 8. Each reusable Booth multiplication unit includes one SRAM storage array, one Booth encoder, four Booth decoders, and one product generation circuit. The storage array is connected to the input of the Booth encoder via a local computation data line and an inverter. The input of the Booth decoder includes the input data of the Booth multiplication unit and the encoding result of the Booth encoder. The input of the product generation circuit includes the output of the Booth decoder and the compensation signal generated by the Booth encoder. The output of the product generation circuit is the multiplication result of the selected storage unit's 8-bit data and the input 8-bit data. The memory array consisting of all reusable Booth multiplication units is composed of 8 rows and 8 columns of 8T-SRAM. The memory cells in each row share read / write operation word lines and in-memory computation selection lines. The memory cells in each column share a set of local computation data lines. The read / write operation word lines are used to select data from a specific row during in-memory computation operations and send it to the corresponding local computation data lines. In the memory array of 8 reusable Booth multiplication units, the memory cells in the same column share the same set of read / write operation bit lines. The in-memory computation selection lines are used to select data from a specific row during read / write operations and connect it to the corresponding read / write operation bit lines. The adder tree has eight 16-bit input ports, each port corresponding to the multiplication result of a reusable Booth multiplication unit. The output of the adder tree is a 19-bit multiplication accumulation result. When the circuit is in in-memory computing mode, the output of the adder tree is used as the output of the in-memory computing circuit. The number of sensitive amplifiers is 8. The input of each sensitive amplifier corresponds to the read and write operation bit lines of a column of memory cells. When the circuit is in SRAM mode, the output of the sensitive amplifier is used as the output of the in-memory computing circuit. When the circuit is in mixed mode, the output of the sensitive amplifier and the output of the adder tree are used as the output of the in-memory computing circuit after data selection.

2. The in-memory computing circuit based on a reusable Booth multiplication unit according to claim 1, characterized in that, The memory cell in the memory array is an 8-transistor memory cell, including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The sources of the first and second PMOS transistors are connected to the power supply. The drain of the first PMOS transistor is connected to the gate of the second PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, the drain of the third NMOS transistor, and the source of the fifth NMOS transistor. The drain of the second PMOS transistor is connected to the gate of the first PMOS transistor, the gate of the first NMOS transistor, and the source of the second NMOS transistor. The drain of the MOS transistor, the drain of the fourth NMOS transistor, and the source of the sixth NMOS transistor; the source of the first NMOS transistor and the source of the second NMOS transistor are grounded; the substrates of all PMOS transistors are connected to the power supply, and the substrates of all NMOS transistors are grounded; the gate of the third NMOS transistor is connected to the read / write operation word line, and its source is connected to the read operation bit line; the gate of the fourth NMOS transistor is connected to the read / write operation word line, and its source is connected to the write operation bit line; the gate of the fifth NMOS transistor is connected to the in-memory compute select line, the gate of the sixth NMOS transistor is connected to the in-memory compute select line, and the drains of the fifth and sixth NMOS transistors are connected to a set of local compute data lines for the in-memory compute mode.

3. The in-memory computing circuit based on a reusable Booth multiplication unit according to claim 2, characterized in that, The Booth encoder uses radix-4 Booth encoding and includes four encoding units. From the most significant bit to the least significant bit, the inputs correspond to the most significant bit to the least significant bit of the encoder input signal line. For eight bits of data stored in eight memory units in the same row, four sets of four-bit control signals are generated. The Booth decoder includes nine decoding units. From the least significant bit to the most significant bit, each decoding unit corresponds to one input data bit. The encoding units use standard CMOS logic, and the XOR gates and data selectors in the decoding units use transmission gate logic to reduce area and power consumption. The product generation circuit combines four partial products and four compensation signals into a multiplication result, which serves as the 16-bit output of the reusable Booth multiplication unit. The adder tree accumulates the multiplication results of eight reusable Booth multiplication units within one cycle to generate a final 19-bit multiplication accumulation output.

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