3D memory devices and methods for programming the same

Abstract

A three-dimensional memory device is disclosed. The three-dimensional memory device includes a plurality of strings of memory cells, each string of memory cells including a plurality of memory cells; a plurality of word lines, each word line associated with respective memory cells of the plurality of strings of memory cells at a same vertical distance from a substrate; and a control circuit. The control circuit is configured to apply a sequence of incremental step programming pulses to selected memory cells and perform a program verify operation after applying a first programming pulse. The control circuit is further configured to determine an updated first programming pulse based on a second programming pulse indicating that a selected memory cell has been programmed and perform the program verify operation starting from the updated first programming pulse for each subsequent selected memory cell.

Description

[0001] Cross-references in related fields

[0002] This application claims priority to Italian patent application No. 102022000008348, filed on April 27, 2022, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of memory devices. In particular, this disclosure relates to a solid-state memory device. More specifically, this disclosure relates to a three-dimensional (3D) memory device with fast programming time characteristics. Background Technology

[0004] Traditional 3D memory devices consist of multiple strings of memory cells. Each string of memory cells typically includes multiple memory cells stacked on top of each other on a substrate, with each memory cell located at a corresponding vertical distance from the substrate.

[0005] The memory cell can be programmed to store each of a plurality of logic levels.

[0006] Each memory cell typically includes a MOS transistor (hereinafter, a memory transistor) with a charge-harvesting or floating-gate structure, meaning it includes a drain terminal, a source terminal, a control terminal (control gate), and a control region buried in an oxide layer for electrical isolation. For example, the control region may include silicon nitride (charge-harvesting structure) or doped polysilicon (floating-gate structure).

[0007] The logic level is physically stored in each memory cell as a charge within a control region: changes in the charge within the control region define corresponding changes in the threshold voltage of the memory transistor. During a read operation of the selected memory cell, this change in the threshold voltage determines a corresponding modulation of the channel current through the memory transistor, the value of which represents the logic level stored in the memory cell.

[0008] Each memory cell can be a single-level memory cell, i.e., a memory cell capable of storing one bit (i.e., logic level 0 or 1), or a multi-level memory cell, i.e., a memory cell capable of storing two bits (i.e., logic levels 00, 01, 10 or 11), three bits (i.e., logic levels 000, 001, 010, 011, 100, 101, 110 or 111) or more bits.

[0009] According to common implementation schemes, the selected memory cell is programmed using ISPP (“Incremental Step Pulse Programming”) technology at a target logic level (or equivalently, at a target threshold voltage).

[0010] According to the ISPP technique, an incremental step programming pulse sequence is applied to the selected memory cells. The incremental step programming pulse sequence (hereinafter referred to as the programming pulse sequence) consists of a short, continuous programming (voltage) pulse sequence with gradually increasing amplitude based on a step voltage (“ISPP voltage step”). To compensate for variations in the size of memory cells within each memory cell string (which would otherwise determine the variability in programming time on the corresponding memory cells), multiple ISPP voltage steps can be set, where each ISPP voltage step is associated with a corresponding group of memory cells (hereinafter referred to as the ISPP memory cell group).

[0011] Based on the ISPP technique, multiple programming verification operations are performed to check whether the selected memory cell has been programmed with the target threshold voltage.

[0012] For each target threshold voltage, the programming pulse and subsequent programming verification operation are applied repeatedly until the threshold voltage of the selected memory cell rises above the corresponding programming verification voltage indicating that the selected memory cell has been programmed at the target threshold voltage.

[0013] To optimize programming time, the programming pulse that initiates the programming verification operation (hereinafter referred to as the PV ("Programming Verification") start programming pulse) is typically variable at the target threshold voltage.

[0014] The PV start programming pulses, which are associated with (all) target threshold voltages that can program each memory cell, are collectively referred to as the PV ("programming verification") scheme. Summary of the Invention

[0015] Traditional 3D memory devices, especially the traditional PV schemes on which they are based, may not be satisfactory when very fast programming times are required.

[0016] This is mainly because, for each target threshold voltage, the PV start programming pulse is a predetermined programming pulse that is usually determined during the characterization phase based on the memory cell with the fastest programming time among the memory cells in the ISPP memory cell group (hereinafter referred to as the fastest memory cell): In fact, for each ISPP memory cell group, with a predetermined margin, the PV start programming pulse is usually determined as the programming pulse before the final programming pulse of the fastest memory cell in the ISPP memory cell group.

[0017] Therefore, the traditional PV scheme provides a fixed PV start programming pulse for all memory cells belonging to the same ISPP memory cell group.

[0018] Traditional PV schemes provide unnecessary programming verification operations for the slower memory cells in the ISPP memory cell group, which means slower programming time.

[0019] The applicant has faced the aforementioned problems and has designed a 3D memory device that has identified an effective PV scheme that can reduce programming time.

[0020] One or more aspects of this teaching are set forth in the independent claims, and advantageous features of the same teaching are pointed out in the dependent claims, the wording of which is incorporated herein by reference verbatim (wherein any advantageous feature is provided with reference to the particular aspect of this teaching which applies to any other aspect).

[0021] More specifically, one aspect of this teaching relates to a three-dimensional memory device. The three-dimensional memory device may include multiple memory cell strings; each memory cell string may include multiple memory cells stacked on a substrate, each memory cell being at a corresponding vertical distance from the substrate. The three-dimensional memory device may include multiple word lines, each word line being associated with a corresponding memory cell of the multiple memory cell strings at the same vertical distance from the substrate. The three-dimensional memory device may include control circuitry configured to:

[0022] (i) Apply an incremental step programming pulse sequence to the selected memory cell in the reference memory cell string to program the selected memory cell at a target threshold voltage among a plurality of target threshold voltages;

[0023] (ii) After the first programming pulse of the incremental step programming pulse sequence is applied, a programming verification operation is performed in response to the corresponding programming pulse, wherein the first programming pulse used to start the programming verification operation is a predetermined programming pulse determined by the three-dimensional memory device.

[0024] The control circuit can be further configured as follows:

[0025] (iii) Based on a second programming pulse indicating that the selected memory cell has been programmed at a target threshold voltage, determine an updated first programming pulse for the selected memory cell and for the target threshold voltage, and

[0026] (iv) A programming verification operation is performed starting from the updated first programming pulse of each subsequently selected memory cell, each of which will be programmed at the target threshold voltage and on the same word line as the selected memory cell.

[0027] Another aspect of this teaching relates to an electronic system including at least one of the aforementioned three-dimensional memory devices.

[0028] Another aspect of this teaching relates to a method of operating a three-dimensional memory device. The three-dimensional memory device may include: a plurality of memory cell strings, each memory cell string comprising a plurality of memory cells stacked on a substrate, each memory cell being at a corresponding vertical distance from the substrate; and a plurality of word lines, each word line associated with a corresponding memory cell of the plurality of memory cell strings at the same vertical distance from the substrate. The method may include:

[0029] (i) Apply an incremental step programming pulse sequence to the selected memory cell in the reference memory cell string to program the selected memory cell at a target threshold voltage among a plurality of target threshold voltages;

[0030] (ii) After the first programming pulse of the incremental step programming pulse sequence is applied, a programming verification operation is performed in response to the corresponding programming pulse, wherein the first programming pulse used to start the programming verification operation is a predetermined programming pulse determined by the three-dimensional memory device.

[0031] (iii) Based on a second programming pulse indicating that the selected memory cell has been programmed at a target threshold voltage, determine an updated first programming pulse for the selected memory cell and for the target threshold voltage, and

[0032] (iv) A programming verification operation is performed starting from the updated first programming pulse of each subsequently selected memory cell, each of which will be programmed at the target threshold voltage and on the same word line as the selected memory cell. Attached Figure Description

[0033] These and other features and advantages of this disclosure will become apparent from the following detailed description of some non-limiting embodiments; for a better understanding, the following detailed description should be read in conjunction with the accompanying drawings, wherein:

[0034] Figure 1 A three-dimensional memory device according to an embodiment of the present disclosure is schematically illustrated;

[0035] Figure 2A A programming verification scheme for a TLC memory cell according to an embodiment of the present disclosure is shown;

[0036] Figure 2B A predetermined programming verification scheme for a TLC memory cell according to an embodiment of the present disclosure is shown;

[0037] Figure 2C An updated programming verification scheme according to embodiments of the present disclosure is shown;

[0038] Figure 3 An operational diagram of a method according to an embodiment of the present disclosure is shown, and

[0039] Figure 4 A simplified block diagram of an electronic system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0040] Figure 1 A three-dimensional (3D) memory device 100 according to an embodiment of the present disclosure is illustrated schematically.

[0041] In the following text, unless otherwise stated and / or unless there is obvious incompatibility among the combination of features, the features introduced by the term "according to the embodiment" will be interpreted as additional or alternative features to any previously introduced features.

[0042] In the following text, only elements and operations considered relevant to understanding this disclosure will be shown and discussed, while other well-known elements and operations will be intentionally omitted for the sake of brevity.

[0043] The 3D memory device 100 includes a memory array 105.

[0044] According to an embodiment, the memory array 105 includes a plurality of memory blocks 110.

[0045] According to an embodiment, each storage block 110 includes a plurality of memory cell strings 115 n，i (n = 1, 2, ..., N; i = 1, 2, ..., I). Multiple memory cell strings 115 of general-purpose storage block 110. n，i The figure is shown in a three-dimensional view with reference to the mutually orthogonal axes X, Y, and Z.

[0046] According to an embodiment, each memory cell string has 115 n，i Includes multiple memory cells T stacked on top of each other on a substrate (not shown). k (k = 1, 2, ..., K), where each memory cell is at a corresponding vertical distance from the substrate (i.e., the distance along the Z-axis).

[0047] According to an embodiment, each memory cell string has 115 n，i memory cell T k Connected in series (NAND memory cell string).

[0048] According to the embodiment, each memory cell T k It can be programmed to store each of multiple logic levels.

[0049] According to the embodiment, each memory cell T kThis includes MOS transistors (hereinafter, memory transistors) with charge-harvesting or floating-gate structures, namely, they include a drain terminal, a source terminal, a control terminal (control gate), and a control region buried in an oxide layer for electrical isolation. The control region may include silicon nitride (charge-harvesting structure) or doped polysilicon (floating-gate structure).

[0050] The logic levels are physically stored in each memory cell T as charges within the control region. k In the diagram: The charge change within the control region defines a corresponding change in the threshold voltage of the memory transistor. During a read operation of the selected memory cell, this change in the threshold voltage determines a corresponding modulation of the channel current through the memory transistor, the value of which represents the value stored in memory cell T. k The logic levels in the code.

[0051] During programming operations, charge is injected into the control region through the Fowler-Nordheim tunneling effect (floating gate structure) or the hot carrier injection effect (charge harvesting structure): According to the Fowler-Nordheim tunneling effect / hot carrier injection effect, the electric field between the control gate and drain terminals of the memory transistor allows charge to pass through the oxide layer to reach the control region.

[0052] According to the embodiment, each memory cell T k It can be a single-level memory cell, that is, a memory cell capable of storing one bit. Each single-level memory cell can be programmed to store a logic level between two logic levels (i.e., 0 and 1).

[0053] According to the embodiment, each memory cell T k It can be a multi-level memory cell, that is, a memory cell capable of storing two or more bits.

[0054] As an example only, consider a multi-level memory cell capable of storing two bits, which can be programmed to store one of four logic levels (i.e., 00, 01, 10, and 11).

[0055] As just another example, consider a multi-level memory cell capable of storing three bits, which is often referred to as a TLC (“three-level cell”) memory cell and can be programmed to store one of eight logic levels (i.e., 000, 001, 010, 011, 100, 101, 110, and 111).

[0056] According to an embodiment, the 3D memory device 100 includes multiple word lines WL k (k = 1, 2, ..., K), each word line is connected to multiple memory cells in a string of 115. n，iThe corresponding memory cells arranged at the same vertical distance from the substrate (i.e., memory cells arranged on the same k-th XY plane) are associated.

[0057] According to an embodiment, the 3D memory device 100 includes: multiple bit lines BLn (n = 1, 2, ..., N) along the Y-axis, each bit line being associated with a corresponding set of memory cell strings 115. n、i Associated, that is, bit line BL1 is associated with a set of memory cell strings 115 1，1 115 1，i 115 1，I Associated, bit line BLn is connected to a set of memory cell strings 115 n，1 115 n，i 115 n，I Associated, bit line BLN is connected to 115 in a set of memory cell strings. N，1 115 N，i 115 N，I Related.

[0058] According to an embodiment, each memory cell string has 115 n，i An electrical connection is made between the associated bit line BLn and the ground line that provides a ground (or ground) potential (e.g., 0V, as is common in electronic circuits).

[0059] According to an embodiment, the 3D memory device 100 includes a plurality of string select transistors TS. i According to an embodiment, each memory cell string has 115 cells. n，i With the selective transfer of memory cell string 115 n，i (memory unit T) k Connect to the corresponding bit line BL n The corresponding string selection transistor TS i Associated. According to an embodiment, each memory cell string 115 n，i Select the corresponding string transistor TS i Electrically connected to the associated bit line BL n .

[0060] According to an embodiment, the 3D memory device 100 includes a plurality of ground selection transistors TG. i According to an embodiment, each memory cell string has 115 cells. n，i With the selective transfer of memory cell string 115 n，i (memory unit T) k The corresponding ground selection transistor TG is connected to the corresponding ground wire. i Associated. According to an embodiment, each memory cell string 115 n，i Select the appropriate grounding transistor TG iElectrically connected to the associated grounding wire.

[0061] According to an embodiment, the 3D memory device 100 includes: a plurality of serial select lines S i Each string select line is used to select the corresponding string select transistor TS. i ; and multiple grounding selection lines G i Each ground select line is used to select the corresponding ground select transistor TG. i .

[0062] According to an embodiment, the 3D memory device 100 includes a function for storing data on multiple word lines WL based on row addresses. k Word line selection circuit 120 selects one or more word lines.

[0063] According to an embodiment, the 3D memory device 100 includes a function for displaying data on multiple bit lines BL based on column addresses. n Bit line selection circuit 125 selects one or more bit lines.

[0064] According to an embodiment, the 3D memory device 100 includes features for selecting multiple serial lines S i Select one or more string selection lines and / or select multiple ground selection lines G. i Select one or more ground selection lines from the series / ground selection circuit (not shown).

[0065] According to an embodiment, the 3D memory device 100 includes a function for reading from a selected memory cell T. k The logic level reading circuit 130 in the middle.

[0066] According to an embodiment, the read circuit 130 is configured to read data based on the flow through the selected memory cell T. k Associated bit line BL n The current is used to read the logic level of the selected memory cell.

[0067] According to an embodiment, the 3D memory device 100 includes control circuitry (hereinafter referred to as a memory controller) 135 configured to control all operations of the 3D memory device 100. As conceptually represented by the connecting arrows in the figures, the memory controller 135 can be configured to provide row addresses to word line selection circuitry 120, column addresses to bit line selection circuitry 125, and memory cell string 115. n，i The address is received and the logic level being read by the read circuit 130 is received.

[0068] According to an embodiment, the memory controller 135 is configured to program selected memory cells of a selected memory cell string at a target logic level (or equivalently, at a target threshold voltage) based on ISPP (“Incremental Step Pulse Programming”) technology.

[0069] According to the ISPP technique (e.g., by or under the control of the memory controller 135), an incremental step programming pulse sequence is applied to the selected memory cell T. k According to an embodiment, the incremental step programming pulse sequence (hereinafter simply referred to as the programming pulse sequence) comprises a short, continuous programming (voltage) pulse sequence with gradually increasing amplitude based on a step voltage. The amplitude of this "step" (i.e., the increase in amplitude of each programming pulse relative to the immediately preceding programming pulse in the sequence, or equivalently, the increase in amplitude between subsequent programming pulses in the sequence) is referred to herein as an "ISPP voltage step". Without loss of generality, in a practical embodiment of the 3D memory device 100, multiple ISPP voltage steps may be provided, each ISPP voltage step being associated with a corresponding set of memory cells (hereinafter, each set of memory cells associated with a corresponding ISPP voltage step will be referred to as an ISPP memory cell group): by way of example only, different ISPP voltage steps for different ISPP memory cell groups can allow compensation for variations in the size of memory cells in each string of memory cells (i.e., along the Z-axis), which would otherwise determine the variability in programming time on the individual memory cells.

[0070] According to the ISPP technique, (e.g., by or under the control of the memory controller 135) multiple programming verification operations are performed to check whether the selected memory cell has been programmed at the target threshold voltage.

[0071] like Figure 2A As shown, it illustrates a programming verification scheme (hereinafter referred to as the PV scheme) obtained by programming one or more TLC memory cells using ISPP technology, for each target threshold voltage Vth. h (h = 1, 2, ..., 7), starting from the first programming pulse (in the PV scheme, programming pulses P1, P5, P7, P... 10 P 12 P 15 P 17 Starting from the target threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, Vth6, and Vth7 respectively, up to the second programming pulse (in the PV scheme, programming pulses P9 and P...). 12 P 14 P 16 P 19 P21 P 22 For the target threshold voltages Vth1, Vth2, Vth3, Vth4, Vth5, Vth6, and Vth7 respectively, in the programmed pulse sequence P1-P 22 (P1 is the initial programming pulse of the programming pulse sequence) Each programming verification operation (represented by PV in the diagram) is performed after the corresponding programming pulse, where, for each target threshold voltage Vth h The corresponding second programming pulse determines that the target threshold voltage Vth has been reached. h After programming the selected memory cell, a programming verification operation is performed.

[0072] In other words, for each target threshold voltage Vth h Starting with the corresponding first programming pulse, programming pulses are repeatedly applied and subsequent programming verification operations are repeated until the threshold voltage of the selected memory cell rises above the target threshold voltage Vth. h The corresponding programming verification voltage is used to program the selected memory cell.

[0073] According to the embodiment, for each target threshold voltage Vth h The corresponding first programming pulse indicates the programming verification operation that begins with it (hereinafter referred to as the PV (“programming verification”) start programming pulse).

[0074] According to the embodiment, for each target threshold voltage Vth h The corresponding second programming pulse represents the programming pulse after the programming verification operation ends; that is, in response to this programming pulse, the corresponding programming verification operation determines that the target threshold voltage Vth has been achieved. h The selected memory cell is programmed, and therefore the programming pulse sequence ends (otherwise, for the target threshold voltage Vth). h The corresponding second programming pulse represents the final programming pulse in the programming pulse sequence that starts from the initial programming pulse P1.

[0075] exist Figure 2A In the example shown:

[0076] When considering the target threshold voltage Vth1, the final programming pulse is programming pulse P9. Therefore, a sequence of nine programming pulses starting from the initial programming pulse P1 and nine programming verification operations starting from the PV-starting programming pulse P1 are necessary for programming the selected memory cell at the target threshold voltage Vth1.

[0077] When considering the target threshold voltage Vth2, the final programming pulse is the programming pulse P. 12Therefore, a sequence of twelve programming pulses starting from the initial programming pulse P1 and eight programming verification operations starting from the programming pulse P5 starting from PV are necessary for programming the selected memory cell at the target threshold voltage Vth2.

[0078] When considering the target threshold voltage Vth3, the final programming pulse is the programming pulse P. 14 Therefore, a sequence of fourteen programming pulses starting from the initial programming pulse P1 and eight programming verification operations starting from the programming pulse P7 starting from PV are necessary for programming the selected memory cell at the target threshold voltage Vth3.

[0079] When considering the target threshold voltage Vth4, the final programming pulse is the programming pulse P. 16 Therefore, the sequence of sixteen programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV... 10 The initial seven programming verification operations are necessary for programming the selected memory cells at the target threshold voltage Vth4;

[0080] When considering the target threshold voltage Vth5, the final programming pulse is the programming pulse P. 19 Therefore, the sequence of nineteen programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV... 12 The initial eight programming verification operations are necessary for programming the selected memory cells at the target threshold voltage Vth5;

[0081] When considering the target threshold voltage Vth6, the final programming pulse is the programming pulse P. 21 Therefore, the twenty-one programming pulse sequence starting from the initial programming pulse P1 and the programming pulse P starting from PV... 15 The initial seven programming verification operations are necessary for programming the selected memory cells at the target threshold voltage Vth6, and

[0082] When considering the target threshold voltage Vth7, the final programming pulse is the programming pulse P. 22 Therefore, the sequence of twenty-two programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV... 17 The initial six programming verification operations are necessary for programming the selected memory cell at the target threshold voltage Vth7.

[0083] According to the embodiment, for each target threshold voltage Vth h The PV start programming pulse is a predetermined programming pulse determined during the characterization phase. Similar to conventional methods, this is applied for each target threshold voltage Vth. hFor each ISPP memory cell group, the PV start programming pulse can be determined based on the memory cell with the fastest programming time among the memory cells in the ISPP memory cell group (hereinafter referred to as the fastest memory cell): by way of example only, for each ISPP memory cell group, the PV start programming pulse can be determined as the programming pulse that precedes (with a predetermined margin) the final programming pulse of the fastest memory cell in the ISPP memory cell group.

[0084] Figure 2B The PV scheme (hereinafter referred to as the fast PV scheme) associated with the fastest memory cell in the ISPP memory cell group is shown. As mentioned above, according to the conventional method, for each threshold voltage Vth h The final programming pulse associated with the fastest memory cell in each ISPP memory cell group is used (for this threshold voltage Vth) h Determine the PV start programming pulse for all memory cells in the ISPP memory cell group.

[0085] exist Figure 2B In the example shown:

[0086] When considering the target threshold voltage Vth1, the programming pulse P7 is the final programming pulse for the fastest memory cell. Therefore, the seven programming pulse sequence starting from the initial programming pulse P1 and the seven programming verification operations starting from the PV-starting programming pulse P1 are necessary for programming the fastest memory cell with the target threshold voltage Vth1.

[0087] When considering the target threshold voltage Vth2, the programming pulse P 10 The final programming pulse for the fastest memory cell is the initial programming pulse P1. Therefore, a sequence of ten programming pulses starting from the initial programming pulse P1 and six programming verification operations starting from the programming pulse P5 starting from PV are necessary to program the fastest memory cell at the target threshold voltage Vth2.

[0088] When considering the target threshold voltage Vth3, the programming pulse P 12 The final programming pulse for the fastest memory cell is the initial programming pulse P1. Therefore, a sequence of twelve programming pulses starting from the initial programming pulse P1 and eight programming verification operations starting from the programming pulse P7 starting from PV are necessary to program the fastest memory cell at the target threshold voltage Vth3.

[0089] When considering the target threshold voltage Vth4, the programming pulse P 14 It is the final programming pulse of the fastest memory cell, therefore the sequence of fourteen programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV. 10The initial five programming verification operations are necessary for programming the fastest memory cell at the target threshold voltage Vth4;

[0090] When considering the target threshold voltage Vth5, the programming pulse P 17 It is the final programming pulse of the fastest memory cell, therefore the sequence of seventeen programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV. 12 The initial six programming verification operations are necessary for programming the fastest memory cell at the target threshold voltage Vth5;

[0091] When considering the target threshold voltage Vth6, the programming pulse P 19 It is the final programming pulse of the fastest memory cell, therefore the sequence of nineteen programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV. 15 The initial five programming verification operations are necessary for programming the fastest memory cell at the target threshold voltage Vth6; and

[0092] When considering the target threshold voltage Vth7, the programming pulse P 21 It is the final programming pulse of the fastest memory cell, therefore the sequence of twenty-one programming pulses starting from the initial programming pulse P1 and the programming pulse P starting from PV. 17 The initial five programming verification operations are necessary for programming the fastest memory cell at the target threshold voltage Vth7.

[0093] According to an embodiment, the 3D memory device 100 (e.g., memory controller 135 or any other module or circuitry of the 3D memory device 100) is configured to store data for each target threshold voltage Vth. h The indication of the corresponding PV start programming pulse (i.e., the predetermined programming pulse determined during the characterization phase of the 3D memory device 100 based on the above conventional method).

[0094] According to the principles of this disclosure, the memory controller 135 is configured to operate at a target threshold voltage Vth. h Programming the selected memory cells in the reference memory cell string (hereinafter referred to as reference memory cells):

[0095] (i) For the target threshold voltage Vth h The updated PV start programming pulse for initiating the programming verification operation is determined, wherein in the programming pulse sequence, the updated PV start programming pulse follows the PV start programming pulse (i.e., the predetermined PV start programming pulse determined during the characterization phase of the 3D memory device 100), and

[0096] (ii) For the target threshold voltage Vth hEach subsequently selected memory cell, programmed to exhibit (i.e., reasonably exhibit) electrical characteristics similar to the reference memory cell (hereinafter referred to as the similar memory cell), performs a programming verification operation based on the updated PV start programming pulse.

[0097] According to an embodiment, by targeting each target threshold voltage Vth h The iterative step (i) yields an updated PV scheme for the reference memory cell, which includes a scheme for each target threshold voltage Vth. h The corresponding updated PV start programming pulse is used to program each subsequently selected similar memory cell (i.e., each subsequently selected memory cell is similar to the reference memory cell, including the reference memory cell itself).

[0098] According to an embodiment, a plurality of reference memory cells are provided. According to an embodiment, this is achieved by targeting each target threshold voltage Vth. h Furthermore, for each iterative step (i) of the reference memory cell, multiple updated PV schemes are obtained. Each updated PV scheme is associated with a corresponding reference memory cell and includes a specific approach for each target threshold voltage Vth. h The corresponding updated PV start programming pulse is to be used to program each subsequently selected similar memory cell (i.e., each subsequently selected memory cell is similar to the corresponding reference memory cell, including the corresponding reference memory cell itself).

[0099] According to an embodiment, similar memory cells may include memory cells associated with the same word line as the reference memory cell (in addition to the reference memory cell itself). In this embodiment, the reference memory cell may include all memory cells in a reference memory cell string, thus providing an updated PV scheme with the same number of memory cells as each memory cell string.

[0100] Unlike known 3D memory devices in the art, where a fixed PV start programming pulse is set for all memory cells belonging to the same ISPP memory cell group based on the fastest memory cell in the ISPP memory cell group (i.e., a predetermined PV start programming pulse determined during the characterization phase of the 3D memory device 100), the 3D memory device 100 according to this disclosure allows unnecessary programming verification operations to be avoided for slower memory cells, thereby reducing programming time: in fact, as better understood below in the description of the updated PV scheme, for each target threshold voltage Vth h Compared to the PV scheme, which uses a predetermined PV start programming pulse for a slower memory cell, many programming verification operations can be avoided, saved, or skipped.

[0101] According to an embodiment, a similar memory cell may include (in addition to the reference memory cell itself) memory cells associated with one or more word lines that are different from the word lines associated with the reference memory cell. By way of example only, a similar memory cell may include (in addition to the reference memory cell itself) memory cells associated with one or more adjacent word lines that are adjacent to the word line associated with the reference memory cell. In this embodiment, the reference memory cell may include a subset of memory cells in a string of reference memory cells, thus allowing for a smaller number of updated PV schemes than the number of memory cells in each string of memory cells: this allows for further reduction in programming time (where a single updated PV scheme must be accessed when selecting similar memory cells associated with different word lines).

[0102] According to an embodiment, for each memory block, the reference memory cell string includes the initial memory cell string of the memory block (memory cell string 115 in the example discussed). 1，1 ).

[0103] According to an embodiment, for each memory block, the reference memory cell string includes the memory cell string that is first programmed in the memory block (i.e., the memory cell string to which the first selected memory cell to be programmed belongs).

[0104] Assume the PV scheme associated with the reference memory cell is Figure 2A The PV scheme (where, as described above, for each target threshold voltage Vth) h PV scheme associated with reference memory cell ( Figure 2A ) and the fastest PV solution ( Figure 2B In the initial selection of memory cells for use with the target threshold voltage Vth h The selected memory cells are programmed with the same predetermined PV start programming pulse. In this case:

[0105] When considering the target threshold voltage Vth1, the final programming pulse P9 of the reference memory cell is after the final programming pulse P7 of the fastest memory cell (i.e., the reference memory cell is slower than the fastest memory cell when programming with the target threshold voltage Vth1).

[0106] When considering the target threshold voltage Vth2, the final programming pulse P of the reference memory cell 12 In the final programming pulse P of the fastest memory cell 10 Then (i.e., when programming with the target threshold voltage Vth2, the reference memory cell is slower than the fastest memory cell);

[0107] When considering the target threshold voltage Vth3, the final programming pulse P of the reference memory cell 14 In the final programming pulse P of the fastest memory cell 12 Then (i.e., when programming with the target threshold voltage Vth3, the reference memory cell is slower than the fastest memory cell);

[0108] When considering the target threshold voltage Vth4, the final programming pulse P of the reference memory cell 16 In the final programming pulse P of the fastest memory cell 14 Then (i.e., when programming with the target threshold voltage Vth4, the reference memory cell is slower than the fastest memory cell);

[0109] When considering the target threshold voltage Vth5, the final programming pulse P of the reference memory cell 19 In the final programming pulse P of the fastest memory cell 17 Then (i.e., when programming with the target threshold voltage Vth5, the reference memory cell is slower than the fastest memory cell);

[0110] When considering the target threshold voltage Vth6, the final programming pulse P of the reference memory cell 21 In the final programming pulse P of the fastest memory cell 19 Then (i.e., when programming at the target threshold voltage Vth6, the reference memory cell is slower than the fastest memory cell); and

[0111] When considering the target threshold voltage Vth7, the final programming pulse P of the reference memory cell 22 In the final programming pulse P of the fastest memory cell 21 Then (i.e., when programming with the target threshold voltage Vth7, the reference memory cell is slower than the fastest memory cell).

[0112] Figure 2C An updated PV scheme that can be obtained by the memory controller 135 based on the above situation is shown (where each "X" symbol represents a corresponding "saved" or avoided" programming verification operation relative to the PV scheme associated with the reference (slower) memory cell). Specifically, in the considered updated PV scheme:

[0113] When the target threshold voltage Vth1 is taken into account, the updated PV start programming pulse is programming pulse P5 (instead of the predetermined programming pulse P1). Therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth1 according to the updated PV scheme, four programming verification operations can be saved, avoided, or skipped.

[0114] When the target threshold voltage Vth2 is taken into account, the updated PV start programming pulse is programming pulse P8 (instead of the predetermined programming pulse P5). Therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth2 according to the updated PV scheme, three programming verification operations can be saved, avoided, or skipped.

[0115] When considering the target threshold voltage Vth3, the updated PV start programming pulse is the programming pulse P. 10 (Instead of the predetermined programming pulse P7), therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth3 according to the updated PV scheme, three programming verification operations can be saved, avoided, or skipped.

[0116] When considering the target threshold voltage Vth4, the updated PV start programming pulse is the programming pulse P. 12 (instead of the pre-programmed pulse P) 10 Therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth4 according to the updated PV scheme, two programming verification operations can be saved, avoided, or skipped.

[0117] When considering the target threshold voltage Vth5, the updated PV start programming pulse is the programming pulse P. 15 (instead of the pre-programmed pulse P) 12 Therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth5 according to the updated PV scheme, three programming verification operations can be saved, avoided, or skipped.

[0118] When considering the target threshold voltage Vth6, the updated PV start programming pulse is the programming pulse P. 17 (instead of the pre-programmed pulse P) 15 Therefore, when programming each subsequently selected similar memory cell according to the updated PV scheme at the target threshold voltage Vth6, two programming verification operations can be saved, avoided, or skipped; and

[0119] When considering the target threshold voltage Vth7, the updated PV start programming pulse is the programming pulse P. 18 (instead of the pre-programmed pulse P) 17 Therefore, when programming each subsequently selected similar memory cell with the target threshold voltage Vth7 according to the updated PV scheme, a programming verification operation can be saved, avoided, or skipped.

[0120] According to the embodiments, such as Figure 2C The updated PV scheme is shown, for each target threshold voltage Vth hIn the programming pulse sequence, the updated PV start programming pulse precedes the final programming pulse of the reference memory cell by a predetermined number of programming pulses. According to an embodiment, the predetermined number of programming pulses may be a planned number of programming pulses. According to an embodiment, the predetermined number of programming pulses may be a predetermined number of programming pulses determined during the characterization phase. According to an embodiment, the predetermined number of programming pulses may be set or changed externally by a user (e.g., via an external command on the data bus). In the example shown, for each target threshold voltage Vth... h In the programming pulse sequence, the updated PV starts programming five pulses ahead of the final programming pulse of the reference memory cell, and specifically:

[0121] When considering the target threshold voltage Vth1, the updated PV start programming pulse P5 precedes the final programming pulse P9 of the reference memory cell by five programming pulses.

[0122] When considering the target threshold voltage Vth2, the updated PV start programming pulse P8 is different from the final programming pulse P of the reference memory cell. 12 Leading by five programming pulses;

[0123] When considering the target threshold voltage Vth3, the updated PV begins programming the pulse P. 10 The final programming pulse P of the reference memory cell 14 Leading by five programming pulses;

[0124] When considering the target threshold voltage Vth4, the updated PV begins programming the pulse P. 12 The final programming pulse P of the reference memory cell 16 Leading by five programming pulses;

[0125] When considering the target threshold voltage Vth5, the updated PV begins programming the pulse P. 15 The final programming pulse P of the reference memory cell 19 Leading by five programming pulses;

[0126] When considering the target threshold voltage Vth6, the updated PV begins programming the pulse P. 17 The final programming pulse P of the reference memory cell 21 Leading by five programming pulses; and

[0127] When considering the target threshold voltage Vth7, the updated PV begins programming the pulse P. 18 The final programming pulse P of the reference memory cell 22 Leading by five programming pulses.

[0128] According to an embodiment, the predetermined number of programming pulses may be the same for all memory cells of the 3D memory device 100.

[0129] According to an embodiment, for each ISPP memory cell group (i.e., for each memory cell group having the same ISPP voltage step), a predetermined number of programming pulses can be the same: in other words, in this embodiment, a plurality of predetermined number of programming pulses can be set, each predetermined number of programming pulses being associated with a corresponding ISPP memory cell group.

[0130] Figure 3 An operational diagram of method 300 according to an embodiment of the present disclosure is shown.

[0131] According to an embodiment, method 300 includes: selecting a target threshold voltage Vth. h When programming a memory cell (operation node 305), it is checked whether the selected memory cell is a reference memory cell (decision node 310), that is, whether the selected memory cell belongs to the reference memory cell string. As mentioned above, for each memory block, the reference memory cell string may include the initial memory cell string of the memory block, or the memory cell string first programmed in the memory block.

[0132] According to an embodiment, method 300 includes: if the selected memory cell is not a reference memory cell (the branch of decision node 310 is "No"), then checking the target threshold voltage Vth. h Whether the updated PV start programming pulse (or more generally, the updated PV scheme) has been associated with the selected memory cell (decision node 315), i.e., for the target threshold voltage Vth. h The method checks whether an updated PV start programming pulse has been determined for a reference memory cell that exhibits (i.e., reasonably exhibits) electrical characteristics similar to the selected memory cell. Otherwise, method 300 includes, at decision node 315: targeting the target threshold voltage Vth h Check whether an updated PV start programming pulse (or more generally, an updated PV scheme) has been determined for the reference memory cell, and the selected memory cell is a similar memory cell relative to the reference memory cell.

[0133] According to an embodiment, method 300 includes: if there is no target threshold voltage Vth h If the selected memory cell is associated with an updated PV start programming pulse (the branch of decision node 315 is "No"), then the selected memory cell is programmed based on the predetermined PV start programming pulse and the corresponding programming verification operation is performed (operation node 320).

[0134] According to an embodiment, method 300 includes: if a target threshold voltage Vth exists... h If the selected memory cell is associated with an updated PV start programming pulse (the branch of decision node 315 is "yes"), then the selected memory cell is programmed based on the updated PV start programming pulse (i.e., by starting the corresponding programming verification operation from the updated PV start programming pulse) (operation node 325).

[0135] According to an embodiment, method 300 includes: if the selected memory cell is a reference memory cell (the branch of decision node 310 is "yes"), then checking the target threshold voltage Vth. h Whether the updated PV start programming pulse (or more generally, the updated PV scheme) has been used for the selected memory cell (decision node 330), i.e., for the target threshold voltage Vth. h Check whether the updated PV start programming pulse has been determined for the selected reference memory cell.

[0136] According to an embodiment, method 300 includes: if the updated PV starts programming pulse with a target threshold voltage Vth h If the selected reference memory cell is associated with the decision node 330 (the branch is "yes"), then the selected reference memory cell is programmed based on the updated PV programming pulse (operation node 325).

[0137] According to an embodiment, method 300 includes: if the updated PV start programming pulse does not coincide with the target threshold voltage Vth h If the selected reference memory cell is associated with the decision node 330 (the branch of decision node 330 is "No"), then the selected memory cell is programmed based on the predetermined PV start programming pulse and the corresponding programming verification operation is performed (i.e., the corresponding programming verification operation is started from the predetermined PV start programming pulse) (operation node 335).

[0138] According to an embodiment, method 300 includes: targeting a target threshold voltage Vth h Determine the updated PV start programming pulse for the selected reference memory cell (operation node 340) (the updated PV start programming pulse will be used to achieve the target threshold voltage Vth) h (For each subsequently selected similar memory cell in the programming sequence). According to an embodiment, as previously described, the updated PV start programming pulse is determined based on the final programming pulse of the reference memory cell. According to an embodiment, as previously described, in the programming pulse sequence, the updated PV start programming pulse precedes the final programming pulse of the reference memory cell by a predetermined number of programming pulses.

[0139] Figure 4A simplified block diagram of an electronic system 400 according to an embodiment of the present disclosure is shown.

[0140] According to an embodiment, the electronic system 400 includes a 3D memory device 100 (or more). The 3D memory device (100) includes a plurality of memory cell strings, a plurality of word lines, and control circuitry. After a first programming pulse is used as a predetermined programming pulse to initiate a programming verification operation, the control circuitry performs a programming verification operation in response to a corresponding programming pulse. The control circuitry determines an updated first programming pulse based on the result of the programming verification operation. The programming verification operation is performed starting with the updated first programming pulse for each subsequently selected memory cell.

[0141] According to an embodiment, the electronic system 400 may include a controller 405 (e.g., one or more microprocessors and / or one or more microcontrollers). According to an embodiment, one or more microprocessors and / or one or more microcontrollers, or at least a subset thereof, may be embedded in the 3D memory device 100.

[0142] According to an embodiment, the electronic system 400 may include input / output devices 410, such as a screen and / or a keyboard.

[0143] According to an embodiment, the electronic system 400 may include a wireless interface 415 (e.g., one or more antennas and / or one or more wireless transceivers) for wirelessly exchanging messages with a wireless communication network (not shown).

[0144] According to an embodiment, the electronic system 400 may include a power supply device (e.g., a battery) 420 for supplying power to the electronic system 400.

[0145] According to an embodiment, the electronic system 400 may include one or more communication channels (buses) 425 to allow data exchange between the 3D memory device 100, the controller 405 (when provided), the input / output device 410 (when provided), the wireless interface 415 (when provided), and the power supply device 420 (when provided).

[0146] Naturally, those skilled in the art can apply numerous logical and / or physical modifications and alterations to the above teachings to meet local and specific requirements. More specifically, while this disclosure has been described with a degree of particularity with reference to its preferred embodiments, it should be understood that various omissions, substitutions, and changes in form and detail, as well as in other embodiments, are possible. Specifically, different embodiments of this disclosure may even be implemented without the specific details set forth in the foregoing detailed embodiments for providing a more thorough understanding thereof; instead, well-known features may have been omitted or simplified to avoid unnecessary detail from obscuring the description. Furthermore, specific elements and / or method steps explicitly described in connection with any disclosed embodiment of this disclosure may be incorporated into any other embodiment.

[0147] In particular, similar considerations apply if the 3D memory device (and / or the system including the 3D memory device) has a different structure or includes equivalent components. In any case, any of its components can be separated into several elements, or two or more components can be combined into a single element; furthermore, each component can be replicated to support parallel operation of the corresponding operations. It should also be noted that (unless otherwise stated) any interaction between different components generally does not need to be sequential and can be performed directly or indirectly through one or more intermediate media.

Claims

1. A three-dimensional memory device (100), comprising: Multiple memory cell strings (115) n，1 Each memory cell string comprises multiple memory cells (T) stacked on top of each other on a substrate. k Each memory cell is at a corresponding vertical distance from the substrate; Multiple word lines (WL) k Each word line is associated with a corresponding memory cell in the plurality of memory cell strings, which is at the same vertical distance from the substrate; as well as Control circuit (135): (i) Apply an incremental step programming pulse sequence to the selected memory cell of the reference memory cell string to program the selected memory cell at a target threshold voltage among a plurality of target threshold voltages; (ii) After the first programming pulse of the incremental step programming pulse sequence is applied, a programming verification operation is performed in response to a corresponding programming pulse, wherein the first programming pulse for initiating the programming verification operation is a predetermined programming pulse determined by the three-dimensional memory device; (iii) Based on the second programming pulse, determine that another pulse in the incremental step programming pulse sequence is an updated first programming pulse for the selected memory cell and for the target threshold voltage, the second programming pulse being the final programming pulse of the incremental step programming pulse sequence, and after the second programming pulse, a programming verification operation determines that the selected memory cell is programmed with the target threshold voltage; as well as (iv) The programming verification operation is performed starting with the updated first programming pulse of each subsequently selected memory cell, each of which will be programmed at the target threshold voltage and on the same word line as the selected memory cell.

2. The three-dimensional memory device (100) according to claim 1, wherein the control circuit (135) repeats steps (i), (ii), (iii) and (iv) for each of the plurality of target threshold voltages.

3. The three-dimensional memory device (100) according to claim 1, wherein in the incremental step programming pulse sequence, the updated first programming pulse precedes the second programming pulse by a predetermined number of programming pulses.

4. The three-dimensional memory device (100) according to claim 3, wherein the predetermined number of programming pulses is the same for each group of memory cells having the same incremental voltage step between subsequent programming pulses.

5. The three-dimensional memory device (100) according to claim 1, wherein the control circuit (135): starting from the updated first programming pulse, performs the programming verification operation in response to a corresponding programming pulse; and, during the incremental step programming pulse, performs the operation on the same word line (WL) as the selected memory cell. k The above programming verification operation is performed on each subsequently selected memory cell and for each subsequently selected memory cell located on at least one word line different from the same word line.

6. The three-dimensional memory device (100) according to claim 5, wherein at least one word line different from the same word line includes at least one adjacent word line adjacent to the same word line.

7. The three-dimensional memory device (100) according to claim 1, comprising: Multiple storage blocks (110), each storage block comprising a subset of multiple memory cell strings, wherein for each storage block, the reference memory cell string comprises either the initial memory cell string of the storage block or the memory cell string first programmed in the storage block.

8. The three-dimensional memory device (100) according to claim 1, wherein the control circuit (135) repeats steps (i), (ii), (iii) and (iv) for each of at least one additionally selected memory cell in the reference memory cell string.

9. The three-dimensional memory device (100) according to claim 1, wherein the memory unit (T) k Each of the units in the array is a single-level memory cell or a multi-level memory cell.

10. An electronic system (400) comprising at least one three-dimensional memory device (100) as claimed in claim 1.

11. A method (300) for operating a three-dimensional memory device (100), wherein the three-dimensional memory device comprises: Multiple memory cell strings (115) n，1 Each memory cell string comprises multiple memory cells (T) stacked on top of each other on a substrate. k Each memory cell is positioned at a corresponding vertical distance from the substrate; and multiple word lines (WL) k Each word line is associated with a corresponding memory cell in the plurality of memory cell strings that is at the same vertical distance from the substrate, the method comprising: (i) Apply an incremental step programming pulse sequence to the selected memory cell of the reference memory cell string to program the selected memory cell at a target threshold voltage among a plurality of target threshold voltages (320; 335). (ii) After the first programming pulse of the incremental step programming pulse sequence is applied, a programming verification operation is performed in response to a corresponding programming pulse (320; 335), wherein the first programming pulse for initiating the programming verification operation is a predetermined programming pulse determined by the three-dimensional memory device; (iii) Based on the second programming pulse, determine that another pulse in the incremental step programming pulse sequence is an updated first programming pulse for the selected memory cell and for the target threshold voltage, the second programming pulse being the final programming pulse of the incremental step programming pulse sequence, and after the second programming pulse, a programming verification operation determines that the selected memory cell is programmed with the target threshold voltage (340); and (iv) The programming verification operation is performed starting from the updated first programming pulse of each subsequently selected memory cell, each of which will be programmed at the target threshold voltage and on the same word line (325) as the selected memory cell.

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