Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a substrate, the substrate is provided with vertically stacked multiple spaced channel layers, the channel layers are sequentially provided with dielectric layers and first barrier layers, the dielectric layers cover the channel layers, and the first barrier layers cover the dielectric layers; forming a second barrier layer containing silicon, the second barrier layer covers the first barrier layer, and the material of the second barrier layer further comprises one or more of titanium, tantalum or nitrogen; and performing heat treatment, so that the silicon in the second barrier layer is combined with the first barrier layer to play a blocking role. The characteristic that the second barrier layer is not easy to be crystallized and aggregated can prevent the second barrier layer from closing the channel between the adjacent channel layers in the heat treatment process, thereby solving the problem that there is residual in the space between the channel layers.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] With the advancement of technology nodes, GAA (gate all around) structures have begun to be used in MOS transistors. Nanosheet / wire-GAA FETs are key devices that can effectively replace FinFETs (Fin Field-Effect Transistors) after the 3nm node, and can significantly suppress short-channel effects and improve the current drive performance of the device.

[0003] In the traditional GAA HKMG (high-K metal gate) process, PCA (post high-K capping anneal) treatment is required after A-Si deposition to improve reliability. Figure 1 This is a schematic diagram of the structure of a semiconductor device, such as... Figure 1 As shown, the semiconductor device includes a substrate 10, on which a plurality of vertically stacked, spaced-apart channel layers 20 are formed. Each channel layer 20 is sequentially coated with a dielectric layer 21, a barrier layer 22, and an A-Si layer (not shown), followed by PCA processing. However, the PCA process leads to the following problems: 1. Because A-Si crystallizes and agglomerates at the high temperature of PCA, the crystallized and agglomerated Si is difficult to remove. 2. The spacing between the channel layers 20 is relatively close; after wet etching removes A-Si, A-Si may remain between the layers, such as... Figure 1 The A-Si layer is 23mm thick. Unremovable A-Si will prevent the corresponding location from being filled with a metal gate during subsequent processes, and if etching is intensified, it may damage other structural layers.

[0004] Therefore, it is necessary to provide a method for fabricating semiconductor devices to solve the problem of residues existing in the gaps between channel layers. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, in order to solve the problem of residual material existing in the gaps between channel layers.

[0006] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] A substrate is provided, on which a plurality of vertically stacked, spaced-apart channel layers are formed, and a dielectric layer and a first barrier layer are sequentially formed on the channel layers, wherein the dielectric layer covers the channel layers and the first barrier layer covers the dielectric layer.

[0008] A second barrier layer containing silicon is formed, the second barrier layer covering the first barrier layer, and the material of the second barrier layer further includes one or more of titanium, tantalum, or nitrogen; and,

[0009] Heat treatment is performed to combine the silicon in the second barrier layer with the first barrier layer to achieve a barrier effect.

[0010] Optionally, the first barrier layer is made of titanium nitride, and the second barrier layer is made of titanium silicon nitride.

[0011] Optionally, after the heat treatment, the manufacturing method further includes: thinning the second barrier layer to the desired thickness.

[0012] Optionally, prior to the heat treatment, the fabrication method further includes: forming a sacrificial layer that covers the substrate and the second barrier layer, wherein the gap between adjacent channel layers is not filled by the sacrificial layer;

[0013] After the heat treatment, the manufacturing method further includes removing the sacrificial layer.

[0014] Optionally, the sacrificial layer may be made of silicon.

[0015] Optionally, the sacrificial layer may be formed using physical vapor deposition.

[0016] Optionally, the sacrificial layer may be removed by wet etching, wherein the etchant used in the wet etching includes NH4OH.

[0017] Optionally, the heat treatment includes PCA treatment.

[0018] Optionally, the second barrier layer is formed by atomic layer deposition and thinned by atomic layer etching.

[0019] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0020] This invention provides a semiconductor device and its fabrication method. First, a substrate is provided on which a plurality of vertically stacked, spaced-apart channel layers are formed. A dielectric layer and a first barrier layer are sequentially formed on each channel layer, with the dielectric layer covering the channel layer and the first barrier layer covering the dielectric layer. Next, a silicon-containing second barrier layer is formed, covering the first barrier layer. The material of the second barrier layer further includes one or more of titanium, tantalum, or nitrogen. Then, heat treatment is performed to combine the silicon in the second barrier layer with the first barrier layer to achieve a barrier effect. This invention uses the second barrier layer instead of the existing A-Si layer. The second barrier layer plays the same role in the semiconductor device as the A-Si layer, and its resistance to crystallization and aggregation prevents it from blocking the channels between adjacent channel layers during heat treatment, thus solving the problem of residual material remaining between channel layers.

[0021] Furthermore, due to the characteristic that the second barrier layer is not prone to crystallization and agglomeration, the generation of residues can be avoided when the second barrier layer is subsequently thinned.

[0022] Furthermore, a sacrificial layer is formed before heat treatment, covering the substrate and the second barrier layer to prevent damage to the second barrier layer during subsequent heat treatment. The sacrificial layer is formed using physical vapor deposition (PVD). Due to the poor filling capability of PVD, the gaps between adjacent channel layers are not filled by the sacrificial layer, making it easier to remove it completely and avoiding sacrificial layer residue. Additionally, the vacuum environment provided by PVD further protects the second barrier layer from cracking or other problems during heat treatment. Attached Figure Description

[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0024] Figure 1 This is a schematic diagram of the structure of a semiconductor device.

[0025] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0026] Figures 3 to 4 This is a schematic diagram of the structure of each step of the semiconductor device fabrication method provided in Embodiment 1 of the present invention.

[0027] Figures 5 to 6 This is a schematic diagram of the structure of each step of the semiconductor device fabrication method provided in Embodiment 2 of the present invention.

[0028] Figure 1 middle,

[0029] 10-Substrate, 20-Channel layer, 21-Dielectric layer, 22-Barrier layer, 23-A-Si;

[0030] Figures 3-6 middle,

[0031] 100 - Substrate, 200 - Channel layer, 210 - Dielectric layer, 220 - First barrier layer, 230 - Second barrier layer, 240 - Sacrificial layer. Detailed Implementation

[0032] exist Figure 1 In the semiconductor device shown, after A-Si deposition, PCA is performed. The silicon in A-Si combines with the barrier layer 22 (preferably made of titanium nitride) to act as a barrier against metals such as aluminum and improve the stability of the dielectric layer 21. However, because A-Si crystallizes and agglomerates at the high temperature of PCA, residues are generated in the gaps between the channel layers.

[0033] To address the above problems, the present invention provides a semiconductor device and a method for manufacturing the same.

[0034] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0035] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0036] Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0037] like Figure 2As shown, the method for fabricating the semiconductor device includes the following steps:

[0038] S1: A substrate is provided, on which a plurality of vertically stacked, spaced-apart channel layers are formed, and a dielectric layer and a first barrier layer are sequentially formed on the channel layers, wherein the dielectric layer covers the channel layers and the first barrier layer covers the dielectric layer.

[0039] S2: Form a silicon-containing second barrier layer, the second barrier layer covering the first barrier layer, and the material of the second barrier layer further includes one or more of titanium, tantalum or nitrogen;

[0040] S3: Perform heat treatment to combine the silicon in the second barrier layer with the first barrier layer to achieve a blocking effect.

[0041] Figures 3 to 4 This is a schematic diagram of the structure of each step in the method for fabricating a semiconductor device provided in Embodiment 1 of the present invention. Figures 5 to 6 This is a schematic diagram of the structure of each step in the method for fabricating a semiconductor device according to Embodiment 2 of the present invention. Next, we will combine... Figure 2 and Figures 3-6 The method for fabricating the semiconductor device provided by the present invention will be described in detail through two embodiments.

[0042] Example 1

[0043] In step S1, please refer to Figure 3 As shown, a substrate 100 is provided, on which a plurality of vertically stacked, spaced-apart channel layers 200 are formed. A dielectric layer 210 and a first barrier layer 220 are sequentially formed on the channel layers. The dielectric layer 210 covers the channel layers 200, and the first barrier layer 220 covers the dielectric layer 210.

[0044] The substrate 100 can be made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 100 is preferably made of silicon.

[0045] The channel layer 200 can be a nanowire, a nanosheet, or other shapes. The thickness of multiple channel layers 200 can be the same or different, and the spacing between adjacent channel layers 200 can be the same or different.

[0046] The dielectric layer 210 is preferably an HK dielectric layer. Before forming the HK dielectric layer, an interface layer (IL) may be formed, which covers the channel layer, and the HK dielectric layer covers the interface layer. The material of the interface layer (IL) may include materials such as silicon nitride, or other suitable materials, such as silicon oxynitride. The interface layer may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. The material of the HK dielectric layer may include tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2), etc., preferably hafnium oxide. The HK dielectric layer may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some implementations, ALD (Atomic Layer Deposition) may be preferred, in which a film is grown on the surface by exposing its surface to alternating gaseous substances (commonly referred to as precursors). The ALD process has the advantage of forming a highly uniform and precise HK dielectric layer on the substrate surface. The first barrier layer 220 is preferably made of TiN, but is not limited thereto. The first barrier layer 220 is preferably formed using atomic layer deposition (ALD), but is not limited thereto.

[0047] In one embodiment of the present invention, after the dielectric layer 210 is formed, a heat treatment is performed, preferably a PDA (post-High-K deposition anneal) treatment.

[0048] In another embodiment of the present invention, after the first barrier layer 220 is formed, a heat treatment is performed, preferably a PMA (post-metal annealing) treatment.

[0049] In another embodiment of the present invention, after the dielectric layer 210 is formed, a heat treatment is performed, preferably a PDA treatment, and after the first barrier layer 220 is formed, a heat treatment is performed again, preferably a PMA treatment.

[0050] The PMA treatment involves introducing ammonia (NH3) under nitrogen (N2), argon (Ar), or helium (He) protection to improve the interfacial state characteristics of the first barrier layer 220. Preferably, the PMA treatment includes a Soak stage and a Spike stage, with the temperature of the Soak stage between 500°C and 700°C, and the temperature of the Spike stage between 700°C and 1000°C, but not limited thereto.

[0051] In step S2, please refer to Figure 4 As shown, a silicon-containing second barrier layer 230 is formed, which covers the first barrier layer 220, and the material of the second barrier layer 230 also includes one or more of titanium, tantalum or nitrogen.

[0052] The second barrier layer 230 is made of one or more of titanium, tantalum, or nitrogen, in addition to silicon, and its material characteristics include that it is not prone to crystallization and agglomeration after heat treatment. In this embodiment, preferably, the material of the second barrier layer 23 includes titanium silicon nitride (TiSiN), but it is not limited to this.

[0053] In step S3, please continue to refer to Figure 4 As shown, heat treatment is performed to combine the silicon in the second barrier layer 230 with the first barrier layer 220 to achieve a blocking effect.

[0054] In this embodiment, the heat treatment is PCA (post high-K capping anneal). The PCA treatment is performed in a protective gas atmosphere such as nitrogen (N2), argon (Ar), oxygen (O2), or helium (He). Preferably, the PCA treatment includes a Soak stage and a Spike stage. The temperature of the Soak stage is between 500℃ and 700℃, and the temperature of the Spike stage is between 700℃ and 1000℃, but it is not limited to these.

[0055] After the heat treatment, the silicon in the second barrier layer 230 combines with the first barrier layer 220 to provide a barrier function, such as blocking the metal in the subsequently formed metal gate, primarily blocking aluminum. Furthermore, the heat treatment improves the stability of the dielectric layer 210 film, enhancing the reliability of the semiconductor device. In this invention, the second barrier layer 230 replaces the A-Si used in the prior art. The second barrier layer 230 plays the same role in the semiconductor device as the A-Si, and its resistance to crystallization and aggregation prevents it from blocking the channels between adjacent channel layers 20 during heat treatment. This solves the problem of residual material remaining between channel layers 20 in the prior art, preventing the semiconductor device's electrical properties from failing to meet standards or exhibiting excessive fluctuations.

[0056] In addition, the second barrier layer 230 is made of titanium silicon nitride, and the first barrier layer 220 is made of titanium nitride. In semiconductor devices, titanium silicon nitride can replace a portion of titanium nitride, thereby reducing the thickness of titanium nitride and thus reducing the budget for heat treatment. Here, heat treatment refers to the heat treatment performed after the formation of the first barrier layer 220.

[0057] It should be noted that, in this embodiment, in order to avoid damage to the second barrier layer 230 during the heat treatment process, the thickness of the second barrier layer 230 formed in step S2 is greater than the actual required thickness.

[0058] Therefore, in this embodiment, after the heat treatment, the fabrication method further includes thinning the second barrier layer 230 to the desired thickness. Atomic layer etching (ALE) can be used to uniformly thin the second barrier layer 230 to the desired thickness, but this method is not limited to it. Because the second barrier layer 230 is not prone to crystallization and agglomeration, the generation of residues can be avoided when thinning the second barrier layer 230.

[0059]

Example 2

[0060] Compared with Embodiment 1, this embodiment does not require thinning of the thickness of the second barrier layer.

[0061] In this embodiment, after performing step S2 and before performing step S3, the fabrication method further includes: forming a sacrificial layer, the sacrificial layer covering the substrate and the second barrier layer, wherein the gap between adjacent channel layers is not filled by the sacrificial layer. After performing step S3, the fabrication method further includes: removing the sacrificial layer.

[0062] For specific details on the steps involved in forming the sacrificial layer, please refer to [link / reference]. Figure 5As shown, a sacrificial layer 240 is formed, which covers the substrate 100 and the second barrier layer 230, and the gap between adjacent channel layers 200 is not filled by the sacrificial layer 240.

[0063] In this embodiment, the sacrificial layer 240 is preferably made of silicon, but is not limited thereto. The sacrificial layer 240 can be formed using physical vapor deposition (PVD), or other methods known to those skilled in the art can be used to form the sacrificial layer 240.

[0064] The sacrificial layer 240 covers the second barrier layer 230, protecting it and preventing damage from subsequent heat treatment. Therefore, in this embodiment, the thickness of the second barrier layer 230 does not need to be excessive; it only needs to reach the required thickness after heat treatment, without requiring a thinning step.

[0065] Because physical vapor deposition (PVD) has relatively poor filling capability, the sacrificial layer 240 may cover the second barrier layer 230 without filling the gaps between adjacent channel layers 200, or may only slightly fill the gaps between adjacent channel layers 200. Therefore, the sacrificial layer 240 is easier to remove subsequently. Furthermore, the vacuum environment provided by PVD further protects the second barrier layer 230 from cracking or other problems during subsequent heat treatment.

[0066] Please refer to the steps for removing the sacrificial layer. Figure 6 As shown, the sacrificial layer 240 is removed.

[0067] The preferred removal process for the sacrificial layer 240 is a wet etching process, wherein the etchant used in the wet etching process includes, but is not limited to, NH4OH solution. Because the sacrificial layer 240 has poor filling capacity and does not fill the gaps between the channel layers 200, the wet etching process can easily remove the sacrificial layer 240 completely, leaving no residue in the gaps between the channel layers 200.

[0068] Accordingly, the present invention also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.

[0069] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, on which a plurality of vertically stacked, spaced-apart channel layers are formed, and a dielectric layer and a first barrier layer are sequentially formed on the channel layers, wherein the dielectric layer covers the channel layers and the first barrier layer covers the dielectric layer. A second barrier layer containing silicon is formed, the second barrier layer covering the first barrier layer, and the material of the second barrier layer further includes one or more of titanium, tantalum, or nitrogen; and, Heat treatment is performed to combine the silicon in the second barrier layer with the first barrier layer to achieve a barrier effect.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The first barrier layer is made of titanium nitride, and the second barrier layer is made of titanium silicon nitride.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, After the heat treatment, the manufacturing method further includes: thinning the second barrier layer to the desired thickness.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, Prior to the heat treatment, the fabrication method further includes: forming a sacrificial layer that covers the substrate and the second barrier layer, wherein the gap between adjacent channel layers is not filled by the sacrificial layer; After the heat treatment, the manufacturing method further includes removing the sacrificial layer.

5. The method for fabricating a semiconductor device as described in claim 4, characterized in that, The sacrificial layer is made of silicon.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The sacrificial layer was formed using physical vapor deposition.

7. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The sacrificial layer is removed by wet etching, wherein the etchant used in the wet etching includes NH4OH.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The heat treatment includes PCA treatment.

9. The method for fabricating a semiconductor device as described in claim 3, characterized in that, The second barrier layer is formed by atomic layer deposition and then thinned by atomic layer etching.

10. A semiconductor device, characterized in that, It is manufactured using the method for manufacturing a semiconductor device as described in any one of claims 1 to 9.

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