3D fan-out package structure and preparation method

Abstract

The application provides a 3D fan-out packaging structure and a preparation method, which comprise a rewiring layer, a conductive column, an intermediate chip, a first plastic encapsulation material layer, an electric connection structure and a solder ball bump array, a bottom chip and a second plastic encapsulation material layer. The electric connection structure comprises stacked electric connection layers, and the problem that aluminum is difficult to fill in a via with a 10:1 aspect ratio is solved in a layered manner. The vertical electric connection from top to bottom can reduce the resistance and the signal delay. The bottom chip further comprises a passive element. When power is lost, the passive element is discharged to protect the data from being damaged. The electric connection structure manufactured by the damascene process considers the global and local planarization of the chip, further reduces the resistance and the signal delay, is suitable for various metals, can use the metal with excellent electric performance to solve the bottleneck problem, the metal wire width and spacing is less than 0.1 mu m, so that more chips can be packaged, more input / output interfaces are provided, the packaging size is reduced, and the demand for high-performance chips is met.

Description

Technical Field

[0001] This invention relates to a semiconductor packaging structure and its fabrication method, and particularly to a 3D fan-out packaging structure and its fabrication method. Background Technology

[0002] With the ever-increasing performance requirements of high-performance computing (HPC) chips such as CPUs, GPUs, and FPGAs, traditional packaging technologies such as flip-chip (FC) and point-of-purchase (POP) packaging can no longer meet the demands, leading to a growing need for 2.5D / 3D packaging technologies. The principle of 3DFO packaging is to fabricate a transistor (CMOS) structure on the chip and directly connect the electronic signals of different chips using through-silicon vias, thereby enabling the vertical stacking of memory chips or other chips.

[0003] The biggest technical challenge of 3DFO packaging is directly fabricating silicon vias on the chip to achieve top and bottom interconnects. As semiconductor manufacturing processes enter the 0.18-micron era, back-end aluminum interconnect technology has encountered significant bottlenecks, including increased signal delay, electromigration, and the difficulty of depositing aluminum in vias with a 10:1 aspect ratio. Therefore, we should continuously optimize and improve existing process technologies to enhance chip performance and solve these technical challenges and bottlenecks. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a 3D fan-out packaging structure and manufacturing method to solve the problems of increased signal delay, electromigration, and difficulty in padding aluminum in vias with a 10:1 aspect ratio in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a 3D fan-out packaging structure, the 3D fan-out packaging structure comprising:

[0006] A rewiring layer, comprising a first surface and a second surface disposed opposite to each other;

[0007] A conductive post, the conductive post being located on the first surface of the redistribution layer and electrically connected to the redistribution layer;

[0008] An intermediate chip, the intermediate chip being bonded to the first surface of the redistribution layer, and the front side of the intermediate chip being away from the redistribution layer;

[0009] A first molding compound layer covers the conductive pillars, the intermediate chip, and the redistribution layer, and exposes the top surfaces of the conductive pillars and the intermediate chip.

[0010] An electrical connection structure and a solder ball bump array are provided. The electrical connection structure is located on the surface of the first molding compound layer away from the redistribution layer. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar and the intermediate chip. The solder ball bump array is located on the electrical connection structure and is electrically connected to the metal pillar.

[0011] A bottom chip, the bottom chip being located on the second surface of the redistribution layer and electrically connected to the redistribution layer;

[0012] A second molding compound layer covers the redistribution layer and the bottom chip.

[0013] Preferably, the redistribution layer includes a dielectric layer and a metal wiring layer located inside the dielectric layer.

[0014] Preferably, the electrical connection structure and the solder ball bump array constitute a 4P4M structure, including four sub-dielectric layers, three sub-metal connection layers penetrating within the sub-dielectric layers, and a top-level sub-metal connection layer consisting of the solder ball bump array and a metallization layer located below the solder ball bump array, wherein the linewidth of the metal interconnects in the sub-metal connection layers of the 4P4M layer and / or the spacing between adjacent metal interconnects is less than 0.1 μm.

[0015] Preferably, the bottom chip further includes passive components, which include one or a combination of capacitors, inductors, and resistors.

[0016] Preferably, the upper surface of the bottom chip is provided with soldering microbumps, and the bottom chip is electrically connected to the redistribution layer through the soldering microbumps.

[0017] Preferably, an underfill adhesive is further used to fill the space between the redistribution layer and the bottom chip.

[0018] Meanwhile, the present invention provides a method for fabricating a 3D fan-out packaging structure, the method comprising the following steps:

[0019] S1. A first substrate is provided and a separation layer is formed on the first substrate, and a redistribution layer is formed on the separation layer, the redistribution layer including a first surface and a second surface disposed opposite to each other;

[0020] S2. A conductive pillar is formed on the first surface of the redistribution layer, the conductive pillar is electrically connected to the redistribution layer, and the intermediate chip is bonded to the first surface of the redistribution layer with the front side facing up.

[0021] S3. A first molding compound layer is formed on the first surface of the redistribution layer, the first molding compound layer covering the conductive pillar, the intermediate chip and the redistribution layer, and exposing the top surfaces of the conductive pillar and the intermediate chip;

[0022] S4. An electrical connection structure is fabricated on the first molding compound layer using a damascus embedding process. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar and the intermediate chip. A solder ball bump array is formed on the electrical connection structure. The solder ball bump array is electrically connected to the metal pillar.

[0023] S5. Provide a second substrate and bond the second substrate to the solder ball bump array, remove the first substrate and the separation layer to expose the second surface of the redistribution layer;

[0024] S6. Etch the second surface of the redistribution layer to expose the metal wiring layer within the redistribution layer, and electrically connect the bottom chip to the redistribution layer.

[0025] S7. A second molding compound layer is formed on the second surface of the redistribution layer, the second molding compound layer covering the redistribution layer and the bottom chip;

[0026] S8. Remove the second substrate.

[0027] Preferably, the step of forming the redistribution layer on the upper surface of the first substrate in S1 includes: first forming a dielectric layer on the upper surface of the first substrate, then forming a metal layer on the surface of the dielectric layer, etching the metal layer to form a metal wiring layer, and finally forming a dielectric layer again on the metal wiring layer.

[0028] Preferably, in step S3, after forming a first molding compound layer on the first surface of the redistribution layer, the step further includes removing a portion of the first molding compound layer above the conductive pillars and the intermediate chip to expose the top surface of the conductive pillars and the intermediate chip.

[0029] Preferably, step S4, which involves fabricating an electrical connection structure on the first molding compound layer using a damascus inlay process and forming a solder ball bump array on the electrical connection structure, includes the following steps:

[0030] 1) A first sub-dielectric layer is formed on the first molding compound layer, and the first sub-dielectric layer is etched to form a first sub-wiring dielectric layer;

[0031] 2) A first metal line layer is formed on the first sub-wiring dielectric layer, and the first metal line layer is in electrical contact with the conductive pillar and the intermediate chip;

[0032] 3) Use chemical mechanical polishing to remove excess metal layers, exposing the first sub-wiring dielectric layer and the first sub-metal interconnect layer formed in the first sub-wiring dielectric layer;

[0033] 4) Repeat steps 1-3 twice to form a 3P3M structure, form a fourth sub-dielectric layer on the 3P3M, and etch the fourth sub-dielectric layer to form a fourth sub-wiring dielectric layer;

[0034] 5) A metallization layer and a solder ball bump array are formed on the fourth sub-wiring dielectric layer.

[0035] As described above, the 3D fan-out packaging structure and manufacturing method of the present invention have the following beneficial effects: The 3D fan-out packaging structure includes a redistribution layer, conductive pillars, an intermediate chip, a first molding compound layer, an electrical connection structure and a solder ball bump array, a bottom chip, and a second molding compound layer. The electrical connection structure includes stacked electrical connection layers, which solves the problem that aluminum is difficult to pad in vias with a 10:1 aspect ratio by layering. The vertical electrical connection of each sub-metal connection layer from top to bottom can reduce resistance and signal delay. The bottom chip also includes passive components. The intermediate chip can be directly controlled through the electrical connection structure and solder ball bump array and the redistribution layer, or the intermediate chip can be controlled after signal processing by the bottom chip. In the event of a sudden power failure, the passive components in the bottom chip can discharge, thereby protecting the data from damage.

[0036] Meanwhile, the electrical connection structure manufactured using the damascus damascene process can achieve both global and local planarization of the chip, further reducing resistance and signal delay, and improving the overall performance of the chip. The damascus damascene process is applicable to various metals, and can use metals with superior electrical performance, such as copper, to solve various bottleneck problems encountered in back-end aluminum interconnect technology. The damascus damascene process can meet the requirement that the metal interconnect linewidth and line spacing be less than 0.1μm, thereby enabling the 3D fan-out packaging structure to package more chips, provide more input / output interfaces, reduce package size, and meet the current demand for high-performance chips. Attached Figure Description

[0037] Figure 1 The flowchart shown is a method for preparing the 3D fan-out packaging structure of the present invention.

[0038] Figures 2-7 show Figure 1 The structural diagrams presented for each step are as follows: Figure 7 Also shown is a schematic diagram of the 3D fan-out packaging structure of the present invention.

[0039] Component designation explanation

[0040] 100 Rerouting Layer

[0041] 110 Dielectric Layer

[0042] 120 Metal Wiring Layer

[0043] 200 conductive pillars

[0044] 300 intermediate chips

[0045] 310 Adhesive Layer

[0046] 301 contact pad

[0047] 400 First molding compound layer

[0048] 500 Electrical connection structure and solder ball bump array

[0049] 510 First Sub-wiring Medium Layer

[0050] 520 First Sub-metal Connector Layer

[0051] 530 Second Sub-metal Connecting Layer

[0052] 540 Third Sub-metallic Connecting Layer

[0053] 550 Fourth Sub-wiring Medium Layer

[0054] 560 metallization layer

[0055] 570 solder ball bump array

[0056] 600 bottom chip

[0057] 610 Welding Micro-protrusions

[0058] 620 bottom filler glue

[0059] 700 Second molding compound layer

[0060] 800 Second Substrate

[0061] 900 First Substrate

[0062] 910 Separation Layer

[0063] Steps S1 to S8 Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] like Figures 1-7 In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure will be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0066] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0068] Example 1

[0069] like Figure 1 As shown, the present invention provides a method for fabricating a 3D fan-out packaging structure, which includes the following steps:

[0070] S1. A first substrate 900 is provided and a separation layer 910 is formed on the first substrate 900. A redistribution layer 100 is formed on the separation layer. The redistribution layer 100 includes a first surface and a second surface disposed opposite to each other.

[0071] S2. A conductive post 200 is formed on the first surface of the redistribution layer 100, the conductive post 200 is electrically connected to the redistribution layer 100, and the intermediate chip 300 is bonded to the first surface of the redistribution layer 100 with the front side facing up.

[0072] S3. A first molding compound layer 400 is formed on the first surface of the redistribution layer 100. The first molding compound layer 400 covers the conductive pillar 200, the intermediate chip 300 and the redistribution layer 100, and exposes the top surfaces of the conductive pillar 200 and the intermediate chip 300.

[0073] S4. An electrical connection structure is fabricated on the first molding compound layer 400 using a damascus inlay process. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar 200 and the intermediate chip 300. A solder ball bump array is formed on the electrical connection structure. The solder ball bump array is electrically connected to the metal pillar.

[0074] S5. Provide a second substrate 800 and bond the second substrate 800 to the solder ball bump array, remove the first substrate 900 and the separation layer 910 to expose the second surface of the redistribution layer 100;

[0075] S6. Etch the second surface of the redistribution layer 100 to expose the metal wiring layer 120 within the redistribution layer 100, and electrically connect the bottom chip 600 to the redistribution layer 100.

[0076] S7. A second molding compound layer 700 is formed on the second surface of the redistribution layer 100, the second molding compound layer covering the redistribution layer 100 and the bottom chip 600;

[0077] S8. Remove the second substrate 800.

[0078] like Figure 1 Step S1 in the middle and Figure 2 As shown, a first substrate 900 is provided. The first substrate 900 can be one of a semiconductor substrate, a glass substrate, a ceramic substrate, a polymer substrate, and a metal substrate. The first substrate 900 provides a supporting plane for the subsequent packaging structure to prevent problems such as cracking, breakage, and warping of the semiconductor chip during subsequent fabrication. It needs to be removed later. In this embodiment, a relatively low-cost glass substrate is used. A separation layer is easily formed on the glass substrate, and the subsequent peeling process is also relatively convenient.

[0079] The separation layer 910 serves as a base for forming the redistribution layer 100 and other structures, and is therefore preferably made of an adhesive material with a smooth surface. Furthermore, since the separation layer 910 and the first substrate 900 need to be removed in subsequent processes, a certain degree of adhesion is required between the separation layer 910 and the redistribution layer 100 to prevent movement of the redistribution layer 100 during these processes. However, the adhesion between the separation layer 910 and the redistribution layer 100 is less than the adhesion between the separation layer 910 and the first substrate 900 to facilitate subsequent peeling processes. Therefore, the separation layer 910 can be a UV adhesive layer or a polymer layer such as epoxy resin, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), etc. The UV adhesive layer or the polymer layer is coated onto the surface of the first substrate 900 using a spin-coating process, and then cured using a UV curing or thermosetting process. The UV adhesive layer can be peeled off by softening with heat, and the polymer layer can be peeled off by wet etching, chemical mechanical polishing, etc. Preferably, in this embodiment, a UV adhesive layer is used as the separation layer 910.

[0080] As an example, after forming the separation layer 910 on the first substrate 900, the method further includes the following steps to form the redistribution layer 100:

[0081] 1. A dielectric layer 110 is formed on the separation layer 910. The forming process includes, but is not limited to, physical vapor deposition or chemical vapor deposition. The material of the dielectric layer 110 includes one or a combination of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass.

[0082] 2. A metal layer is formed on the dielectric layer 110, and the forming process includes, but is not limited to, physical vapor deposition, sputtering, and electroplating. The metal layer is etched to form a metal wiring layer 120. The material of the metal wiring layer 120 includes one or a combination of aluminum, gold, silver, copper, nickel, and titanium.

[0083] 3. A dielectric layer 110 is formed on the metal wiring layer 120, so the redistribution layer 100 has a first surface and a second surface disposed opposite to each other.

[0084] Furthermore, the material, number of layers, and distribution morphology of the dielectric layer 110 and the metal wiring layer 120 can be set according to the specific chip requirements, and no special restrictions are imposed here. In addition, unless otherwise specified in this application, electrical connection with the redistribution layer 100 specifically refers to electrical connection with the metal wiring layer 120.

[0085] like Figure 1 S2 step and Figure 3 As shown, the conductive pillar 200 is formed on the first surface of the redistribution layer 100, the conductive pillar 200 is electrically connected to the redistribution layer 100, and the intermediate chip 300 is bonded to the first surface of the redistribution layer 100 with its front side facing up.

[0086] like Figure 3 As shown, in this embodiment, the first surface of the redistribution layer 100 is etched to expose a portion of the metal wiring layer 120, and the conductive pillars 200 are formed on the portion of the metal wiring layer 120. The conductive pillars 200 are electrically connected to the redistribution layer 100 through contact with the metal wiring layer 120. The conductive pillars 200 include one or a combination of copper pillars, aluminum pillars, gold pillars, and silver pillars, and the forming method includes one or a combination of wire bonding, electroplating, and electroless plating.

[0087] The intermediate chip 300 includes one or a combination of bare chips and packaged chips, depending on actual needs, and is not specifically limited here. In this embodiment, the intermediate chip 300 is shown as two chips, but it is not limited to this. The number of intermediate chips can be greater than two, such as three, four, five, six, etc., depending on actual packaging requirements. The intermediate chip 300 connects to external circuits via contact pads 301. The contact pads 301 are located within the intermediate chip 300. One end of the contact pad 301 is electrically connected to the internal circuitry of the intermediate chip 300, and the other end is connected to the subsequent electrical connection structure and solder ball bump array 500, thereby connecting external electrical signals to the electrical signals of the intermediate chip 300.

[0088] The side of the intermediate chip 300 closest to the contact pad 301 is the front side, and the side furthest from the contact pad 301 is the back side. The intermediate chips 300 are bonded to the first surface of the redistribution layer 100 with their front side facing up via an adhesive layer 310. The intermediate chips can be arranged side-by-side or staggered, depending on actual requirements. The adhesive layer 310 fixes the intermediate chips 300 to the redistribution layer 100 to ensure that the intermediate chips 300 will not move during subsequent processes. Therefore, there are no special restrictions on the material of the adhesive layer 310, as long as it has the aforementioned adhesive properties.

[0089] like Figure 1 Step S3 in the middle and Figure 4 As shown, a first molding compound layer 400 is formed on the first surface of the redistribution layer 100. The first molding compound layer 400 covers the conductive pillar 200, the intermediate chip 300 and the redistribution layer 100, and exposes the top surfaces of the conductive pillar 200 and the intermediate chip 300.

[0090] A first molding compound layer 400 is formed on the first surface of the redistribution layer 100. The first molding compound layer 400 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer. The method for forming the first molding compound layer 400 includes one of compression molding, transfer molding, liquid sealing molding, molding underfill, capillary underfill, vacuum lamination, and spin coating. Preferably, in this embodiment, a molding underfill process is used. This process allows the molding compound to smoothly and quickly fill the gap between the intermediate chip 300, the conductive pillar 200, and the redistribution layer 100, effectively preventing interface delamination.

[0091] As an example, after forming the first molding compound layer 400 on the first surface of the redistribution layer 100, the method further includes removing a portion of the first molding compound layer 400 above the conductive pillar 200 and the intermediate chip 300 to expose the top surfaces of the conductive pillar 200 and the intermediate chip 300.

[0092] Specifically, after the first molding compound layer 400 fills the gap between the intermediate chip 300, the conductive pillar 200 and the redistribution layer 100, the height of the first molding compound layer 400 is higher than the height of the intermediate chip 300 and the conductive pillar 200. In order to expose the intermediate chip 300 and the conductive pillar 200, a portion of the first molding compound layer 400 can be removed by grinding or other methods, so that the top of the first molding compound layer 400 is flush with the top of the intermediate chip 300 and the conductive pillar 200, thereby exposing the top surface of the conductive pillar 200 and the top surface of the intermediate chip 300.

[0093] like Figure 1 S4 step and Figure 5 As shown, the electrical connection structure is fabricated on the first molding compound layer 400 using a damascus inlay process. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar 200 and the intermediate chip 300. A solder ball bump array is formed on the electrical connection structure. The solder ball bump array is electrically connected to the metal pillar.

[0094] As an example, the electrical connection structure is fabricated on the first molding compound layer 400 using a damascus inlay process, which includes the following steps:

[0095] 1) A first sub-dielectric layer is formed on the first molding compound layer 400, and the first sub-dielectric layer is etched to form a first sub-wiring dielectric layer 510; wherein, the first sub-dielectric layer is preferably, but not limited to, a low-k dielectric layer, and the first sub-dielectric layer is etched to form the first sub-wiring dielectric layer 510, wherein the opening of the first sub-wiring dielectric layer 510 is correspondingly disposed with respect to the conductive pillar 200 and the metal pillar 302 of the intermediate chip 300, that is, the first sub-wiring dielectric layer 510 exposes the top surface of the conductive pillar 200 and the top surface of the metal pillar 302 of the intermediate chip 300.

[0096] 2) A first sub-metal line layer is formed on the first sub-wiring dielectric layer 510. The first sub-metal line layer is in electrical contact with the conductive pillar 200 and the intermediate chip 300. The first sub-metal line layer is formed on the first sub-wiring dielectric layer 510, and at the opening of the first sub-wiring dielectric layer 510, the first sub-metal line layer is located on the top surface of the metal pillar 302 of the conductive pillar 200 and the intermediate chip 300. Therefore, the first sub-metal line layer is electrically connected to the conductive pillar 200 and the intermediate chip 300. The first sub-metal line layer includes one or a combination of copper, aluminum, gold, silver, nickel, titanium, tin, and tantalum. The formation method includes, but is not limited to, sputtering, electroplating, physical vapor deposition, chemical vapor deposition, and immersion. Furthermore, to prevent the first sub-metal line layer from diffusing into the first sub-wiring dielectric layer, a diffusion barrier layer can be deposited before depositing the first sub-metal line layer. For example, TiN is generally used as a diffusion barrier layer in aluminum processes, and TaN is generally used as a diffusion barrier layer in copper processes.

[0097] 3) Excess metal layers are removed using chemical mechanical polishing (CMP) to expose the first sub-wiring dielectric layer 510 and the first sub-metal interconnect layer 520 formed in the first sub-wiring dielectric layer 510. The excess metal layers are removed using CMP to form the first sub-metal interconnect layer 520. The first sub-metal interconnect layer 520 is electrically connected to the conductive pillar 200 and the intermediate chip 300. The linewidth of the metal interconnects in the first sub-metal interconnect layer 520 and / or the line spacing between adjacent metal interconnects can be less than 0.1 μm. The 1P1M structure formed by the first sub-wiring dielectric layer 510 and the first sub-metal interconnect layer 520 constitutes one layer of the electrical interconnect structure. The electrical interconnect structure treated by CMP can achieve both overall and local planarization.

[0098] 4) Repeat steps 1-3 twice to form a 3P3M structure, form a fourth sub-dielectric layer on the 3P3M, and etch the fourth sub-dielectric layer to form a fourth sub-wiring dielectric layer 550; wherein, in the 3P3M structure, the first sub-metal interconnect layer 520, the second sub-metal interconnect layer 530 and the third sub-metal interconnect layer 540 are vertically connected from bottom to top to form metal pillars located in the electrical connection structure, and the metal pillars are electrically connected to the conductive pillar 200 and the intermediate chip 300; form a fourth sub-dielectric layer on the 3P3M, and etch the fourth sub-dielectric layer to form a fourth sub-wiring dielectric layer 550, and the etched fourth sub-wiring dielectric layer 550 will expose the third sub-metal interconnect layer 540.

[0099] 5) A metallization layer 560 and a solder ball bump array 570 are formed on the fourth sub-wiring dielectric layer 550; wherein, before forming the metallization layer 560 and the solder ball bump array 570, a bottom metallization layer (not shown) is deposited on the fourth sub-wiring dielectric layer 550 as a diffusion barrier layer and / or a seed layer, the bottom metallization layer being located on the fourth sub-wiring dielectric layer 550 and the third sub-metal interconnect layer 540; a bump mask layer (not shown) is formed on the bottom metallization layer, the bump mask layer having patterned openings, the patterned openings being correspondingly disposed with respect to the third sub-metal interconnect layer 540; on the bumps The metallization layer 560 and the solder layer are deposited in the patterned openings of the mask layer, and the solder ball bump array 570 is formed by solder reflow process; the bump mask layer is removed by etching, and then the uncovered part of the bottom metallization layer is removed to expose the fourth sub-wiring dielectric layer 550. The 4P4M structure thus formed constitutes the complete electrical connection structure and solder ball bump array 500, and the solder ball bump array 570 is electrically connected to the metal pillars formed by the third sub-metal connection layer 540, the second sub-metal connection layer 530 and the first sub-metal connection layer 520 through the metallization layer 560 and the bottom metallization layer.

[0100] Specifically, as shown in the example above, the electrical connection structure and solder ball bump array layer 500 fabricated using the damascus damascene process is a 4P4M structure, but it is not limited to this. The material, number of layers, and distribution morphology of the electrical connection structure and solder ball bump array layer 500 can be set according to the actual chip requirements, for example, it can be an nPnM structure, where n is greater than or equal to 2. In addition, the damascus damascene fabrication method can achieve a linewidth and line spacing of less than 0.1μm for its metal interconnects, thereby enabling the packaging of more chips, providing more input / output interfaces, and reducing package size. Since each layer undergoes chemical mechanical polishing, it can simultaneously achieve overall and local planarization, effectively reducing resistance and signal delay, and improving the overall performance of the package structure. The damascus damascene process is applicable to various metals and can use metals with better electrical performance, such as copper, to solve various bottleneck problems encountered in back-end aluminum interconnect technology, while also providing the possibility of stacking three or even more layers of chips.

[0101] like Figure 1 S5 steps and Figure 6 As shown, a second substrate 800 is provided and bonded to the solder ball bump array 570. The first substrate 900 and the release layer 910 are removed to expose the second surface of the redistribution layer 100. The second substrate 800, like the first substrate 900, provides a support plane for the subsequent packaging structure to prevent problems such as cracking, breakage, and warping of the semiconductor chip during subsequent fabrication. Therefore, the bonding between the second substrate 800 and the solder ball bump array 570 is not described in detail. The removal of the first substrate 900 and the release layer 910 can be achieved by one or a combination of mechanical polishing, chemical polishing, etching, heating, and mechanical stripping. In this embodiment, heating is used to reduce the stickiness of the release layer 910 to remove the first substrate 900 and the release layer 910.

[0102] like Figure 1 S6 steps and Figure 7As shown, the second surface of the redistribution layer 100 is etched to expose the metal wiring layer 120 within the redistribution layer 100, electrically connecting the bottom chip 600 to the redistribution layer 100. The bottom chip 600 includes a controller, amplifier, etc., capable of processing and compiling electrical signals. Additionally, the bottom chip 600 includes passive components, including one or a combination of capacitors, inductors, and resistors. In this embodiment, the passive component 610 is a capacitor, which can store and release charge, discharging when the system loses power to protect the information stored within the package structure from damage. In this embodiment, the number of bottom chips 600 is two, but it is not limited to this. Depending on the actual chip requirements, the number of bottom chips 600 can also be one, two, three, or even more.

[0103] Furthermore, the second surface of the redistribution layer 100 is etched to expose the metal wiring layer 120. The bottom chip 600 forms solder microbumps 610 on its upper surface by reflow soldering. The bottom chip 600 is soldered and assembled with the metal wiring layer 120 by surface mount technology, thereby realizing the electrical connection between the bottom chip 600 and the redistribution layer 100.

[0104] After the bottom chip 600 is electrically connected to the redistribution layer 100, the process further includes filling the gap between the bottom chip 600 and the redistribution layer 100 with underfill adhesive 620. In this embodiment, a capillary underfill method is used, utilizing capillary action to allow the adhesive to flow rapidly across the bottom of the bottom chip 600, with a minimum capillary flow space of 10µm. This also meets the minimum electrical characteristic requirements between the pads and solder balls in the soldering process, as the adhesive will not flow through gaps smaller than 4µm, thus ensuring the electrical safety characteristics of the soldering process. Furthermore, the large-area bottom gap is filled using a heat-curing method, thereby achieving reinforcement and enhancing the drop resistance of the packaging structure.

[0105] like Figure 1 S7 steps and Figure 7 As shown, a second molding compound layer 700 is formed on the second surface of the redistribution layer 100, and the second molding compound layer 700 covers the redistribution layer 100 and the bottom chip 600. The second molding compound layer 700 includes one or a combination of a polyimide layer, a silicone layer, and an epoxy resin layer. The method for forming the second molding compound layer 700 includes one of compression molding, transfer molding, liquid sealing molding, molding underfill, capillary underfill, vacuum lamination, and spin coating. To simplify the process, in this embodiment, the second molding compound layer 700 also uses a capillary underfill method to ensure the electrical safety characteristics of the soldering process.

[0106] like Figure 1 As shown in step S8, the second substrate 800 is removed. The removal of the second substrate 800 can be done using a similar or identical method to the removal of the first substrate 900, which will not be described in detail here.

[0107] Example 2

[0108] This embodiment provides a 3D fan-out packaging structure. This packaging structure can be prepared using the method described in Embodiment 1, but is not limited to the method described in Embodiment 1, as long as the 3D fan-out packaging structure can be formed. The beneficial effects achievable by this 3D fan-out packaging structure can be found in Embodiment 1, and will not be repeated below.

[0109] like Figure 7 The 3D fan-out packaging structure includes:

[0110] A rewiring layer, comprising a first surface and a second surface disposed opposite to each other;

[0111] A conductive post, the conductive post being located on the first surface of the redistribution layer and electrically connected to the redistribution layer;

[0112] An intermediate chip, the intermediate chip being bonded to the first surface of the redistribution layer, and the front side of the intermediate chip being away from the redistribution layer;

[0113] A first molding compound layer covers the conductive pillars, the intermediate chip, and the redistribution layer, and exposes the top surfaces of the conductive pillars and the intermediate chip.

[0114] An electrical connection structure and a solder ball bump array are provided. The electrical connection structure is located on the surface of the first molding compound layer away from the redistribution layer. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar and the intermediate chip. The solder ball bump array is located on the electrical connection structure and is electrically connected to the metal pillar.

[0115] A bottom chip, the bottom chip being located on the second surface of the redistribution layer and electrically connected to the redistribution layer;

[0116] A second molding compound layer covers the redistribution layer and the bottom chip.

[0117] Preferably, the redistribution layer includes a dielectric layer and a metal wiring layer located inside the dielectric layer.

[0118] Preferably, the electrical connection structure and the solder ball bump array constitute a 4P4M structure, including four sub-dielectric layers, three sub-metal connection layers penetrating within the sub-dielectric layers, and a top-level sub-metal connection layer consisting of the solder ball bump array and a metallization layer located below the solder ball bump array, wherein the linewidth of the metal interconnects in the sub-metal connection layers of the 4P4M layer and / or the spacing between adjacent metal interconnects is less than 0.1 μm.

[0119] Preferably, the bottom chip further includes passive components, which include one or a combination of capacitors, inductors, and resistors.

[0120] Preferably, the upper surface of the bottom chip is provided with soldering microbumps, and the bottom chip is electrically connected to the redistribution layer through the soldering microbumps.

[0121] Preferably, an underfill adhesive is further used to fill the space between the redistribution layer and the bottom chip.

[0122] In summary, this invention provides a 3D fan-out package structure and its fabrication method. The 3D fan-out package structure includes a redistribution layer, conductive pillars, an intermediate chip, a first molding compound layer, an electrical connection structure and a solder ball and bump array, a bottom chip, and a second molding compound layer. The electrical connection structure includes stacked electrical connection layers, which solves the problem of aluminum being difficult to pad in vias with a 10:1 aspect ratio by using a layered approach. The vertical electrical connections of each sub-metal connection layer from top to bottom can reduce resistance and signal delay. The bottom chip also includes passive components. The intermediate chip can be directly controlled through the electrical connection structure and solder ball and bump array and the redistribution layer, or the intermediate chip can be controlled after signal processing by the bottom chip. In the event of a sudden power loss, the passive components in the bottom chip can discharge, thereby protecting the data from damage.

[0123] Meanwhile, the electrical connection structure manufactured using the damascus damascene process can achieve both global and local planarization of the chip, further reducing resistance and signal delay, and improving the overall performance of the chip. The damascus damascene process is applicable to various metals, and can use metals with superior electrical performance, such as copper, to solve various bottleneck problems encountered in back-end aluminum interconnect technology. The damascus damascene process can meet the requirement that the metal interconnect linewidth and line spacing be less than 0.1μm, thereby enabling the 3D fan-out packaging structure to package more chips, provide more input / output interfaces, reduce package size, and meet the current demand for high-performance chips.

[0124] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A 3D fan-out packaging structure, characterized in that, The 3D fan-out packaging structure includes at least: A rewiring layer, comprising a first surface and a second surface disposed opposite to each other; A conductive post, the conductive post being located on the first surface of the redistribution layer and electrically connected to the redistribution layer; An intermediate chip, the intermediate chip being bonded to the first surface of the redistribution layer, and the front side of the intermediate chip being away from the redistribution layer; A first molding compound layer covers the conductive pillars, the intermediate chip, and the redistribution layer, and exposes the top surfaces of the conductive pillars and the intermediate chip. An electrical connection structure and a solder ball bump array are provided. The electrical connection structure is located on the surface of the first molding compound layer away from the redistribution layer. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar and the intermediate chip. The solder ball bump array is located on the electrical connection structure and is electrically connected to the metal pillar. A bottom chip, the bottom chip being located on the second surface of the redistribution layer and electrically connected to the redistribution layer; A second molding compound layer covers the redistribution layer and the bottom chip.

2. The 3D fan-out packaging structure according to claim 1, characterized in that: The redistribution layer includes a dielectric layer and a metal wiring layer located inside the dielectric layer.

3. The 3D fan-out packaging structure according to claim 1, characterized in that: The electrical connection structure and the solder ball bump array constitute a 4P4M structure. The 4P4M structure includes four sub-dielectric layers, three sub-metal interconnect layers penetrating within the sub-dielectric layers, the solder ball bump array, and a top-level sub-metal interconnect layer composed of a metallization layer located below the solder ball bump array. In the 4P4M structure, the linewidth of the metal interconnects in the sub-metal interconnect layers and / or the spacing between adjacent metal interconnects is less than 0.1 μm.

4. The 3D fan-out packaging structure according to claim 1, characterized in that: The bottom chip also includes passive components, including one or more of capacitors, inductors, and resistors.

5. The 3D fan-out packaging structure according to claim 1, characterized in that: The upper surface of the bottom chip is provided with solder microbumps, and the bottom chip is electrically connected to the redistribution layer through the solder microbumps.

6. The 3D fan-out packaging structure according to claim 1, characterized in that: The redistribution layer and the bottom chip are further filled with underfill adhesive.

7. A method for fabricating a 3D fan-out packaging structure, characterized in that, Includes the following steps: S1. A first substrate is provided and a separation layer is formed on the first substrate, and a redistribution layer is formed on the separation layer, the redistribution layer including a first surface and a second surface disposed opposite to each other; S2. A conductive pillar is formed on the first surface of the redistribution layer, the conductive pillar is electrically connected to the redistribution layer, and the intermediate chip is bonded to the first surface of the redistribution layer with the front side facing up. S3. A first molding compound layer is formed on the first surface of the redistribution layer, the first molding compound layer covering the conductive pillar, the intermediate chip and the redistribution layer, and exposing the top surfaces of the conductive pillar and the intermediate chip; S4. An electrical connection structure is fabricated on the first molding compound layer using a damascus inlay process. The electrical connection structure includes stacked electrical connection layers. Each electrical connection layer includes a sub-dielectric layer and a sub-metal connection layer penetrating the sub-dielectric layer. Each sub-metal connection layer is vertically electrically connected from top to bottom to form a metal pillar located in the electrical connection structure. The metal pillar is electrically connected to the conductive pillar and the intermediate chip. A solder ball bump array is formed on the electrical connection structure. The solder ball bump array is electrically connected to the metal pillar. S5. Provide a second substrate and bond the second substrate to the solder ball bump array, remove the first substrate and the separation layer to expose the second surface of the redistribution layer; S6. Etch the second surface of the redistribution layer to expose the metal wiring layer within the redistribution layer, and electrically connect the bottom chip to the redistribution layer. S7. A second molding compound layer is formed on the second surface of the redistribution layer, the second molding compound layer covering the redistribution layer and the bottom chip; S8. Remove the second substrate.

8. The method for fabricating the 3D fan-out packaging structure according to claim 7, characterized in that, The step of forming the redistribution layer on the upper surface of the first substrate in S1 includes: first forming a dielectric layer on the upper surface of the first substrate, then forming a metal layer on the surface of the dielectric layer, etching the metal layer to form a metal wiring layer, and finally forming a dielectric layer again on the metal wiring layer.

9. The method for fabricating the 3D fan-out packaging structure according to claim 7, characterized in that: In step S3, after forming a first molding compound layer on the first surface of the redistribution layer, the step further includes removing the first molding compound layer above the conductive pillars and the intermediate chip to expose the top surface of the conductive pillars and the intermediate chip.

10. The method for fabricating the 3D fan-out packaging structure according to claim 7, characterized in that, S4 involves fabricating an electrical connection structure on the first molding compound layer using a damascus inlay process, and forming a solder ball bump array on the electrical connection structure, which includes the following steps: A first sub-dielectric layer is formed on the first molding compound layer, and the first sub-dielectric layer is etched to form a first sub-wiring dielectric layer; A first metal line layer is formed on the first sub-wiring dielectric layer, and the first metal line layer is in electrical contact with the conductive pillar and the intermediate chip; Excess metal layers are removed by chemical mechanical polishing to expose the first sub-wiring dielectric layer and the first sub-metal interconnect layer formed in the first sub-wiring dielectric layer. Repeat steps 1-3 twice to form a 3P3M structure, form a fourth sub-dielectric layer on the 3P3M structure, and etch the fourth sub-dielectric layer to form a fourth sub-wiring dielectric layer; A metallization layer and a solder ball bump array are formed on the fourth sub-wiring dielectric layer.

Images