Heat dissipation substrate, power module and method for manufacturing heat dissipation substrate

Abstract

The application discloses a heat dissipation substrate, a power module and a preparation method of the heat dissipation substrate. The heat dissipation substrate comprises a ceramic substrate, a first metal layer connected to a first side surface of the ceramic substrate and having a plurality of first conductive lines, a second metal layer connected to the first side surface of the ceramic substrate and having a plurality of second conductive lines, and a third metal layer connected to a second side surface of the ceramic substrate opposite to the first side surface. The minimum spacing between adjacent first conductive lines is greater than the minimum spacing between adjacent second conductive lines, and / or the minimum line width of the first conductive lines is greater than the minimum line width of the second conductive lines. In the application, the first metal layer and the second metal layer are both connected to the same side surface of the ceramic substrate, so that a series of problems caused by deformation of the bonding wire due to impact or vibration can be improved. In addition, the heat dissipation substrate of the application is also helpful to reduce the volume of the power module.

Description

Technical Field

[0001] This invention relates to the field of power module fabrication technology, and in particular to a heat dissipation substrate, a power module, and a method for fabricating the heat dissipation substrate. Background Technology

[0002] Intelligent power modules contain various chips, such as control chips and power chips. In related technologies, power chips are mounted on a heat sink substrate, while control chips are mounted on a frame. The power chips and control chips are connected by leads. Current intelligent power modules have the following problems: Due to the significant height difference between the heat sink substrate and the frame, the leads connecting the power chips and control chips are relatively long. These leads are prone to direct contact or breakage due to vibrations during transportation or impacts from the packaging material during packaging, leading to short circuits or open circuits. Furthermore, the frame manufacturing process limits the linewidth of the circuits and the distance between adjacent lines, which must be maintained at a certain size, restricting the miniaturization of the power module. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a heat dissipation substrate that can improve the problem of lead wire deformation and help to achieve miniaturization of power modules.

[0004] The present invention also proposes a power module using the aforementioned heat dissipation substrate, and a method for preparing the aforementioned heat dissipation substrate.

[0005] A heat dissipation substrate according to a first embodiment of the present invention, used for connecting chips, includes:

[0006] Ceramic substrate;

[0007] A first metal layer is connected to a first side of the ceramic substrate and has multiple first conductive lines;

[0008] The second metal layer is connected to the first side of the ceramic substrate and has a plurality of second conductive lines;

[0009] A third metal layer is connected to the second side of the ceramic substrate, which is disposed opposite to the first side.

[0010] Wherein, the minimum spacing between adjacent first conductive lines is greater than the minimum spacing between adjacent second conductive lines, and / or, the minimum line width of the first conductive line is greater than the minimum line width of the second conductive line.

[0011] The heat dissipation substrate according to the first embodiment of the present invention has at least the following beneficial effects:

[0012] Both the first and second metal layers are connected to the same side surface of the ceramic substrate. The height difference between the first and second metal layers is small. When the first metal layer is connected to the power chip and the second metal layer is connected to the control chip, the height difference between the power chip and the control chip is also small, which can shorten the length of the bonding wire. In addition, since the first and second metal layers are connected to the ceramic substrate at the same time, there will be no relative vibration between the power chip and the control chip. All of the above can improve a series of problems caused by the deformation of the bonding wire due to impact or vibration.

[0013] On the other hand, compared with the conductive lines of traditional power modules, the second conductive lines in this embodiment are disposed on the heat dissipation substrate and are not limited by the frame manufacturing process. Therefore, while meeting the current requirements of the control chip, the minimum spacing between adjacent second conductive lines can be smaller than the minimum spacing between adjacent first conductive lines, and / or the minimum linewidth of the second conductive lines is smaller than the minimum linewidth of the first conductive lines. In this way, the size of the power module can be reduced.

[0014] In other embodiments of the present invention, the minimum spacing between adjacent first conductive lines is 350 μm to 800 μm, and the minimum spacing between adjacent second conductive lines is 50 μm to 200 μm;

[0015] And / or, the minimum linewidth of the first conductive line is 350 μm to 800 μm, and the minimum linewidth of the second conductive line is 65 μm to 200 μm.

[0016] In other embodiments of the present invention, the thickness of the first metal layer is greater than the thickness of the second metal layer.

[0017] In other embodiments of the present invention, the thickness of the first metal layer is 200 μm to 500 μm, and the thickness of the second metal layer is 50 μm to 75 μm.

[0018] In other embodiments of the present invention, the current carrying capacity of the first conductive line is less than or equal to 200A, the current carrying capacity of the second conductive line is less than or equal to 50A, and the current carrying capacity of the first conductive line is greater than the current carrying capacity of the second conductive line.

[0019] A heat dissipation substrate according to a second embodiment of the present invention, used for connecting chips, includes:

[0020] Ceramic substrate;

[0021] A first metal layer is connected to a first side of the ceramic substrate and has multiple first conductive lines;

[0022] The second metal layer is connected to the first side of the ceramic substrate and has a plurality of second conductive lines;

[0023] A third metal layer is connected to the second side of the ceramic substrate, which is disposed opposite to the first side.

[0024] The thickness of the first metal layer is greater than the thickness of the second metal layer.

[0025] A power module according to a third embodiment of the present invention includes:

[0026] The aforementioned heat dissipation substrate;

[0027] A power chip is connected to the first metal layer;

[0028] The first frame is connected to the first metal layer;

[0029] The second frame is connected to the second metal layer.

[0030] In other embodiments of the present invention, the power module further includes a control chip and a first lead, the control chip being connected to the second metal layer, and the first lead being connected to the control chip and the power chip.

[0031] In other embodiments of the present invention, the power module further includes a control chip, a second lead and a third lead, at least one of the plurality of second conductive lines is defined as an mounting line and at least another as a transition line, the control chip is connected to the second metal layer, the second lead is connected to the control chip and the transition line, and the third lead is connected to the transition line and the power chip.

[0032] The method for preparing a heat dissipation substrate according to a fourth embodiment of the present invention includes the following steps:

[0033] Prepare a ceramic substrate, wherein a first side of the ceramic substrate has a first region and a second region;

[0034] A first metal layer is prepared in the first region of the ceramic substrate by a direct copper plating process, the first metal layer having a plurality of first conductive lines;

[0035] A second metal layer is prepared in the second region of the ceramic substrate by a direct copper plating process, the second metal layer having a plurality of second conductive lines;

[0036] Wherein, the minimum spacing between adjacent first conductive lines is greater than the minimum spacing between adjacent second conductive lines, and / or, the minimum line width of the first conductive line is greater than the minimum line width of the second conductive line.

[0037] In other embodiments of the present invention, the method of preparing the first metal layer in the first region of the ceramic substrate by a direct copper plating process and preparing the second metal layer in the second region of the ceramic substrate by a direct copper plating process includes:

[0038] Prepare a first metal substrate, attach the first metal substrate to the first side of the ceramic substrate, and cover at least a portion of the first region and at least a portion of the second region;

[0039] The first metal substrate is etched to form the first metal layer and expose the second region;

[0040] A metal film is formed in the exposed second region;

[0041] The metal film is electroplated to form a second metal substrate;

[0042] The second metal substrate is etched to form the second metal layer.

[0043] In other embodiments of the present invention, the method of preparing the first metal layer in the first region of the ceramic substrate by a direct copper plating process and preparing the second metal layer in the second region of the ceramic substrate by a direct copper plating process includes:

[0044] Prepare a first metal substrate, connect the first metal substrate to the first side of the ceramic substrate, and at least cover the first area, while keeping the second area of ​​the metal substrate exposed.

[0045] The first metal substrate is etched to form the first metal layer;

[0046] A metal film is formed in the exposed second region;

[0047] The metal film is electroplated to form a second metal substrate;

[0048] The second metal substrate is etched to form the second metal layer.

[0049] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0050] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0051] Figure 1 A 3D schematic diagram of a traditional power module before packaging;

[0052] Figure 2for Figure 1 Enlarged view of region A in the middle;

[0053] Figure 3 This is a front view of the heat dissipation substrate in an embodiment of the present invention;

[0054] Figure 4 for Figure 3 Side view of the heat dissipation substrate;

[0055] Figure 5 This is a front view of the power module before packaging in an embodiment of the present invention;

[0056] Figure 6 For is Figure 5 Enlarged view of region B in the middle;

[0057] Figure 7 for Figure 5 Side view of the medium power module;

[0058] Figure 8 This is a schematic diagram of the process for preparing the first metal layer by direct copper plating in an embodiment of the present invention;

[0059] Figure 9 This is a schematic diagram of the process for preparing the second metal layer by direct copper plating in an embodiment of the present invention;

[0060] Figure 10 This is a schematic diagram of the process for preparing the first metal layer by direct copper plating in another embodiment of the present invention;

[0061] Figure 11 This is a schematic diagram showing the distribution of bonding lines between the display control chip and the power chip in a traditional power module;

[0062] Figure 12 for Figure 5 A schematic diagram showing the wiring distribution between the control chip and the power chip in the medium power module display.

[0063] Figure label:

[0064] First chip 1, second chip 2, lead frame 3, conductive line 31, copper-clad ceramic substrate 4, bonding wire 5;

[0065] Heat dissipation substrate 100, first metal layer 110, first conductive line 111, second metal layer 120, second conductive line 121, mounting line 122, transition line 123, frame line 124, third metal layer 130, ceramic substrate 140, first region 141, second region 142;

[0066] Power chip 200;

[0067] First frame 300;

[0068] Second frame 400;

[0069] Control chip 500;

[0070] First lead 610, second lead 620, third lead 630;

[0071] First metal substrate 700;

[0072] Metal film 800;

[0073] Second metal substrate 900;

[0074] Dry film 1000. Detailed Implementation

[0075] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0076] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0077] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0078] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0079] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0080] Reference Figure 1 , Figure 2 This shows a three-dimensional schematic diagram and a partially enlarged schematic diagram of a traditional power module before packaging, such as... Figure 1 As shown, a traditional power module includes a first chip 1, a second chip 2, a lead frame 3, a copper-clad ceramic substrate 4, and bonding wires 5. The first chip 1 is connected to the lead frame 3 via the copper-clad ceramic substrate 4, and the second chip 2 is directly connected to the lead frame 3. The first chip 1 can be a power chip, and the second chip 2 can be a control chip. The bonding wires 5 are connected to the pads of the first chip 1 and the second chip 2, respectively. Because the area of ​​the second chip 2 is smaller, and multiple bonding wires 5 need to be connected to a single second chip 2, the area of ​​the pad allocated to each conductive component is correspondingly smaller. Therefore, the bonding wires 5 are usually made of thin gold or copper wire, resulting in lower strength.

[0081] like Figure 2As shown, the copper-clad ceramic substrate 4 is lower than the lead frame, and there is a relatively large height difference between the two, resulting in a longer bonding wire 5. The longer lead wire causes some problems in the actual production process: The lead frame 3 with the first chip 1 and the second chip 2 shown in the figure needs to go through a packaging step to form a complete power module. During the packaging process, the molten packaging material (such as epoxy resin) will impact the bonding wire 5. In addition, during the transfer process before packaging, the lead frame 3 with the first chip 1 and the second chip 2 will also vibrate. Especially for the first chip 1, since the copper-clad ceramic substrate 4 is connected to the lead frame 3 on one side to form a cantilever structure, the vibration amplitude of the first chip 1 will be much greater. Due to the vibration amplitude of the lead frame 3, and the relatively long length and small diameter of the bonding wire 5, its overall strength is low. Therefore, it is easily deformed by the aforementioned impacts or vibrations, and it is difficult for it to automatically return to its original shape after deformation. Deformation of the bonding wire 5 will cause the following problems: 1. In order to avoid short circuits caused by the bonding wire 5 contacting the chip or lead frame 3, the bonding wire 5 needs to have a certain curvature to ensure that there is a certain safe distance between the bonding wire 5 and the chip and lead frame 3 respectively. If the bonding wire 5 is deformed, there is a risk that the bonding wire 5 will contact the chip or lead frame 3 and short circuit. In addition, there is also a risk that the bonding wires 5 will contact each other and short circuit; 2. When the deformation of the bonding wire 5 exceeds the limit, it will also lead to the breakage of the bonding wire 5.

[0082] On the other hand, the second chip 2 has a smaller current, and in practice, only a thinner conductive line is needed to meet the requirements. However, referring to... Figure 1 The second chip 2 is directly connected to the lead frame 3. That is, a part of the structure of the lead frame 3 serves as a conductive line 31 that is electrically connected to the second chip 2. The width of the conductive line 31 exceeds the conductivity requirements of the second chip 2. However, due to the manufacturing process of the lead frame 3, the width of the conductive line 31 cannot be further reduced, and the distance between adjacent conductive lines 31 cannot be further reduced, which restricts the miniaturization of the power module.

[0083] To address the aforementioned problems, this invention proposes a heat dissipation substrate 100, which facilitates the miniaturization of power modules. (Refer to...) Figure 3 , Figure 4 The heat dissipation substrate 100 in this embodiment of the invention includes a first metal layer 110, a second metal layer 120, a third metal layer 130, and a ceramic substrate 140. The ceramic substrate 140 includes a first side surface and a second side surface disposed opposite to each other. Figure 4 For example, the first side is the upper side of the ceramic substrate 140, the second side is the lower side of the ceramic substrate 140, the first metal layer 110 and the second metal layer 120 are both connected to the first side of the ceramic substrate 140, and the third metal layer 130 is connected to the second side of the ceramic substrate 140. After encapsulation, the third metal layer 130 is away from the side of the ceramic substrate 140 (e.g., Figure 4 The lower side of the chip is exposed from the package to dissipate heat from the internal chip.

[0084] Reference Figure 3 For ease of observation, the first metal layer 110 and the second metal layer 120 are respectively marked with dashed frames. It should be noted that the dashed frames are used to roughly indicate the extent of the first metal layer 110 and the second metal layer 120, and do not represent restrictions on the shape and size of the first metal layer 110 and the second metal layer 120. Figure 3 As shown, the first metal layer 110 and the second metal layer 120 are both roughly rectangular and arranged side by side.

[0085] The first metal layer 110 includes a plurality of spaced-apart first conductive lines 111, and the second metal layer 120 includes a plurality of spaced-apart second conductive lines 121. It should be noted that the description of "conductive lines" in this invention primarily reflects their conductive function and does not imply a limitation on their shape to be linear or strip-shaped. Figure 3 Taking the example shown, the first conductive line 111 is a block-shaped conductive line. In this embodiment, the first metal layer 110 can be prepared using a direct copper plating process, and the second metal layer 120 can be prepared using a direct copper plating process. Since the direct copper plating process is easier to control in terms of precision than the direct copper plating process, the second conductive lines 121 can be distributed more densely. That is, the distance between adjacent first conductive lines 111 is generally greater than the distance between adjacent second conductive lines 121. Specifically, at least the minimum spacing between adjacent first conductive lines 111 is greater than the minimum spacing between adjacent second conductive lines 121. It should be noted that the spacing between adjacent conductive lines can also be understood as the width of the gap between adjacent conductive lines. For ease of description, the following description uses the width of the gap. The widths of different gaps can be the same or different, and the width of the same gap can be constant or variable. Taking the first conductive line 111 as an example, the gap between adjacent first conductive lines 111 is named the first gap. The "minimum spacing between adjacent first conductive lines 111" referred to in this invention refers to the minimum width of each first gap. The minimum spacing between adjacent second conductive lines 121 is understood in the same way.

[0086] In other embodiments, since the direct copper plating process is easier to control in terms of precision compared to the direct copper cladding process, the second conductive line 121 can be thinner. That is, the linewidth of the first conductive line 111 is generally greater than the linewidth of the second conductive line 121. Specifically, at least the minimum linewidth of the first conductive line 111 is greater than the minimum linewidth of the second conductive line 121. Similarly, the linewidths of different first conductive lines 111 can be the same or different, and the linewidth of the same first conductive line 111 can be constant or variable. The "minimum linewidth of the first conductive line 111" referred to in this invention refers to the minimum linewidth of each first conductive line 111. The "minimum linewidth of the second conductive line 121" is understood in the same way.

[0087] In this embodiment, the first metal layer 110 and the second metal layer 120 are both connected to the same side surface of the ceramic substrate 140, such as... Figure 4 As shown, the height difference between the first metal layer 110 and the second metal layer 120 is small. Thus, when the first metal layer 110 is connected to the power chip and the second metal layer 120 is connected to the control chip, the height difference between the power chip and the control chip is also small, thereby shortening the length of the bonding wire. In addition, the first metal layer 110 and the second metal layer 120 are simultaneously connected to the ceramic substrate 140, so there is no relative vibration between the power chip and the control chip. All of the above can improve a series of problems caused by the deformation of the bonding wire due to impact or vibration.

[0088] Specifically, the effects of this invention will be illustrated with specific numerical values ​​below. Assuming the power chip and control chip have the same thickness, Figure 1 The height difference between the upper surface of the medium-power chip and the upper surface of the control chip is 1.04 mm. Figure 7 The height difference between the upper side of the medium-power chip and the upper side of the control chip is 0.088mm, which shows that the height difference between the chips can be significantly reduced in this embodiment.

[0089] In addition, refer to Figure 11 , Figure 12 The two figures are schematic diagrams illustrating the connection between the power chip and the control chip via leads in a traditional power module and in this embodiment, respectively. Figure 11 The diagram shows six first chips 1, two second chips 2, and nine bonding lines 5 (here, bonding lines 5 refer to the bonding lines connecting the first chips 1 and the second chips 2). Figure 12 The diagram shows six power chips 200, two control chips 500, and nine sets of connecting leads (here, connecting leads refer to the connecting leads that connect the power chips 200 and the control chips 500). Figure 11 The bonding wire 5 in the middle directly connects the first chip 1 and the second chip 2. Figure 12The set of connecting leads can include either the first lead 610 that directly connects the power chip 200 and the control chip 500, or a combination of the second lead 620 and the third lead 630. The second lead 620 connects the control chip 500 and the transition line 123, and the third lead 630 connects the transition line 123 and the power chip 200. For ease of description, the bonding lines 5 are named bonding lines 1 to 9 from left to right, and the connecting leads are named connecting leads 1 to 9. Connecting leads 1, 3, and 6 to 9 are all combinations of the second lead 620 and the third lead 630. Connecting leads 2, 4, and 5 all include the first lead 610.

[0090] Establish a projection plane parallel to the explanatory plane. Name the projection length of the bonding wire 5 on the projection plane as the first line length L1, and name the projection length of the connecting lead on the projection plane as the first line length L2. The values ​​of the first line length L1 and the first line length L2 are shown in the table below. It should be noted that when the connecting lead includes a combination of the second lead 620 and the third lead 630, the corresponding line length is the sum of the projection lengths of the second lead 620 and the third lead 630 on the projection plane.

[0091]

[0092] As shown in the table above, compared with traditional power modules, the projected length of each connecting lead in this embodiment is shorter, so the actual length of each connecting lead is also less than the actual length of the corresponding bonding wire.

[0093] On the other hand, compared with the conductive line 31 of a traditional power module, the second conductive line 121 of this embodiment is disposed on the heat dissipation substrate 100 and is not limited by the frame manufacturing process. Therefore, while meeting the current requirements of the control chip, the minimum spacing between adjacent second conductive lines 121 can be smaller than the minimum spacing between adjacent first conductive lines 111, and / or the minimum linewidth of the second conductive line 121 is smaller than the minimum linewidth of the first conductive line 111. In this way, the volume of the power module can be reduced. Figure 3 As shown in the example, since the second conductive line 121 is thinner and more compactly distributed, the size of the heat dissipation substrate 100 can be reduced at least along its width, thereby contributing to the miniaturization of the power module. It should be noted that even if the power module does not have a control chip, using the heat dissipation substrate 100 of this embodiment can still achieve the effect of reducing its size.

[0094] Based on the aforementioned first embodiment, in some embodiments the minimum spacing between adjacent first conductive lines 111 is 350μm to 800μm, and the minimum spacing between adjacent second conductive lines 121 is 50μm to 200μm. It can be seen that the minimum spacing between adjacent second conductive lines 121 is significantly smaller than the minimum spacing between adjacent first conductive lines 111, and the second conductive lines 121 are generally more compactly distributed.

[0095] Based on the aforementioned first embodiment, in some embodiments the minimum line width of the first conductive line 111 is 350μm to 800μm, and the minimum line width of the second conductive line 121 is 65μm to 200μm. It can be seen that the minimum line width of the second conductive line 121 is significantly smaller than the minimum line width of the first conductive line 111, and the second conductive line 121 is thinner overall.

[0096] Based on the aforementioned first embodiment, referring to Figure 4 Since the first metal layer 110 is prepared using a direct copper cladding process and the second metal layer 120 is prepared using a direct copper plating process, in some embodiments the thickness of the first metal layer 110 is greater than the thickness of the second metal layer 120. It should be noted that although there is a height difference between the first metal layer 110 and the second metal layer 120, the height difference is significantly smaller than... Figure 2 The height difference between the copper-clad ceramic substrate 4 and the lead frame 3 can shorten the bonding wire.

[0097] When the thickness of the first metal layer 110 is greater than the thickness of the second metal layer 120, in some specific embodiments the thickness of the first metal layer 110 is 200 μm to 500 μm and the thickness of the second metal layer 120 is 50 μm to 75 μm.

[0098] Based on the aforementioned first embodiment, since the first conductive line 111 is used to connect the power chip and carries a larger current, while the second conductive line 121 is used to connect the control chip and carries a smaller current, in some embodiments the current carrying capacity of the first conductive line 111 is greater than that of the second conductive line 121. Specifically, the current carrying capacity of the first conductive line 111 is less than or equal to 200A, and the current carrying capacity of the second conductive line 121 is less than or equal to 50A.

[0099] A second embodiment of the present invention discloses a heat dissipation substrate 100, including a first metal layer 110, a second metal layer 120, a third metal layer 130, and a ceramic substrate 140. The ceramic substrate 140 includes a first side surface and a second side surface disposed opposite to each other. Figure 4For example, the first side is the upper side of the ceramic substrate 140, the second side is the lower side of the ceramic substrate 140, the first metal layer 110 and the second metal layer 120 are both connected to the first side of the ceramic substrate 140, and the third metal layer 130 is connected to the second side of the ceramic substrate 140.

[0100] In this embodiment, the first metal layer 110 is prepared using a direct copper plating process, and the second metal layer 120 is prepared using a direct copper plating process. Therefore, the thickness of the first metal layer 110 is greater than the thickness of the second metal layer 120. It should be noted that although there is a height difference between the first metal layer 110 and the second metal layer 120, since both the first metal layer 110 and the second metal layer 120 are connected to the same side of the ceramic substrate 140, the height difference between them is significantly smaller than that between the first metal layer 110 and the second metal layer 120. Figure 2 The height difference between the copper-clad ceramic substrate 4 and the lead frame 3 is small when the first metal layer 110 connects to the power chip and the second metal layer 120 connects to the control chip. This reduces the length of the bonding wire. In addition, there is no relative vibration between the power chip and the control chip. All of these measures can improve a series of problems caused by the deformation of the bonding wire due to impact or vibration.

[0101] Based on the second embodiment, in some embodiments the thickness of the first metal layer 110 is 200 μm to 500 μm, and the thickness of the second metal layer 120 is 50 μm to 75 μm.

[0102] The third embodiment of the present invention proposes a power module, referring to... Figures 5 to 7 It includes a power chip 200, a first frame 300, a second frame 400, and a heat dissipation substrate 100 as described in the preceding embodiments. The power chip 200 and at least a portion of the first frame 300 are connected to a first metal layer 110, specifically by soldering or sintering to the upper surface of the first metal layer 110 with solder paste. One end of the first frame 300 extends from the package after encapsulation to serve as a pin of the power module. Figure 5 As shown in the example, the first metal layer 110 includes a plurality of first conductive lines 111, and the power module includes a plurality of power chips 200 and a plurality of first frames 300, with the plurality of power chips 200 and the plurality of first frames 300 connected to the corresponding first conductive lines 111.

[0103] The second frame 400 is connected to the second metal layer 120, specifically soldered to the upper surface of the second metal layer 120 using solder paste. One end of the second frame 400 extends from the package after encapsulation to serve as a pin for the power module. Corresponding to the arrangement direction of the first metal layer 110 and the second metal layer 120, the first frame 300 and the second frame 400 are located on opposite sides of the power chip 200. Figure 5As shown in the example, the second metal layer 120 includes a plurality of second conductive lines 121, the power module includes a plurality of second frames 400, a portion of the plurality of second conductive lines 121 is defined as frame lines 124, and the second frames 400 are connected to the corresponding frame lines 124.

[0104] Based on the third embodiment, referring to Figure 6 , Figure 7 In some embodiments, the power module further includes a control chip 500 and a first lead 610. The control chip 500 is connected to the second metal layer 120, specifically by being adhered to the upper surface of the second metal layer 120 with silver paste. Figure 5 As shown in the example, the second metal layer 120 includes a plurality of second conductive lines 121. At least one of the plurality of second conductive lines 121 is defined as a mounting line 122. The control chip 500 is connected to the upper surface of the mounting line 122. Compared with the other second conductive lines 121, the mounting line 122 has a larger area to facilitate the connection of the control chip 500.

[0105] In this embodiment, the first lead 610 is directly connected between the control chip 500 and the power chip 200. As mentioned above, since the first metal layer 110 and the second metal layer 120 are connected to the same side of the ceramic substrate 140, the height difference between the control chip 500 and the power chip 200 is small and there will be no relative vibration. Therefore, a series of problems caused by the deformation of the first lead 610 due to impact or vibration can be improved.

[0106] Based on the third embodiment, referring to Figure 6 , Figure 7 The power module also includes a control chip 500, a second lead 620, and a third lead 630. The control chip 500 is connected to the second metal layer 120, specifically by silver paste sintering onto the upper surface of the second metal layer 120. Figure 5 As shown in the example, the second metal layer 120 includes a plurality of second conductive lines 121. At least one of the plurality of second conductive lines 121 is defined as a mounting line 122, and at least another of the plurality of second conductive lines 121 is defined as a transition line 123. The control chip 500 is connected to the upper surface of the mounting line 122. Compared with the other second conductive lines 121, the mounting line 122 has a larger area to facilitate the connection of the control chip 500. The transition line 123 is disposed close to the first metal layer 110.

[0107] In this embodiment, the second lead 620 is connected to the control chip 500 and the transition line 123, and the third lead 630 is connected to the transition line 123 and the power chip 200. That is, the control chip 500 and the power chip 200 are connected via the second lead 620, the transition line 123, and the third lead 630. If directly connecting the control chip 500 and the power chip 200 via the first lead 610 would result in an excessively long first lead 610, the transition line 123 can be used to shorten the length of the third lead 630. Figure 5 Taking the transition line 123, control chip 500, and power chip 200 at the bottom as an example, the upper end of the transition line 123 extends to the control chip 500 at the bottom. The second lead 620 is connected to the upper end of the transition line 123 and the control chip 500 at the bottom. The lower end of the transition line 123 extends to the power chip 200 at the bottom. The third lead 630 is connected to the lower end of the transition line 123 and the power chip 200 at the bottom. Compared with the scheme of directly connecting the control chip 500 and the power chip 200 through the first lead 610, the lengths of the second lead 620 and the third lead 630 can be significantly shortened.

[0108] The above embodiments can be combined. Depending on the relative positions of the control chip 500 and each power chip 200, the two can be connected either through the first lead 610 or through the second lead 620 and the third lead 630.

[0109] Based on the third embodiment, in some embodiments the power module does not have a control chip 500, and in this case the second conductive line 121 is connected to the power chip 200 by a lead wire.

[0110] The fourth embodiment of the present invention also proposes a method for preparing a heat dissipation substrate, which includes the following steps:

[0111] In step S100, a ceramic substrate 140 is prepared. The first side of the ceramic substrate 140 has a first region 141 and a second region 142. Specifically, the first region 141 and the second region 142 are arranged adjacent to each other, for example, along the width direction of the ceramic substrate. For ease of understanding, the range of the first region 141 and the second region 142 is roughly marked by a dashed box in the figure. In addition, the ceramic substrate 140 also has a second side disposed opposite to the first side.

[0112] S200 prepares a first metal layer 110 in a first region 141 of a ceramic substrate 140 by a direct copper plating process. The first metal layer 110 has a plurality of first conductive lines 111.

[0113] S300 prepares a second metal layer 120 in the second region 142 of the ceramic substrate 140 by a direct copper plating process. The second metal layer 120 has a plurality of second conductive lines 121.

[0114] In this embodiment, the minimum spacing between adjacent first conductive lines 111 is greater than the minimum spacing between adjacent second conductive lines 121, and / or the minimum linewidth of the first conductive line 111 is greater than the minimum linewidth of the second conductive line 121. In the heat dissipation substrate prepared by the fabrication scheme of this embodiment, the first metal layer 110 and the second metal layer 120 are both connected to the same side surface of the ceramic substrate 140. When the first metal layer 110 is connected to the power chip and the second metal layer 120 is connected to the control chip, the height difference between the power chip and the control chip is also small, thereby shortening the length of the bonding wire. In addition, since the first metal layer 110 and the second metal layer 120 are simultaneously connected to the ceramic substrate 140, no relative vibration will occur between the power chip and the control chip. All of the above can improve a series of problems caused by the deformation of the bonding wire due to impact or vibration.

[0115] On the other hand, compared with the conductive line 31 of the traditional power module, the second conductive line 121 is disposed on the heat dissipation substrate 100 and is not limited by the frame manufacturing process. Therefore, while meeting the current requirements of the control chip, the minimum spacing between adjacent second conductive lines 121 can be smaller than the minimum spacing between adjacent first conductive lines 111, and / or the minimum line width of the second conductive line 121 is smaller than the minimum line width of the first conductive line 111. In this way, the volume of the power module can be reduced.

[0116] It should be noted that the fabrication scheme of the heat dissipation substrate in this embodiment may also include the step of forming a third metal layer 130 on the second side. The third metal layer 130 may also be fabricated using a direct copper plating process.

[0117] Based on the fourth embodiment, referring to Figure 8 In some embodiments, the method for preparing a first metal layer 110 in a first region 141 of a ceramic substrate 140 by a direct copper plating process includes the following steps:

[0118] S210 Prepare a first metal substrate 700 and connect the first metal substrate 700 to a first side of the ceramic substrate 140, for example, by sintering. After the first metal substrate 700 is connected to the first side, the first metal substrate 700 covers at least a portion of the first region 141 and at least a portion of the second region 142. In other words, the first metal substrate 700 may cover all of the first region 141 or a portion of the first region 141, and the first metal substrate 700 may cover at least a portion of the second region 142 accordingly.

[0119] S220 etches the first metal substrate 700 to form a first metal layer 110 and expose the second region 142. Specifically, the method of etching the first metal substrate 700 includes coating the upper side of the first metal substrate 700 with a dry film 1000 and performing exposure and development treatments, followed by etching with an etching solution. After etching, the first metal substrate 700 can form multiple first gaps, thereby separating multiple first conductive lines 111. Furthermore, the etched portion of the first metal substrate 700 also includes a portion covering the second region 142, so that the entire second region 142 is exposed.

[0120] S230 removes the remaining dry film, thereby obtaining an intermediate component with a first metal layer 110 formed on it.

[0121] Based on the intermediate components, refer to Figure 9 The method for preparing a second metal layer 120 in a second region 142 of a ceramic substrate 140 by direct copper plating includes the following steps:

[0122] S310 forms a metal film 800 in the exposed second region 142. Specifically, the metal film 800 can be formed by vacuum sputtering or other methods.

[0123] S320 performs electroplating on the metal film 800, thickening the metal film 800 to form the second metal substrate 900. Prior to electroplating, a dry film 1000 is coated onto the upper side of the first metal layer 110, concentrating the electroplating reaction on the metal film 800. After electroplating, the dry film 1000 on the upper side of the first metal layer 110 is removed.

[0124] S330 etches the second metal substrate 900 to form a second metal layer 120. Specifically, the method for etching the second metal substrate 900 includes coating a dry film 1000 on the upper side of the second metal substrate 900 and performing exposure and development treatments, followed by etching with an etching solution. After etching, the second metal substrate 900 can form multiple second gaps, thereby separating multiple second conductive lines 121.

[0125] S340 removes the remaining dry film and performs surface treatment to obtain a heat dissipation substrate having a first metal layer 110 and a second metal layer 120.

[0126] Based on the fourth embodiment, referring to Figure 10 In another embodiment, the method for preparing a first metal layer 110 in a first region 141 of a ceramic substrate 140 by a direct copper plating process includes the following steps:

[0127] S210 Prepare a first metal substrate 700 and connect the first metal substrate 700 to a first side of the ceramic substrate 140, for example, by sintering. After the first metal substrate 700 is connected to the first side, the first metal substrate 700 covers at least a portion of the first region 141, and the second region 142 of the metal substrate remains exposed.

[0128] S220 etches the first metal substrate 700 to form a first metal layer 110. Specifically, the method for etching the first metal substrate 700 includes coating a dry film 1000 on the upper side of the first metal substrate 700 and performing exposure and development treatments, followed by etching with an etching solution. After etching, the first metal substrate 700 can form multiple first gaps, thereby separating multiple first conductive lines 111.

[0129] S230 removes the remaining dry film, thereby obtaining an intermediate component with a first metal layer 110 formed on it.

[0130] Based on the above, the difference between this embodiment and the previous embodiment is that: after the first metal substrate 700 in the previous embodiment is connected to the ceramic substrate 140, it will cover at least part of the second region 142. Therefore, it is necessary to remove the part covering the second region 142 by etching process. In this embodiment, the first metal substrate 700 will not cover the second region 142 from the beginning, so the corresponding etching step can be omitted.

[0131] In this embodiment, the method for preparing the second metal layer 120 in the second region 142 of the ceramic substrate 140 by direct copper plating is the same as that in the previous embodiment, and will not be described again here.

[0132] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A method for preparing a heat dissipation substrate, characterized in that, Includes the following steps: Prepare a ceramic substrate, wherein a first side of the ceramic substrate has a first region and a second region; A first metal layer is prepared in the first region of the ceramic substrate by a direct copper plating process, the first metal layer having a plurality of first conductive lines; A second metal layer is prepared in the second region of the ceramic substrate by a direct copper plating process, the second metal layer having a plurality of second conductive lines; Wherein, the minimum spacing between adjacent first conductive lines is greater than the minimum spacing between adjacent second conductive lines, and / or, the minimum line width of the first conductive line is greater than the minimum line width of the second conductive line.

2. The method for preparing a heat dissipation substrate according to claim 1, characterized in that, The method for preparing the first metal layer in the first region of the ceramic substrate using a direct copper plating process, and preparing the second metal layer in the second region of the ceramic substrate using a direct copper plating process, includes: Prepare a first metal substrate, attach the first metal substrate to the first side of the ceramic substrate, and cover at least a portion of the first region and at least a portion of the second region; The first metal substrate is etched to form the first metal layer and expose the second region; A metal film is formed in the exposed second region; The metal film is electroplated to form a second metal substrate; The second metal substrate is etched to form the second metal layer.

3. The method for preparing a heat dissipation substrate according to claim 1, characterized in that, The method for preparing the first metal layer in the first region of the ceramic substrate using a direct copper plating process, and preparing the second metal layer in the second region of the ceramic substrate using a direct copper plating process, includes: Prepare a first metal substrate, connect the first metal substrate to the first side of the ceramic substrate, and at least cover the first area, while keeping the second area of ​​the metal substrate exposed. The first metal substrate is etched to form the first metal layer; A metal film is formed in the exposed second region; The metal film is electroplated to form a second metal substrate; The second metal substrate is etched to form the second metal layer.

4. A heat dissipation substrate for connecting chips, said heat dissipation substrate being prepared by the preparation method according to any one of claims 1 to 3, characterized in that, include: Ceramic substrate; A first metal layer is connected to a first side of the ceramic substrate and has multiple first conductive lines; The second metal layer is connected to the first side of the ceramic substrate and has a plurality of second conductive lines; A third metal layer is connected to the second side of the ceramic substrate, which is disposed opposite to the first side. Wherein, the minimum spacing between adjacent first conductive lines is greater than the minimum spacing between adjacent second conductive lines, and / or, the minimum line width of the first conductive line is greater than the minimum line width of the second conductive line.

5. The heat dissipation substrate according to claim 4, characterized in that, The minimum spacing between adjacent first conductive lines is 350 μm to 800 μm, and the minimum spacing between adjacent second conductive lines is 50 μm to 200 μm; And / or, the minimum linewidth of the first conductive line is 350 μm to 800 μm, and the minimum linewidth of the second conductive line is 65 μm to 200 μm.

6. The heat dissipation substrate according to claim 4, characterized in that, The thickness of the first metal layer is greater than the thickness of the second metal layer.

7. The heat dissipation substrate according to claim 6, characterized in that, The thickness of the first metal layer is 200 μm to 500 μm, and the thickness of the second metal layer is 50 μm to 75 μm.

8. The heat dissipation substrate according to claim 4, characterized in that, The current carrying capacity of the first conductive line is less than or equal to 200A, the current carrying capacity of the second conductive line is less than or equal to 50A, and the current carrying capacity of the first conductive line is greater than the current carrying capacity of the second conductive line.

9. A heat dissipation substrate for connecting chips, said heat dissipation substrate being prepared by the preparation method according to any one of claims 1 to 3, characterized in that, include: Ceramic substrate; A first metal layer is connected to a first side of the ceramic substrate and has multiple first conductive lines; The second metal layer is connected to the first side of the ceramic substrate and has a plurality of second conductive lines; A third metal layer is connected to the second side of the ceramic substrate, which is disposed opposite to the first side. The thickness of the first metal layer is greater than the thickness of the second metal layer.

10. A power module, characterized in that, include: The heat dissipation substrate according to any one of claims 4 to 9; A power chip is connected to the first metal layer; The first frame is connected to the first metal layer; The second frame is connected to the second metal layer.

11. The power module according to claim 10, characterized in that, The power module further includes a control chip and a first lead. The control chip is connected to the second metal layer, and the first lead is connected to the control chip and the power chip.

12. The power module according to claim 10, characterized in that, The power module further includes a control chip, a second lead, and a third lead. At least one of the plurality of second conductive lines is defined as an installation line, and at least another is a transition line. The control chip is connected to the second metal layer, the second lead is connected to the control chip and the transition line, and the third lead is connected to the transition line and the power chip.

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