Chip packaging structure and its fabrication method

Abstract

This invention provides a chip packaging structure and a method for fabricating the chip packaging structure, relating to the field of chip packaging technology. The chip packaging structure includes a carrier cover, a fixing adhesive layer, a sensing chip, a first dielectric layer, a wiring layer, a second dielectric layer, and solder balls. A patterned positioning opening is formed in the first dielectric layer, and then a slot is formed in the sensing chip within the patterned positioning opening to form a conductive via. The conductive via extends to the solder pad. Compared to existing technologies, this invention, by additionally setting a first dielectric layer and providing a patterned positioning opening on the first dielectric layer, determines the opening position of the conductive via. This achieves precise positioning of the via, avoiding back-side opening offset and ensuring product structural integrity. Furthermore, by setting the first dielectric layer, direct wiring on the sensing chip is avoided, and the first dielectric layer acts as a buffer, mitigating wiring delamination and ensuring product performance.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a chip packaging structure and a method for preparing the chip packaging structure. Background Technology

[0002] In existing technologies, the packaging of sensor chips typically involves mounting a wafer onto a glass substrate and then using through-silicon via (TSV) technology to directly connect the back of the sensor chip to the front pads. However, conventional TSV technology is prone to back-side via misalignment, which can damage the circuitry layers around the pads and the transistors inside the pads, ultimately harming the product. Furthermore, inconsistencies in the thermal expansion coefficients and Young's moduli of various materials within the package structure can cause delamination of the wiring layers on the chip recesses, affecting product performance. Summary of the Invention

[0003] The objectives of this invention include, for example, providing a chip packaging structure and a method for preparing the chip packaging structure, which can accurately position the through holes, avoid the phenomenon of back-side opening offset, ensure the integrity of the product structure, and at the same time reduce the phenomenon of wiring delamination, thus ensuring product performance.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a chip packaging structure, comprising:

[0006] Vehicle cover;

[0007] A fixing adhesive layer is disposed on one side of the vehicle cover plate;

[0008] A sensing chip is disposed on the side of the fixing adhesive layer away from the carrier cover plate;

[0009] A first dielectric layer is disposed on the surface of the sensing chip away from the carrier cover plate;

[0010] A wiring layer is disposed on the side of the first dielectric layer away from the vehicle cover plate;

[0011] The second dielectric layer is disposed on the side of the first dielectric layer away from the vehicle cover plate and covers the wiring layer.

[0012] Solder balls are disposed on the side of the second dielectric layer away from the carrier cover and are electrically connected to the wiring layer;

[0013] The sensing chip has a pad on the side where it is bonded to the adhesive layer. The first dielectric layer has a patterned positioning opening corresponding to the pad. The sensing chip within the patterned positioning opening has a conductive via extending through the pad. The wiring layer extends to the patterned positioning opening and the conductive via, and is electrically connected to the pad through the conductive via. The diameter of the conductive via is smaller than the diameter of the patterned positioning opening. The patterned positioning opening is used to position the conductive via.

[0014] In an optional embodiment, the fixing adhesive layer is provided with an optical groove, the central region of the sensing chip covers the optical groove, and the central region of the sensing chip is provided with a sensing device, the sensing device corresponding to the optical groove.

[0015] In an optional embodiment, the sidewall of the conductive via is provided with a bonding layer, one end of which is connected to the pad and the other end extends to the pattern positioning opening, and the wiring layer is bonded to the bonding layer.

[0016] In an optional implementation, the diameter of the pattern positioning opening is less than or equal to the diameter of the pad.

[0017] In an optional embodiment, the edge of the sensing chip is provided with a buffer groove so that the central region of the sensing chip protrudes to form a boss, and the first dielectric layer, the wiring layer and the second dielectric layer all extend to the buffer groove.

[0018] In an optional embodiment, the buffer groove is filled with a first buffer layer, which is disposed on the side of the second medium layer away from the vehicle cover.

[0019] In an optional embodiment, the edge sidewall of the sensing chip is further provided with a second buffer layer, which extends to the edge sidewall of the fixing adhesive layer and is embedded between the carrier cover and the first dielectric layer.

[0020] In an optional embodiment, a third medium layer is further provided on the side of the boss portion away from the vehicle cover plate, and the third medium layer is disposed between the boss portion and the first medium layer.

[0021] In an optional embodiment, a metal pillar is further provided in the fixing adhesive layer, one end of which is joined to the carrier cover plate and the other end is connected to the solder pad.

[0022] In an optional embodiment, the surface of the vehicle cover near the fixing adhesive layer is provided with a receiving groove, and the metal column extends into the receiving groove.

[0023] Secondly, the present invention provides a method for fabricating a chip packaging structure, used to fabricate the chip packaging structure as described in the foregoing embodiments, the method comprising:

[0024] A fixing adhesive layer is formed on the vehicle cover plate;

[0025] A sensor chip is mounted on the adhesive layer.

[0026] A first dielectric layer is disposed on the surface of the sensing chip away from the vehicle cover plate;

[0027] A groove is made on the surface of the first dielectric layer to form a patterned positioning opening;

[0028] A conductive via is formed by slotting the surface of the sensing chip within the graphic positioning opening.

[0029] A wiring layer is provided on the side of the first dielectric layer away from the vehicle cover plate;

[0030] A second dielectric layer is disposed on the side of the first dielectric layer away from the vehicle cover plate, and the second dielectric layer covers the wiring layer.

[0031] Solder balls are formed on the side of the second dielectric layer away from the carrier cover plate, and the solder balls are electrically connected to the wiring layer;

[0032] The sensing chip has a pad on the side where it is bonded to the fixing adhesive layer. The pattern positioning opening corresponds to the pad. The conductive via extends through the pad. The wiring layer extends to the pattern positioning opening and the conductive via, and is electrically connected to the pad through the conductive via. The diameter of the conductive via is smaller than the diameter of the pattern positioning opening.

[0033] In an optional embodiment, prior to the step of mounting the sensor chip on the adhesive layer, the preparation method further includes:

[0034] An optical groove is formed by carving a groove in the fixing adhesive layer;

[0035] The central region of the sensing chip covers the optical groove, and a sensing device is disposed in the central region of the sensing chip, the sensing device corresponding to the optical groove.

[0036] In an optional embodiment, prior to the step of forming a first dielectric layer on the surface of the sensing chip away from the carrier cover, the fabrication method further includes:

[0037] The edge region of the sensing chip is thinned to form a buffer groove, so that the central region of the sensing chip protrudes to form a boss.

[0038] In an optional embodiment, prior to the step of forming a first dielectric layer on the surface of the sensing chip away from the carrier cover, the fabrication method further includes:

[0039] A third dielectric layer is formed on the surface of the sensing chip on the side away from the carrier cover.

[0040] A buffer opening is formed by slotting in the third dielectric layer, and the buffer opening is located in the edge region of the sensing chip.

[0041] The sensing chip and the fixing adhesive layer are cut using the buffer opening as the cutting path, and a cutting groove is formed;

[0042] A second buffer layer is formed by filling the cut groove with a buffer material.

[0043] In an optional embodiment, after the step of filling the cutting groove with buffer material to form a second buffer layer, the preparation method further includes:

[0044] The third dielectric layer is removed by grinding.

[0045] In an optional embodiment, after the step of forming solder balls by planting them on the side of the second dielectric layer away from the carrier cover, the preparation method further includes:

[0046] The sensor chip is cut using the second buffer layer as the cutting path.

[0047] The beneficial effects of the embodiments of the present invention include, for example:

[0048] The chip packaging structure and its fabrication method provided in this invention involve setting a fixing adhesive layer on a carrier cover plate, bonding a sensing chip to the fixing adhesive layer, and then setting a first dielectric layer on the surface of the sensing chip. A patterned positioning opening is first formed in the first dielectric layer, corresponding to the position of the pad. Then, a slot is formed in the sensing chip within the patterned positioning opening to form a conductive via, which extends to the pad. A wiring layer, a second dielectric layer, and solder balls are then sequentially set. The wiring layer extends to the patterned positioning opening and the conductive via, and is electrically connected to the pad through the conductive via. The diameter of the conductive via is smaller than the patterned positioning opening, which is used to position the conductive via. Compared to existing technologies, this invention, by additionally setting a first dielectric layer and a patterned positioning opening on it, determines the opening position of the conductive via. This achieves precise positioning of the via, avoiding back-side opening offset and ensuring product structural integrity. Furthermore, the first dielectric layer avoids direct wiring on the sensing chip and acts as a buffer, mitigating wiring delamination and ensuring product performance. Attached Figure Description

[0049] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a schematic diagram of the chip packaging structure provided in the first embodiment of the present invention;

[0051] Figure 2 for Figure 1 A schematic diagram showing the positional relationship between the first dielectric layer and the conductive via.

[0052] Figures 3 to 10 A process flow diagram of the method for fabricating the chip packaging structure provided in the first embodiment of the present invention;

[0053] Figure 11 This is a schematic diagram of the chip packaging structure provided in the second embodiment of the present invention;

[0054] Figure 12 This is a schematic diagram of the chip packaging structure provided in the third embodiment of the present invention;

[0055] Figures 13 to 15 A process flow diagram of the method for fabricating the chip packaging structure provided in the third embodiment of the present invention;

[0056] Figure 16 This is a schematic diagram of the chip packaging structure provided in the fourth embodiment of the present invention;

[0057] Figure 17 This is a schematic diagram of the chip packaging structure provided in the fifth embodiment of the present invention.

[0058] Icons: 100 - Chip package structure; 110 - Carrier cover; 111 - Receiving groove; 120 - Fixing adhesive layer; 121 - Optical groove; 130 - Sensor chip; 131 - Solder pad; 133 - Conductive via; 135 - Sensor device; 137 - Bonding layer; 139 - Boss; 140 - First dielectric layer; 141 - Pattern positioning opening; 150 - Wiring layer; 160 - Second dielectric layer; 170 - Solder ball; 180 - Buffer groove; 181 - First buffer layer; 183 - Second buffer layer; 185 - Third dielectric layer; 186 - Buffer opening; 187 - Metal pillar. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0060] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0061] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0062] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0063] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0064] As disclosed in the background section, in the prior art, for sensing chips, through-silicon via (TSV) technology is typically used to directly connect the front pads of the chip through the back of the sensing chip, and then wiring is performed.

[0065] This through-hole wiring method has the following problems:

[0066] 1. The process of directly opening holes on the back of the chip is prone to misalignment, which can damage the circuit layer around the chip pads and the transistors (P / N junctions) inside the chip pads, thus impairing the product's performance.

[0067] 2. In existing technologies, wiring processes are usually performed directly after through-hole drilling. However, the inconsistent thermal expansion coefficients and Young's modulus of various materials inside the packaging structure can easily lead to delamination of the wiring layer on the chip recess, affecting product performance.

[0068] 3. In the existing technology, the TSV metal pillars and the edge of the circuit layer have no insulating layer, which easily leads to leakage current, resulting in parasitic effects and capacitance effects, causing a decrease in transmission efficiency and silicon sidewall cracks.

[0069] 4. Furthermore, chip thinning technology has emerged to reduce the difficulty of perforation. However, after chip thinning, its structural strength is greatly reduced, and light waves in the photosensitive area can easily penetrate the chip body, resulting in diffraction and refraction, which in turn causes ghosting and other phenomena in the photosensitive area, affecting the photosensitive performance.

[0070] To address the aforementioned problems, this invention provides a novel chip packaging structure. It should be noted that, without conflict, the features in the embodiments of this invention can be combined with each other.

[0071] First Embodiment

[0072] See Figure 1 and Figure 2 This embodiment provides a chip packaging structure 100 that can accurately position vias, avoiding back-side via misalignment, ensuring product structural integrity, mitigating wiring delamination, and guaranteeing product performance. Furthermore, it can prevent leakage current at the vias, thus avoiding parasitic and capacitive effects, thereby ensuring transmission efficiency and the stability of the via structure.

[0073] This embodiment provides a chip packaging structure 100, including a carrier cover 110, a fixing adhesive layer 120, a sensing chip 130, a first dielectric layer 140, a wiring layer 150, a second dielectric layer 160, and solder balls 170. The fixing adhesive layer 120 is disposed on one side of the carrier cover 110; the sensing chip 130 is disposed on the side of the fixing adhesive layer 120 away from the carrier cover 110; the first dielectric layer 140 is disposed on the surface of the sensing chip 130 away from the carrier cover 110; the wiring layer 150 is disposed on the side of the first dielectric layer 140 away from the carrier cover 110; the second dielectric layer 160 is disposed on the side of the first dielectric layer 140 away from the carrier cover 110 and covers the wiring layer 150; the solder balls 170 are disposed on... The second dielectric layer 160 is located on the side away from the carrier cover plate 110 and is electrically connected to the wiring layer 150. A pad 131 is provided on the side where the sensing chip 130 is joined to the fixing adhesive layer 120. A pattern positioning opening 141 is provided on the first dielectric layer 140, corresponding to the pad 131. A conductive via 133 is provided on the sensing chip 130 within the pattern positioning opening 141. The conductive via 133 extends to the pad 131. The wiring layer 150 extends to the pattern positioning opening 141 and the conductive via 133 and is electrically connected to the pad 131 through the conductive via 133. The diameter of the conductive via 133 is smaller than the diameter of the pattern positioning opening 141. The pattern positioning opening 141 is used to position the open conductive via 133.

[0074] In this embodiment, the fixing adhesive layer 120 can be formed by applying and curing an adhesive layer on the carrier cover plate 110 using a spin coater. The sensing chip 130 can be bonded and fixed on the adhesive layer, and its pads 131 are bonded to the fixing adhesive layer 120. In actual fabrication, a fixing adhesive layer 120 can be first set on the carrier cover plate 110, and the sensing chip 130 can be bonded to the fixing adhesive layer 120. Then, a first dielectric layer 140 can be set on the surface of the sensing chip 130. A pattern positioning opening is first made in the first dielectric layer 140, which corresponds to the position of the pad 131. Then, a slot is made in the sensing chip 130 in the pattern positioning opening to form a conductive via 133. The conductive via 133 extends to the pad 131. Then, a wiring layer 150, a second dielectric layer 160 and solder balls 170 are set in sequence. The wiring layer 150 extends to the pattern positioning opening and the conductive via 133, and is electrically connected to the pad 131 through the conductive via 133. The diameter of the conductive via 133 is smaller than that of the pattern positioning opening 141. The pattern positioning opening 141 is used to position the conductive via 133. Since the aperture of the pattern positioning opening 141 is slightly larger and can serve as a positioning slot, the silicon through-hole process can be performed after positioning by the pattern positioning opening 141. On the one hand, it can achieve precise positioning of the through-hole, avoid the phenomenon of back hole offset, and ensure the integrity of the product structure. On the other hand, by setting the first dielectric layer 140, it can avoid direct wiring on the sensor chip 130, and the first dielectric layer 140 can act as a buffer to reduce the phenomenon of wiring delamination and ensure product performance.

[0075] It should be noted that in this embodiment, the photosensitive chip has a front and a back side. The front side is attached to the fixing adhesive layer 120, and the back side is provided with a first dielectric layer 140. The first dielectric layer 140 covers the back side of the photosensitive chip, and the front pad 131 of the photosensitive chip can be scanned by an IR infrared laser detector. After determining that the pad 131 is the child, an image is formed. Then, the preset mask image of the first dielectric layer 140 is obtained again. After the two images are accurately matched, plasma etching or laser grooving is performed on the preset position to form a pattern positioning opening 141. This facilitates the subsequent grooving in the pattern positioning opening 141 to form a conductive via 133, ensuring that the conductive via 133 corresponds to the pad 131 and avoiding the problem of through-hole misalignment during etching.

[0076] It is worth noting that in traditional technology, it is difficult to achieve accurate positioning of pad 131 using only IR scanning, mainly because: 1. The transistor or metal layer around the bottom of the traditional chip pad 131 is relatively thin; 2. There are voids in the adhesive layer at the bottom of the chip pad 131; 3. The chip material causes IR transmittance to be too strong, so the image after IR scanning is prone to problems of unclear layers and blurriness. However, in this application, by combining mask images, accurate positioning can be achieved, and the slot is formed to create the pattern positioning opening 141.

[0077] In this embodiment, the fixing adhesive layer 120 is provided with an optical groove 121, the central region of the sensing chip 130 covers the optical groove 121, and a sensing device 135 is provided in the central region of the sensing chip 130, corresponding to the optical groove 121. Specifically, the carrier cover plate 110 in this embodiment can be a transparent cover plate with light transmittance, such as glass, silicon substrate, or transparent polymer composite material. Here, the sensing chip 130 can be a photosensitive chip, such as an image sensor or filter, with the sensing device 135 provided in its central region, corresponding to the optical groove 121, which can achieve good optical performance. Of course, the carrier cover plate 110 can also be made of an opaque material, such as a metal material. In this case, the sensing chip 130 can be a sensing chip, such as a gyroscope or capacitive sensor.

[0078] It should be noted that in this embodiment, the pad 131 is bonded to the surface of the carrier cover plate 110, and the pad 131 is located outside the optical groove 121 and spaced apart from the optical groove 121, which can prevent the pad 131 from being bonded to the optical groove 121 and affecting the photosensitivity.

[0079] In this embodiment, a bonding layer 137 is provided on the sidewall of the conductive via 133. One end of the bonding layer 137 is connected to the pad 131, and the other end extends to the pattern positioning opening 141. The wiring layer 150 is bonded to the bonding layer 137. Specifically, the bonding layer 137 can be an organic material such as epoxy resin or polyimide, or a non-insulating material such as silicon oxide or silicon nitride. It can work with the first dielectric layer 140 as an insulating layer to prevent leakage in the wiring layer 150. Furthermore, in this embodiment, the contact area between the pad 131 and the wiring layer 150 is small, thereby reducing parasitic and capacitive effects and improving device performance.

[0080] In this embodiment, the diameter of the pattern positioning opening 141 is less than or equal to the diameter of the pad 131. Specifically, the diameter of the pattern positioning opening 141 is smaller than the diameter of the pad 131 and larger than the diameter of the conductive via 133. Therefore, it can be ensured that the conductive via 133 will not penetrate to the periphery of the pad 131, further avoiding the problem of silicon via displacement during etching.

[0081] It is worth noting that in this embodiment, the second dielectric layer 160 covers the wiring layer 150, which can act as a buffer, effectively avoiding stress buffering problems, and can also prevent external moisture from entering the wiring layer 150 or the first dielectric layer 140, avoiding delamination problems caused by moisture erosion, and providing good protection for the sidewalls of the wiring layer 150. Here, both the first dielectric layer 140 and the second dielectric layer 160 can be dielectric materials, which can play a good buffering and protective role, and the first dielectric layer 140 and the second dielectric layer 160 can be high molecular composite materials such as epoxy resin, polyimide, and benzocyclobutene.

[0082] This embodiment also provides a method for fabricating a chip package structure 100, which includes the following steps:

[0083] S1: A fixing adhesive layer 120 is formed on the vehicle cover plate 110.

[0084] join Figure 3 Specifically, a carrier cover plate 110 can be provided. The carrier cover plate 110 can be a transparent material such as glass, silicon substrate, or transparent polymer composite material, which is suitable for mounting optical chips. At the same time, the carrier cover plate 110 can also be an opaque material such as opaque polymer composite material or metal material, which is suitable for mounting sensors.

[0085] Furthermore, in this embodiment, after forming the fixing adhesive layer 120, it is necessary to groove the fixing adhesive layer 120 to form an optical groove 121. Specifically, an adhesive layer is formed on the carrier cover plate 110 by spin coating, and after curing, the fixing adhesive layer 120 is formed. Then, the optical groove 121 is formed by grooving the fixing adhesive layer 120. The grooving process can be etching or laser grooving. The fixing adhesive layer 120 can be a thermosetting adhesive layer, such as epoxy resin, polyimide, benzocyclobutene, and other polymer composite materials.

[0086] S2: Mount the sensor chip 130 on the adhesive layer 120.

[0087] Specifically, see Figure 4 A wafer with multiple sensor chips 130 is mounted on a fixing adhesive layer 120. At this point, the wafer has completed the chip fabrication process, and subsequent dicing will form multiple sensor chips 130. During mounting, the central area of ​​the sensor chip 130 can be made to cover the optical groove 121. A bonding pad 131 is also provided on the side where the photosensitive chip is bonded to the fixing adhesive layer 120. During wafer mounting, a baking process can be used to solidify the wafer.

[0088] In this embodiment, a solder pad is provided on the back of the sensing chip 130 and is attached to the fixing adhesive layer 120. Furthermore, a sensing device 135 is provided in the central area of ​​the sensing chip 130. The sensing device 135 corresponds to the optical groove 121 to realize the photosensitive function.

[0089] S3: A first dielectric layer 140 is disposed on the surface of the sensing chip 130 away from the carrier cover plate 110.

[0090] Specifically, see Figure 5 A dielectric material can be coated on the wafer surface by spin coating, deposition, or other methods to form a first dielectric layer 140. The first dielectric layer 140 can be a photoresist material, which can prevent light waves from penetrating through the photosensitive chip layer and avoid diffraction and refraction problems, thus preventing water ripple phenomena in subsequent openings and problems such as poor bonding of the wiring layer 150.

[0091] S4: A groove is made on the surface of the first dielectric layer 140 to form a patterned positioning opening 141.

[0092] Specifically, see Figure 6 Before forming the first dielectric layer 140, the pads 131 on the front side of the photosensitive chip can be scanned using an IR infrared laser detector to determine the position of the pads 131 and form an image. Then, the mask pattern layer of the pads 131 is acquired to form another image. After precise matching of the two images, an exposure and development process can be performed on the first dielectric layer 140 to form the pattern positioning opening 141, exposing the surface of the photosensitive chip. The scanning method ensures that the position of the pattern positioning opening 141 corresponds to the position of the pads 131, and it is necessary to ensure that the diameter of the pattern positioning opening 141 is smaller than the diameter of the pads 131.

[0093] S5: A conductive via 133 is formed by slotting the surface of the sensing chip 130 within the graphic positioning opening 141.

[0094] Specifically, see Figure 7 After forming the pattern positioning opening 141, using the pattern positioning opening 141 as a positioning point, a conductive via 133 is formed within the opening by laser grooving or plasma etching. The hole-making process can refer to the conventional through-silicon via (TSV) process. The conductive via 133 extends to the pad 131, and the diameter of the conductive via 133 is smaller than the diameter of the pattern positioning opening 141 and also smaller than the diameter of the pad 131. Plasma dry etching can be performed using a mixed plasma gas of O2 and SF6 to etch the hole.

[0095] After forming the conductive via 133, a bonding layer 137 can be formed in the conductive via 133, and the pattern positioning opening 141 can be filled by the bonding layer 137 to form the TSV surface pad 131 structure. The height of the first dielectric layer 140 is H1. The first dielectric layer 140 and the bonding layer 137 can be used as an insulating layer to avoid leakage in the wiring layer 150.

[0096] S6: A wiring layer 150 is provided on the side of the first dielectric layer 140 away from the vehicle cover plate 110.

[0097] Specifically, see Figure 8 A metal layer can be first electroplated in the conductive via 133, and then a wiring layer 150 can be formed by electroplating or sputtering on the surface of the first dielectric layer 140. The wiring layer 150 extends to the pattern positioning opening 141 and the conductive via 133, and is electrically connected to the pad 131 through the conductive via 133.

[0098] S7: A second dielectric layer 160 is provided on the side of the first dielectric layer 140 away from the carrier cover plate 110, and the second dielectric layer 160 covers the wiring layer 150.

[0099] Specifically, see Figure 9 After the wiring layer 150 is formed, a dielectric material can be spin-coated again onto the surfaces of the wiring layer 150 and the first dielectric layer 140. After curing, a second dielectric layer 160 is formed. The second dielectric layer 160 can cover the wiring layer 150, providing good protection. The second dielectric layer 160 can be made of materials such as silicon nitride, silicon oxynitride, polyimide, or benzocyclobutene.

[0100] After the second dielectric layer 160 is formed, a photomask can be placed on the second dielectric layer 160, and an opening in the pattern layer can be formed by the exposure and development process. Then, a metal layer can be formed by electroplating metal in the opening to facilitate subsequent ball placement.

[0101] S8: Solder balls 170 are formed on the side of the second dielectric layer 160 away from the carrier cover plate 110, and solder balls 170 are electrically connected to the wiring layer 150.

[0102] Specifically, see Figure 10 Solder balls 170 are formed by attaching solder balls to the metal layer with openings in the pattern layer using stencil printing or electroplating. These solder balls 170 are electrically connected to the wiring layer 150. Finally, a cutting process is performed to obtain individual products.

[0103] In summary, this embodiment provides a chip packaging structure 100 and its fabrication method. A fixing adhesive layer 120 is provided on a carrier cover plate 110, and a sensing chip 130 is bonded to the fixing adhesive layer 120. Then, a first dielectric layer 140 is provided on the surface of the sensing chip 130. A pattern positioning opening is first formed in the first dielectric layer 140, and the pattern positioning opening corresponds to the position of the pad 131. Then, a slot is formed in the sensing chip 130 within the pattern positioning opening to form a conductive via 133, which extends to the pad 131. Then, a wiring layer 150, a second dielectric layer 160, and solder balls 170 are sequentially provided. The wiring layer 150 extends to the pattern positioning opening and the conductive via 133, and is electrically connected to the pad 131 through the conductive via 133. The diameter of the conductive via 133 is smaller than that of the pattern positioning opening 141, which is used to position the conductive via 133. Compared to existing technologies, this embodiment adds a first dielectric layer 140 and a patterned positioning opening 141 on the first dielectric layer 140. The opening position of the conductive via 133 is determined by the patterned positioning opening 141. On the one hand, it can achieve precise positioning of the via, avoid the phenomenon of back-side opening offset, and ensure the integrity of the product structure. On the other hand, by setting the first dielectric layer 140, it can avoid direct wiring on the sensing chip 130, and the first dielectric layer 140 can play a buffering role, reduce the phenomenon of wiring delamination, and ensure product performance.

[0104] Second Embodiment

[0105] See Figure 11 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0106] In this embodiment, a buffer groove 180 is provided on the edge of the sensing chip 130 so that the central area of ​​the sensing chip 130 protrudes to form a boss 139. The first dielectric layer 140, the wiring layer 150 and the second dielectric layer 160 all extend to the buffer groove 180. The buffer groove 180 is filled with a first buffer layer 181, which is disposed on the side of the second dielectric layer 160 away from the vehicle cover plate 110.

[0107] It is worth noting that in this embodiment, by setting a buffer groove 180 at the edge of the sensing chip 130, the edge of the sensing chip 130 can be effectively thinned. After thinning, the first dielectric layer 140, wiring layer 150, and second dielectric layer 160 are fabricated. Furthermore, the pattern positioning opening 141 is located within the buffer groove 180, which reduces the perforation depth when forming a through-hole, thereby effectively reducing the difficulty of perforation. In addition, the additional first dielectric layer 140 in this embodiment can also compensate for the reduced structural strength caused by thinning the sensing chip 130 with the buffer groove 180. Moreover, thinning the sensing chip 130 can also improve the transmittance of the IR laser through the core, thereby further improving the accuracy of slotting.

[0108] It should be noted that the first buffer layer 181 can be integrally formed with the second dielectric layer 160, or the preparation of the second dielectric layer 160 can be omitted and the first buffer layer 181 can be formed directly.

[0109] In this embodiment, by providing a first buffer layer 181, the stress buffering problem caused by the reduced structural strength after the edge thinning of the sensing chip 130 can be effectively avoided. Simultaneously, the first buffer layer 181 can also effectively prevent moisture from entering the second dielectric layer 160. Furthermore, the first buffer layer 181 can enhance the sidewall structural strength, thereby further preventing delamination caused by internal stress and moisture, effectively achieving sidewall protection. The material of the first buffer layer 181 can be a polymer composite material such as epoxy resin, polyimide, or benzocyclobutene.

[0110] This embodiment also provides a method for preparing a chip packaging structure 100, the basic steps of which are the same as those in the first embodiment. The difference in this preparation method is that, before step S3, a step of forming a buffer groove 180 by slotting is included.

[0111] Specifically, before setting the first dielectric layer 140, a buffer trench 180 can be formed in the edge region of the sensing chip 130 by etching, laser grooving, or grinding processes to achieve local thinning of the sensing chip 130. Furthermore, a buffer material can be filled into the buffer trench 180 by filling or deposition to form the first buffer layer 181.

[0112] Third Embodiment

[0113] See Figure 12 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the second embodiment.

[0114] In this embodiment, a second buffer layer 183 is further provided on the edge sidewall of the sensing chip 130. The second buffer layer 183 extends to the edge sidewall of the fixing adhesive layer 120 and is embedded between the carrier cover plate 110 and the first dielectric layer 140. Specifically, the second buffer layer 183 can cover the fixing adhesive layer 120 and the sidewall of the sensing chip 130, thereby preventing the sidewall of the sensing chip 130 from being exposed and providing good protection for the sidewall of the sensing chip 130.

[0115] This embodiment also provides a method for fabricating a chip packaging structure 100. The basic steps can be referred to in the first embodiment or the second embodiment, wherein steps S1 and S2 are the same as in the first embodiment. The difference from the first embodiment is that this embodiment further includes the step of forming a second buffer layer 183 after step S2:

[0116] First, see Figure 13 A third dielectric layer 185 is formed on the surface of the sensing chip 130 away from the carrier cover plate 110. A buffer opening 186 is then formed by slotting in the third dielectric layer 185. Specifically, a dielectric material can be coated onto the surface of the sensing chip 130 using a spin coating process, and the third dielectric layer 185 is formed after curing. Then, a buffer opening 186 is formed in the third dielectric layer 185 using a laser slotting or etching process. This buffer opening 186 is located in the edge region of the sensing chip 130 and corresponds to the periphery of the pad 131, to avoid affecting the effective area of ​​the sensing chip 130.

[0117] The sensing chip 130 and the fixing adhesive layer 120 are then cut using the buffer opening 186 as the cutting path, forming a cutting groove. Specifically, the sensing chip 130 and the fixing adhesive layer 120 can be cut using a cutter to release wafer stress and form a cutting groove.

[0118] See Figure 14 Then, a buffer material is filled into the cutting groove to form a second buffer layer 183. Specifically, a buffer material, such as epoxy resin, polyimide, benzocyclobutene, or other polymer composite materials, is filled into the cutting groove to form the second buffer layer 183.

[0119] See Figure 15 Finally, the third dielectric layer 185 is removed by grinding. Specifically, the third dielectric layer 185 can be removed by grinding to expose the sensor chip 130.

[0120] After the second buffer layer 183 is fabricated, a buffer trench 180 can be formed in the edge region of the sensor chip 130 by etching, laser grooving, or grinding processes to achieve local thinning of the sensor chip 130. Then, steps S3-S7 as in the first embodiment are performed, and buffer material is filled into the buffer trench 180 by filling or deposition to form the first buffer layer 181. Then, step S8 as in the first embodiment is performed to complete the ball implantation.

[0121] After the ball placement is completed, the sensor chip 130 can be cut using the second buffer layer 183 as the cutting path. During cutting, the second buffer layer 183 can be partially removed, i.e., a portion of the second buffer layer 183 is retained to form the chip package structure 100 provided in this embodiment, or the second buffer layer 183 can be completely removed to form the chip package structure 100 provided in the second embodiment. It should be noted that using the second buffer layer 183 as the cutting path here avoids directly cutting the first dielectric layer 140 and the wiring layer 150, which can effectively avoid line pulling and ensure the accuracy of cutting and the stability of the package structure.

[0122] Fourth embodiment

[0123] See Figure 16 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the third embodiment.

[0124] In this embodiment, a third dielectric layer 185 is also provided on the side of the boss portion 139 away from the carrier cover plate 110, and the third dielectric layer 185 is disposed between the boss portion 139 and the first dielectric layer 140. Specifically, when forming the second buffer layer 183, the third dielectric layer 185 may not need to be ground, while when slotting to form the buffer groove 180, the third dielectric layer 185 at the edge portion may be removed, leaving the third dielectric layer 185 on the boss portion 139. By providing the third dielectric layer 185, it can serve as a photoresist layer, thereby preventing light penetration, preventing penetration during IR detection, and improving scanning accuracy.

[0125] Fifth Embodiment

[0126] See Figure 17 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the second embodiment.

[0127] In this embodiment, a metal pillar 187 is also provided in the fixing adhesive layer 120. One end of the metal pillar 187 is connected to the carrier cover plate 110, and the other end is connected to the pad 131. Specifically, the metal pillar 187 can be a copper layer, and its size is the same as that of the pad 131. By providing the metal pillar 187, the thickness of the detected image during IR detection can be increased, thereby improving the image clarity. Furthermore, the metal pillar 187 can improve the bonding force of the pad 131, thereby improving the bonding force between the carrier cover plate 110, the fixing adhesive layer 120, and the sensing chip 130, and preventing delamination. The heat dissipation pillar can also improve heat dissipation performance and prevent the pad 131 from breaking down, ensuring electrical conductivity.

[0128] In this embodiment, a receiving groove 111 is provided on the surface of the carrier cover plate 110 near the fixing adhesive layer 120, and the metal pillar 187 extends into the receiving groove 111. Specifically, the size of the receiving groove 111 is the same as the size of the pad 131. The receiving groove 111 can be formed by pre-grooving on the carrier cover plate 110. Then, when preparing the metal pillar 187, it can grow upward from the receiving groove 111 until the fixing adhesive layer 120 is exposed, which facilitates connection with the pad 131.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: Vehicle cover; A fixing adhesive layer is disposed on one side of the vehicle cover plate; A sensing chip is disposed on the side of the fixing adhesive layer away from the carrier cover plate; A first dielectric layer is disposed on the surface of the sensing chip away from the carrier cover plate; A wiring layer is disposed on the side of the first dielectric layer away from the vehicle cover plate; The second dielectric layer is disposed on the side of the first dielectric layer away from the vehicle cover plate and covers the wiring layer. Solder balls are disposed on the side of the second dielectric layer away from the carrier cover and are electrically connected to the wiring layer; The sensing chip has a pad on the side where it is bonded to the fixing adhesive layer. The first dielectric layer has a patterned positioning opening corresponding to the pad. The sensing chip within the patterned positioning opening has a conductive via extending through the pad. The wiring layer extends to the patterned positioning opening and the conductive via, and is electrically connected to the pad through the conductive via. The diameter of the conductive via is smaller than the diameter of the patterned positioning opening. The patterned positioning opening is used to position the conductive via. The edge of the sensing chip is provided with a buffer groove so that the central area of ​​the sensing chip protrudes to form a boss. The first dielectric layer, the wiring layer and the second dielectric layer all extend to the buffer groove. The edge sidewall of the sensing chip is also provided with a second buffer layer. The second buffer layer extends to the edge sidewall of the fixing adhesive layer and is embedded between the carrier cover plate and the first dielectric layer. The second buffer layer is used to cover the fixing adhesive layer and the sidewall of the sensing chip. The buffer groove is filled with a first buffer layer, which is disposed on the side of the second medium layer away from the vehicle cover plate. A third dielectric layer is also provided on the side of the boss portion away from the vehicle cover plate. The third dielectric layer is disposed between the boss portion and the first dielectric layer, wherein the third dielectric layer serves as a photoresist layer.

2. The chip packaging structure according to claim 1, characterized in that, The fixing adhesive layer is provided with an optical groove, the central area of ​​the sensing chip covers the optical groove, and the central area of ​​the sensing chip is provided with a sensing device, which corresponds to the optical groove.

3. The chip packaging structure according to claim 1, characterized in that, The conductive via has a bonding layer on its sidewall. One end of the bonding layer is connected to the pad, and the other end extends to the pattern positioning opening. The wiring layer is bonded to the bonding layer.

4. The chip packaging structure according to claim 1, characterized in that, The diameter of the pattern positioning opening is less than or equal to the diameter of the pad.

5. The chip packaging structure according to claim 1, characterized in that, The fixing adhesive layer also includes a metal pillar, one end of which is connected to the carrier cover plate and the other end is connected to the solder pad.

6. The chip packaging structure according to claim 5, characterized in that, The surface of the vehicle cover plate near the fixing adhesive layer is provided with a receiving groove, and the metal column extends into the receiving groove.

7. A method for fabricating a chip packaging structure, characterized in that, The method for preparing the chip packaging structure as described in claim 1 includes: A fixing adhesive layer is formed on the vehicle cover plate; A sensor chip is mounted on the adhesive layer. A first dielectric layer is disposed on the surface of the sensing chip away from the vehicle cover plate; A groove is made on the surface of the first dielectric layer to form a patterned positioning opening; A conductive via is formed by slotting the surface of the sensing chip within the graphic positioning opening. A wiring layer is provided on the side of the first dielectric layer away from the vehicle cover plate; A second dielectric layer is disposed on the side of the first dielectric layer away from the vehicle cover plate, and the second dielectric layer covers the wiring layer. Solder balls are formed on the side of the second dielectric layer away from the carrier cover plate, and the solder balls are electrically connected to the wiring layer; The sensing chip has a pad on the side where it is bonded to the fixing adhesive layer. The pattern positioning opening corresponds to the pad. The conductive via extends through the pad. The wiring layer extends to the pattern positioning opening and the conductive via, and is electrically connected to the pad through the conductive via. The diameter of the conductive via is smaller than the diameter of the pattern positioning opening.

8. The method for fabricating a chip packaging structure according to claim 7, characterized in that, Prior to the step of mounting the sensor chip on the adhesive layer, the preparation method further includes: An optical groove is formed by carving a groove in the fixing adhesive layer; The central region of the sensing chip covers the optical groove, and a sensing device is disposed in the central region of the sensing chip, the sensing device corresponding to the optical groove.

9. The method for fabricating a chip packaging structure according to claim 7, characterized in that, Before the step of forming a first dielectric layer on the surface of the sensing chip away from the carrier cover, the fabrication method further includes: The edge region of the sensing chip is thinned to form a buffer groove, so that the central region of the sensing chip protrudes to form a boss.

10. The method for fabricating a chip packaging structure according to claim 9, characterized in that, Before the step of forming a first dielectric layer on the surface of the sensing chip away from the carrier cover, the fabrication method further includes: A third dielectric layer is formed on the surface of the sensing chip on the side away from the carrier cover. A buffer opening is formed by slotting in the third dielectric layer, and the buffer opening is located in the edge region of the sensing chip. The sensing chip and the fixing adhesive layer are cut using the buffer opening as the cutting path, and a cutting groove is formed; A second buffer layer is formed by filling the cut groove with a buffer material.

11. The method for fabricating a chip packaging structure according to claim 10, characterized in that, After the step of forming solder balls by planting them on the side of the second dielectric layer away from the carrier cover, the preparation method further includes: The sensor chip is cut using the second buffer layer as the cutting path.

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