High electron mobility transistor

Abstract

A high electron mobility transistor (HEMT) includes a first doped layer disposed in a substrate, a mesa isolation disposed on the substrate, a gate electrode disposed on the mesa isolation, a source electrode and a drain electrode disposed on both sides of the gate electrode, a protection layer disposed on the mesa isolation and surrounding the source electrode and the drain electrode, a first metal wire connecting the source electrode and the first doped layer, and a second metal wire connecting the drain electrode and the first doped layer.

Description

Technical Field

[0001] This invention relates to a high electron mobility transistor with a doped layer. Background Technology

[0002] High electron mobility transistors based on gallium nitride (GaN) materials possess numerous advantages in electronic, mechanical, and chemical properties, such as wide bandgap, high breakdown voltage, high electron mobility, high elastic modulus, high piezoelectricity and piezoresistive coefficients, and chemical passivation. These advantages enable GaN-based materials to be used in the fabrication of components for applications such as high-brightness light-emitting diodes, power switching devices, regulators, battery protectors, panel display drivers, and communication components. Summary of the Invention

[0003] One embodiment of the present invention discloses a high electron mobility transistor (HEMT), which mainly includes a first doped layer disposed in a substrate, a mesa isolation disposed on the substrate, a gate electrode disposed on the mesa isolation, a source electrode and a drain electrode disposed on both sides of the gate electrode, a protective layer disposed on the mesa isolation and surrounding the source electrode and the drain electrode, a first metal wire connecting the source electrode and the first doped layer, and a second metal wire connecting the drain electrode and the first doped layer.

[0004] Another embodiment of the present invention discloses a high electron mobility transistor, which mainly includes a first doped layer disposed on the top surface of a substrate, a plateau isolation disposed on the substrate, a gate electrode disposed on the plateau isolation, a source electrode and a drain electrode disposed on both sides of the gate electrode, a protective layer disposed on the plateau isolation and surrounding the source electrode and the drain electrode, a first metal wire connecting the source electrode and the first doped layer, and a second metal wire connecting the drain electrode and the first doped layer. Attached Figure Description

[0005] Figures 1 to 2 This is a schematic diagram of a method for fabricating a high electron mobility transistor according to an embodiment of the present invention;

[0006] Figure 3 This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0007] Figure 4 This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0008] Figure 5This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0009] Figure 6 This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0010] Figure 7 This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0011] Figure 8 This is a schematic diagram of the structure of a high electron mobility transistor according to an embodiment of the present invention;

[0012] Figure 9 This is a schematic diagram of a high electron mobility transistor according to an embodiment of the present invention.

[0013] Explanation of main component symbols

[0014] 12: Base

[0015] 14: Doped layer

[0016] 16: Buffer layer

[0017] 18: Barrier Layer

[0018] 20: P-type semiconductor layer

[0019] 22: Platform Isolation

[0020] 24: Protective layer

[0021] 26: Source electrode

[0022] 28: Drain electrode

[0023] 30: Source electrode extension

[0024] 32: Drain electrode extension

[0025] 34: Doped layer

[0026] 38: Gate electrode

[0027] 42: Doped layer

[0028] 44: Metal silicides

[0029] 46: Metal silicides Detailed Implementation

[0030] Please refer to Figures 1 to 2 , Figures 1 to 2 This is a schematic diagram illustrating a method for fabricating a high electron mobility transistor according to an embodiment of the present invention. Figure 1As shown, a substrate 12 is first provided, for example, a substrate made of silicon, silicon carbide, or aluminum oxide (or sapphire), wherein the substrate 12 may be a single-layer substrate, a multilayer substrate, a gradient substrate, or a combination thereof. According to other embodiments of the present invention, the substrate 12 may further comprise a silicon-on-insulator (SOI) substrate.

[0031] An ion implantation process can then be performed to form a doped layer 14 or a doped region within the substrate 12. In this embodiment, the doped layer 14 may comprise a doped region composed of N-type dopant or a doped region composed of P-type dopant, and the doped layer 14 is preferably completely embedded within the substrate 12 and not exposed on the surface of the substrate 12. In other words, the top surface of the doped layer 14 is preferably lower than the top surface of the substrate 12.

[0032] A selective nucleation layer (not shown) and a buffer layer 16 are then formed on the surface of the substrate 12. In one embodiment, the nucleation layer preferably comprises aluminum nitride and the buffer layer 16 comprises a III-V semiconductor such as gallium nitride, and its thickness may be between 0.5 micrometers and 10 micrometers. In one embodiment, the buffer layer 16 may be formed on the substrate 12 using molecular-beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof.

[0033] Next, an unintentionally doped buffer layer (not shown) may be selectively formed on the surface of buffer layer 16. In this embodiment, the unintentionally doped buffer layer preferably comprises a III-V semiconductor, such as gallium nitride or more specifically, unintentionally doped gallium nitride. In one embodiment, the unintentionally doped buffer layer may be formed on buffer layer 16 using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), or a combination thereof.

[0034] Subsequently, a barrier layer 18 is formed on the surface of the unintentionally doped buffer layer or buffer layer 16. In this embodiment, the barrier layer 18 preferably comprises a III-V semiconductor such as N-type aluminum gallium nitride (Al x Ga 1-x N), where 0 < x < 1. The barrier layer 18 preferably comprises an epitaxial layer formed by an epitaxial growth process, and the barrier layer 18 may comprise dopants of silicon or germanium. Similar to the method of forming the buffer layer 16 as described above, a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof may be used to form the barrier layer 18 on the buffer layer 16.

[0035] Next, a P-type semiconductor layer 20 is formed on the barrier layer 18. In one embodiment, the P-type semiconductor layer 20 preferably comprises p-type gallium nitride (pGaN), and a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, a chemical vapor deposition (CVD) process, a hydride vapor phase epitaxy (HVPE) process, or a combination thereof may be used to form the P-type semiconductor layer 20 on the surface of the barrier layer 18.

[0036] Subsequently, a mesa isolation process is performed to form mesa isolations 22, enabling the components to operate independently without being affected by each other. In this embodiment, the mesa isolation process may use a lithography and etching process to pattern or etch away part of the P-type semiconductor layer 20, part of the barrier layer 18, part of the buffer layer 16, part of the substrate 12, and even part of the doped layer 14, exposing the top surface of the doped layer 14. The edges between the patterned P-type semiconductor layer 20, barrier layer 18, and buffer layer 16 preferably align with each other. Additionally, each mesa isolation 22 in this embodiment preferably comprises part of the substrate 12, the patterned buffer layer 16, the patterned barrier layer 18, and the patterned P-type semiconductor layer 20. The thickness of the patterned buffer layer 16 is about 300 nm, the thickness of the patterned barrier layer 18 is about 10 nm, and the thickness of the patterned P-type semiconductor layer 20 is about 100 nm.

[0037] Next, as shown in Figure 2, a photolithography and etching process is performed to remove a portion of the P-type semiconductor layer 20. The patterned P-type semiconductor layer 20 preferably serves as part of the gate structure for subsequent HEMT devices. Then, a protective layer 24 is conformally formed on the buffer layer 18, covering the top surface and sidewalls of the platform isolation 22. In this embodiment, the protective layer 24 preferably comprises, but is not limited to, silicon nitride, and its thickness is approximately 100-200 nanometers, but not limited to this.

[0038] Subsequently, one or more photolithography and etching processes are performed to remove part of the protective layer 24 and part of the barrier layer 18 to form multiple grooves (not shown). Then, conductive material is formed in the grooves and on the protective layer 24. Then, one or more pattern transfer processes are performed to remove part of the conductive material to form patterned metal wires as source electrode 26 and drain electrode 28. The conductive material disposed on the source electrode 26 and extending to the surface of the adjacent protective layer 24 is preferably used as source electrode extension 30, and the conductive material disposed above the drain electrode 28 and extending to the surface of the adjacent protective layer 24 is used as drain electrode extension 32.

[0039] It is worth noting that the source electrode 26 and drain electrode 28 formed in this stage can be conductive contacts of the same or different properties, thereby enabling the entire HEMT device to achieve the function of a diode. For example, according to an embodiment of the present invention, an ohmic contact can be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 14 below it, and an ohmic contact can also be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14. The source electrode 26 end can be formed by the complete reaction of metal and doped layer 14 to form metal silicide 44 to form an ohmic contact, while the drain electrode 28 end can be formed by first using an ion implantation process to implant ions of the opposite conductivity type to those in the doped layer 14 to form another doped layer 34, thereby forming an ohmic contact at the drain electrode 28 end. For example, the doped layer 14 can contain N-type dopants and the doped layer 34 can contain P-type dopants. In other words, compared to the source electrode 26 end forming an ohmic contact through the metal silicide 44 that is completely reacted between the doped layer 14 and the metal wire, the drain electrode 28 end forms an ohmic contact through the PN junction between the doped layer 14 and the doped layer 34.

[0040] In addition, such as Figure 3As shown, in addition to the aforementioned source electrode 26 and drain electrode 28 being ohmic contacts, according to another embodiment of the present invention, an ohmic contact can be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 14 below, while a Schottky contact can be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14. For example, the source electrode 26 end can form an ohmic contact by completely reacting the source electrode extension 30 and the doped layer 14 to form a metal silicide 44, while the drain electrode 28 end can similarly form a metal silicide 46 by reacting the drain electrode extension 32 and the doped layer 14. However, during the reaction process, the thickness of the metal deposition and / or the time and temperature of the heat treatment process are specially controlled so that the interface between the drain electrode extension 32 and the doped layer 14 does not completely react to form the metal silicide 46. That is, in addition to the reacted metal silicide 46, there is still an unreacted metal layer (not shown in the figure), thereby forming a Schottky contact at the drain electrode 28 end.

[0041] Then another protective layer (not shown) or hard mask is formed on the protective layer 24, the source electrode extension 30 and the drain electrode extension 32. One or more photolithography and etching processes are performed to remove part of the protective layer to form a groove (not shown) and expose the P-type semiconductor layer 20. Another conductive material is formed on the protective layer to fill the groove. Then a pattern transfer process is performed to remove part of the conductive material to form the gate electrode 38.

[0042] In this embodiment, the gate electrode 38, source electrode 26, and drain electrode 28 are preferably made of metal. The gate electrode 38 and source electrode 26 may contain the same or different materials, as may the gate electrode 38 and drain electrode 28, and the source electrode 26 and drain electrode 28 may contain the same or different materials. According to one embodiment of the present invention, the gate electrode 38, source electrode 26, and drain electrode 28 may each contain gold, silver, platinum, titanium, aluminum, tungsten, palladium, or a combination thereof. In some embodiments, conductive materials can be formed in the groove using electroplating, sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), or combinations thereof, and then the electrode materials can be patterned using one or more etching processes to form the gate electrode 38, source electrode 26, and drain electrode 28.

[0043] Please continue to refer to Figures 4 to 5 , Figures 4 to 5 A schematic diagram of a high electron mobility transistor according to an embodiment of the present invention is shown. Figures 4 to 5As shown, compared to Figure 2 or Figure 3 The doped layer 14 is completely embedded within the substrate 12 and not exposed outside the substrate 12. Alternatively, the present invention can place the doped layer 14 above the top surface of the substrate 12, so that the top surface of the doped layer 14 directly contacts the bottom surface of the buffer layer 16. As described above. Figure 2 Example, Figure 4 The source electrode 26 and the drain electrode 28 may contain conductive contacts of the same nature. For example, the source electrode 26 or the source electrode extension 30 and the doped layer 14 below may form an ohmic contact using a fully reacted metal silicide 44. Meanwhile, the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 may form an ohmic contact using a PN junction between the doped layer 14 and the doped layer 34.

[0044] In addition, as Figure 3 Example, Figure 5 The source electrode 26 and drain electrode 28 may contain conductive contacts of different properties. For example, an ohmic contact may be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 14 below using a fully reacted metal silicide 44, while a Schottky contact may be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 using an incompletely reacted metal silicide 46. These variations are all within the scope of this invention.

[0045] Please continue to refer to Figures 6 to 7 , Figures 6 to 7 A schematic diagram of a high electron mobility transistor according to an embodiment of the present invention is shown. Figures 6 to 7 As shown, compared to Figure 2 In this embodiment, only one doped layer 14 is formed within the substrate 12. Alternatively, another doped layer 42 with a different conductivity type can be formed directly below the doped layer 14. For example, the doped layer 14 may contain a doped region composed of N-type dopants, while the doped layer 42 may contain a doped region composed of P-type dopants. Furthermore, compared to the aforementioned source electrode 26, where the metal directly contacts the upper doped layer 14, in this embodiment, it is preferable that in the subsequent packaging process, the wires at the source electrode 26, such as the source electrode extension 30, are connected to and contact the bottom surface of the doped layer 42 on the back side of the substrate 12, while the wires at the drain electrode 28, such as the drain electrode extension 32, remain connected to and contact the top surface of the doped layer 14 on the front side of the substrate 12.

[0046] As mentioned above Figure 2 Example, Figure 6The source electrode 26 and the drain electrode 28 may contain conductive contacts of the same nature. For example, the source electrode 26 or the source electrode extension 30 and the doped layer 42 may form an ohmic contact using a fully reacted metal silicide 44. Meanwhile, the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 may form an ohmic contact using a PN junction between the doped layer 14 and the doped layer 34.

[0047] In addition, as Figure 3 Example, Figure 7 The source electrode 26 and the drain electrode 28 may contain conductive contacts of different properties. For example, an ohmic contact may be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 42 using a fully reacted metal silicide 44, while a Schottky contact may be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 using an incompletely reacted metal silicide 46. These variations are all within the scope of this invention.

[0048] Please refer to Figures 8 to 9 , Figures 8 to 9 A schematic diagram of a high electron mobility transistor according to an embodiment of the present invention is shown. Figures 8 to 9 As shown, the present invention can be combined with Figure 4 and Figure 6 In this embodiment, a doped layer 14 is disposed above the top surface of the substrate 12, and two doped layers with different conductivity types, such as doped layer 14 and doped layer 42, are formed within the substrate 12. Preferably, in the subsequent packaging process, the wire at the source electrode 26 end, such as the source electrode extension 30, is connected to and contacts the bottom surface of the doped layer 42 on the back side of the substrate 12, while the wire at the drain electrode 28 end, such as the drain electrode extension 32, is connected to and contacts the top surface of the doped layer 14 on the front side of the substrate 12.

[0049] As mentioned above Figure 2 Example, Figure 8 The source electrode 26 and the drain electrode 28 may contain conductive contacts of the same nature. For example, the source electrode 26 or the source electrode extension 30 and the doped layer 42 may form an ohmic contact using a fully reacted metal silicide 44. Meanwhile, the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 may form an ohmic contact using a PN junction between the doped layer 14 and the doped layer 34.

[0050] In addition, as Figure 3 Example, Figure 9The source electrode 26 and the drain electrode 28 may contain conductive contacts of different properties. For example, an ohmic contact may be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 42 using a fully reacted metal silicide 44, while a Schottky contact may be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 using an incompletely reacted metal silicide 46. These variations are all within the scope of this invention.

[0051] In summary, this invention discloses a method and structure for realizing a diode using a high electron mobility transistor. It mainly involves forming one or more doped layers within or on a substrate, and then forming conductive contacts of the same or different properties at the source and drain terminals. According to one embodiment of this invention, if the source and drain terminals are conductive contacts of the same property, an ohmic contact can be formed between the source electrode 26 or the source electrode extension 30 and the contacting doped layer 42 using a fully reacted metal silicide. Simultaneously, an ohmic contact can be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 using the PN junction between the doped layer 14 and the doped layer 34.

[0052] Alternatively, if the source electrode and drain electrode are conductive contacts of different properties, an ohmic contact can be formed between the source electrode 26 or the source electrode extension 30 and the doped layer 42 using a fully reacted metal silicide, while a Schottky contact can be formed between the drain electrode 28 or the drain electrode extension 32 and the doped layer 14 using an incompletely reacted metal silicide. These variations are all within the scope of this invention.

[0053] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor (HEMT), characterized in that, Include: The first doped layer is disposed within the substrate; Mesa isolation, built upon this foundation, includes: A buffer layer is disposed on the substrate; and A barrier layer is disposed on the buffer layer and in direct contact with the buffer layer, wherein the top surface of the first doped layer is flush with the bottom surface isolated by the platform; The gate electrode is located on the platform isolation; as well as The source electrode and the drain electrode are located on both sides of the gate electrode.

2. The high electron mobility transistor of claim 1, further comprising: A protective layer is disposed on the platform isolation and surrounds the source electrode and the drain electrode; A first metal wire connects the source electrode and the first doped layer; as well as The second metal wire connects the drain electrode and the first doped layer.

3. The high electron mobility transistor of claim 2, wherein the protective layer is disposed on the platform isolation sidewall.

4. The high electron mobility transistor of claim 1, further comprising: A first ohmic contact is disposed on the first doped layer and adjacent to the source electrode; and The second ohmic contact is disposed on the first doped layer and next to the drain electrode.

5. The high electron mobility transistor of claim 4, wherein the first doped layer comprises a first doped region and the second ohmic contact comprises a second doped region.

6. The high electron mobility transistor of claim 5, wherein the first doped region and the second doped region comprise different conductivity types.

7. The high electron mobility transistor of claim 1, further comprising: An ohmic contact is disposed on the first doped layer and adjacent to the source electrode; and A Schottky contact is disposed on the first doped layer and next to the drain electrode.

8. The high electron mobility transistor of claim 1, further comprising: A second doped layer is disposed within the substrate and below the first doped layer; A first metal wire connects the source electrode and the second doped layer; and The second metal wire connects the drain electrode and the first doped layer.

9. The high electron mobility transistor of claim 8, wherein the first doped layer and the second doped layer comprise different conductivity types.

10. A high electron mobility transistor (HEMT), characterized in that, Include: The first doped layer is disposed on the substrate surface; Mesa isolation, built upon this foundation, includes: A buffer layer is disposed on the substrate; and A barrier layer is disposed on the buffer layer and in direct contact with the buffer layer, wherein the top surface of the first doped layer is flush with the bottom surface isolated by the platform; The gate electrode is located on the platform isolation; as well as The source electrode and the drain electrode are located on both sides of the gate electrode.

11. The high electron mobility transistor of claim 10, further comprising: A protective layer is disposed on the platform isolation and surrounds the source electrode and the drain electrode; A first metal wire connects the source electrode and the first doped layer; and The second metal wire connects the drain electrode and the first doped layer.

12. The high electron mobility transistor of claim 11, wherein the protective layer is disposed on the platform isolation sidewall.

13. The high electron mobility transistor of claim 10, further comprising: A first ohmic contact is disposed on the first doped layer and adjacent to the source electrode; and The second ohmic contact is disposed on the first doped layer and next to the drain electrode.

14. The high electron mobility transistor of claim 13, wherein the first doped layer comprises a first doped region and the second ohmic contact comprises a second doped region.

15. The high electron mobility transistor of claim 14, wherein the first doped region and the second doped region comprise different conductivity types.

16. The high electron mobility transistor of claim 10, further comprising: An ohmic contact is disposed on the first doped layer and adjacent to the source electrode; and A Schottky contact is disposed on the first doped layer and next to the drain electrode.

17. The high electron mobility transistor of claim 10, further comprising: A second doped layer is disposed within the substrate and below the first doped layer; A first metal wire connects the source electrode and the second doped layer; and The second metal wire connects the drain electrode and the first doped layer.

18. The high electron mobility transistor of claim 17, wherein the first doped layer and the second doped layer comprise different conductivity types.

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