A GaN reference vertical junction barrier schottky diode and a method of fabricating the same

Abstract

This invention discloses a GaN-based vertical junction barrier Schottky diode and its fabrication method. The diode comprises: a substrate layer, a buffer layer, and an N-type N-type junction. + Transport layer, N ‑ Drift layer, cathode, anode groove, P + The process includes a secondary epitaxial layer, a dielectric layer, and an anode. The Schottky metal anode prepared in this invention is deeply embedded in the anode groove and subjected to P... + Surrounded by a secondary epitaxial layer, the vertically shaped anode Schottky metal effectively disperses the electric field when the device is reverse biased, improving the diode's reverse breakdown voltage and reducing reverse leakage current; N ‑ The slope of the drift layer can effectively disperse the electric field near the anode when the device is reverse biased, thus enhancing the reverse breakdown voltage capability of the diode; P + The secondary epitaxial layer and the dielectric layer form a PiN structure, which has the advantages of low turn-on voltage, low reverse leakage current, high withstand voltage and high switching speed. At the same time, the dielectric layer can reduce the leakage path and further reduce the reverse leakage current of the device.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology and process, specifically relating to a GaN reference vertical junction barrier Schottky diode and its fabrication method. Background Technology

[0002] In recent years, third-generation semiconductor materials, such as gallium nitride (GaN) and SiC, have attracted widespread attention. Compared to traditional semiconductor materials, GaN exhibits high breakdown field strength, high electron mobility, and high saturation velocity, as well as high reliability under high temperatures and irradiation, demonstrating enormous potential in power electronics and radio frequency microwave electronic devices. However, in conventional lateral structure electronic devices, current collapse and self-heating effects severely restrict device development. Against this backdrop, vertical structure GaN power electronic devices have emerged as a new direction for overcoming these obstacles, offering advantages such as high power density, high reliability, and uniform heat distribution. Furthermore, GaN-based vertical structure electronic devices based on heterojunction substrates offer both performance and price advantages due to their low substrate cost, making them easier to commercialize.

[0003] In high-voltage, high-current circuit applications, silicon-based PiN diodes exhibit good reverse breakdown voltage and very low forward voltage drop at high current densities, demonstrating low resistance. However, PiN diodes are minority carrier devices, and due to their long lifespan, their reverse recovery speed is limited, resulting in a corresponding decrease in the switching speed of power diodes. In particular, their poor reverse recovery characteristics increasingly fail to meet the development requirements of power switching devices. Therefore, in high-frequency power electronic circuits, not only are good forward recovery characteristics required for power diodes (i.e., low forward transient voltage drop and short recovery time), but also excellent reverse recovery characteristics (i.e., short reverse recovery time and low reverse recovery charge) are particularly important. Therefore, leveraging the material advantages and combining the PiN concept, researching high-frequency, high-voltage, fast GaN-based vertical junction barrier (JBS) power diodes has significant practical implications. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a GaN-based vertical junction barrier Schottky diode and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A GaN-based vertical junction barrier Schottky diode includes: a substrate layer, a buffer layer, and an N-type N-type junction. + Transport layer, N - Drift layer, cathode, anode groove, P + Secondary epitaxial layer, dielectric layer, and anode; wherein,

[0006] The substrate layer, the buffer layer, and the N + The transport layers are configured sequentially from bottom to top;

[0007] The N - The drift layer is disposed on the N + On the transport layer, the shape is a frustum; the N - The center of the bottom surface of the drift layer is set at the N. + The center position of the upper surface of the transport layer, the N - The diameter of the bottom surface of the drift layer is larger than the diameter of the top surface, and the N - The slope of the drift layer and the N + The included angle of the upper surface of the transmission layer is within a preset angle range;

[0008] The cathode is ring-shaped and is disposed at the N + Around the outer edge of the upper surface of the transport layer; the cathode and the N - Drift layer interval settings;

[0009] The anode groove is disposed at the N - On the upper surface of the drift layer, the depth of the anode groove does not exceed N. - The bottom surface of the drift layer;

[0010] The P + A secondary epitaxial layer is disposed on the inner sidewall of the anode groove;

[0011] The dielectric layer is disposed on the upper surface of the bottom of the anode groove; the N - The drift layer, the dielectric layer, and the P + The secondary epitaxial layer forms a PiN structure;

[0012] The anode is disposed inside the anode groove and the N - The upper surface of the drift layer.

[0013] In one embodiment of the present invention, the substrate material includes sapphire, silicon (Si), or silicon carbide (SiC).

[0014] In one embodiment of the present invention, N + The transport layer material includes: N-type GaN; the N... + The thickness of the transport layer is 1μm to 4μm; the N + The doping concentration of the transport layer is 8 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 .

[0015] In one embodiment of the present invention, N - The drift layer material includes: N-type GaN; the N... - The thickness of the drift layer is 3μm to 9μm; the N -The doping concentration of the drift layer is: 1×10 16 cm -3 ~4×10 16 cm -3 .

[0016] In one embodiment of the present invention, the preset angle range is 5° to 30°.

[0017] In one embodiment of the present invention, the depth of the anode groove is 300nm to 500nm.

[0018] In one embodiment of the present invention, P + The thickness of the secondary epitaxial layer is 300nm to 400nm.

[0019] In one embodiment of the present invention, the thickness of the dielectric layer is 300 nm to 400 nm.

[0020] A method for fabricating a GaN-based vertical junction barrier Schottky diode includes:

[0021] S1: Select sapphire, silicon (Si) or silicon carbide (SiC) as the substrate layer;

[0022] S2: On the substrate layer, a buffer layer and an N layer are grown sequentially. + Transport layer and N - Drift layer;

[0023] S3: For the N - The drift layer is subjected to photolithography and etching to form a frustum shape; after etching, the N... - The slope of the drift layer and the N + The included angle of the upper surface of the transmission layer is within a preset angle range; the preset angle range is 5° to 30°.

[0024] S4: In the N + A cathode is formed on the outer edge of the upper surface of the transmission layer; the cathode is annular in shape; the cathode is disposed on the N + Around the outer edge of the upper surface of the transport layer; the cathode and the N - Drift layer interval settings;

[0025] S5: In the N - The upper surface of the drift layer is etched to form an anode groove;

[0026] S6: Make P on the inner sidewall of the anode groove + Secondary epitaxial layer;

[0027] S7: A dielectric layer is formed on the upper surface of the bottom of the anode groove;

[0028] S8: Inside the anode groove and the N - An anode is fabricated on the upper surface of the drift layer.

[0029] In one embodiment of the present invention, S6: P is formed on the inner sidewall of the anode groove. + The secondary epitaxial layer includes:

[0030] P is grown on the upper surface of the current device using MOCVD process. + The secondary epitaxial layer was created by using ICP etching technology to etch the bottom of the anode groove and complete the growth of P. + The upper surface of the secondary epitaxial layer is etched to obtain the P layer disposed on the inner sidewall of the anode groove. + Secondary epitaxial layer.

[0031] The beneficial effects of this invention are:

[0032] The anode Schottky metal prepared in this invention penetrates deep into the anode groove and is subjected to P + Surrounded by a secondary epitaxial layer, the vertically shaped anode Schottky metal effectively disperses the electric field when the device is reverse biased, improving the diode's reverse breakdown voltage and reducing reverse leakage current; N - The slope of the drift layer can effectively disperse the electric field near the anode when the device is reverse biased, enhancing the reverse breakdown voltage capability of the diode; P + The secondary epitaxial layer and the dielectric layer form a PiN structure, which has the advantages of low turn-on voltage, low reverse leakage current, high withstand voltage and high switching speed. At the same time, the dielectric layer can reduce the leakage path and further reduce the reverse leakage current of the device. Attached Figure Description

[0033] Figure 1 This is a schematic cross-sectional view of a GaN reference vertical junction barrier Schottky diode fabricated according to an embodiment of the present invention.

[0034] Figure 2 This is a schematic flowchart illustrating a method for fabricating a GaN-based vertical junction barrier Schottky diode according to an embodiment of the present invention.

[0035] Figures 3a to 3i This is a schematic diagram of the process flow for fabricating a GaN-based vertical junction barrier Schottky diode according to an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1

[0038] This invention provides a GaN-based vertical junction barrier Schottky diode, the cross-sectional view of which is shown below. Figure 1 As shown, it includes:

[0039] Substrate layer 1, buffer layer 2, N + Transport layer 3, N - 4. Drift layer; 5. Cathode; 6. Anode groove; 7. P + Secondary epitaxial layer 7, dielectric layer 8, and anode 9; wherein,

[0040] Substrate layer 1, buffer layer 2 and N + Transport layer 3 is set up sequentially from bottom to top.

[0041] N - Drift layer 4 is set at N + On transport layer 3, the shape is a frustum; N - The center of the circle on the bottom surface of drift layer 4 is set at N. + The center position of the upper surface of transport layer 3, N - The diameter of the bottom surface of drift layer 4 is larger than the diameter of the top surface, N - The slope of drift layer 4 and N + The included angle of the upper surface of transmission layer 3 is within a preset angle range;

[0042] The cathode 5 is ring-shaped and is located at N. + Around the outer edge of the upper surface of transport layer 3; cathode 5 and N - Drift layer 4 interval setting;

[0043] Anode groove 6 is set at N - On the upper surface of drift layer 4, the depth of anode groove 6 does not exceed N. - The bottom surface of drift layer 4;

[0044] P + The secondary epitaxial layer 7 is disposed on the inner sidewall of the anode groove 6;

[0045] The dielectric layer 8 is disposed on the upper surface of the bottom of the anode groove 6; N - Drift layer 4, dielectric layer 8 and P + The secondary epitaxial layer 7 forms a PiN structure;

[0046] Anode 9 is disposed inside anode groove 6 and N - The upper surface of drift layer 4.

[0047] In this embodiment, a buffer layer 2 and an N are disposed on the substrate 1. + Transport layer 3 and N -Drift layer 4 creates a quasi-vertical structure between the anode and cathode. In this embodiment, the anode Schottky metal is deeply embedded in the anode groove and is subjected to P... + Surrounded by a secondary epitaxial layer, the vertically shaped anode Schottky metal effectively disperses the electric field when the device is reverse biased, improving the diode's reverse breakdown voltage and reducing reverse leakage current; N - The slope of the drift layer can effectively disperse the electric field near the anode when the device is reverse biased, enhancing the reverse breakdown voltage capability of the diode; P + The secondary epitaxial layer and the dielectric layer form a PiN structure, which has the advantages of low turn-on voltage, low reverse leakage current, high withstand voltage and high switching speed. At the same time, the dielectric layer can reduce the leakage path and further reduce the reverse leakage current of the device.

[0048] Preferably, the material of the substrate layer 1 includes:

[0049] Sapphire, silicon (Si), or silicon carbide (SiC).

[0050] Preferably, the material of the buffer layer 2 includes type I GaN; the thickness of the buffer layer 2 is 1μm to 3μm; and the buffer layer 2 is not intentionally doped.

[0051] Preferably, N + The materials for transport layer 3 include: N-type GaN; N + The thickness of transport layer 3 is 1 μm to 4 μm; N + The doping concentration of transport layer 3 is 8 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 .

[0052] Preferably, N - The materials of drift layer 4 include: N-type GaN; N - The thickness of drift layer 4 is 3 μm to 9 μm; N - The doping concentration of drift layer 4 is 1×10⁻⁶. 16 cm -3 ~4×10 16 cm -3 .

[0053] Preferably, the preset angle range is 5° to 30°.

[0054] N - The preset angle range of the slope of the drift layer 4 is 5° to 30°, which can effectively disperse the electric field near the anode when the device is reverse biased, and enhance the reverse voltage withstand capability of the diode.

[0055] Preferably, the depth of the anode groove 6 is 300nm to 500nm. The anode groove 6 can reduce the device turn-on voltage, form multiple anode edges, and reduce the electric field edge concentration effect.

[0056] Preferably, P + The thickness of the secondary epitaxial layer 7 is 300nm to 400nm.

[0057] Preferably, the thickness of the dielectric layer 8 is 300 nm to 400 nm. The material of the dielectric layer 8 includes Si3N4.

[0058] The cathode 5 is made of materials including Ti / Al / Ni / Au.

[0059] The materials for anode 9 include: Ni / Au.

[0060] In this embodiment, the anode is in contact with the insulating dielectric layer and the P+ secondary epitaxial layer. The P+ secondary epitaxial layer 7, the dielectric layer 8, and the N... - The drift layer 4 forms a PIN structure among the three elements, which helps maintain a low reverse leakage current in the device. The limiting breakdown field strength of general quasi-vertical diode technology is around 1MV / cm, while the embodiment of this invention uses a sloping platform, P-type secondary epitaxy, and grooved anode technology to bring the device breakdown field strength close to the material limit, about 3MV / cm.

[0061] Example 2

[0062] This invention provides a method for fabricating a GaN-based vertical junction barrier Schottky diode, such as... Figure 2 As shown, it includes:

[0063] S1: Sapphire, silicon Si, or silicon carbide SiC are selected as substrate layer 1;

[0064] S2: On substrate 1, buffer layer 2 and N are grown sequentially. + Transport layer 3 and N - Drift layer 4;

[0065] S3: For N - Drift layer 4 is photolithographically and etched to form a frustum shape; after etching, N - The slope of drift layer 4 and N + The included angle of the upper surface of transmission layer 3 is within a preset angle range;

[0066] S4: In N + A cathode 5 is formed on the outer edge of the upper surface of the transmission layer 3; the cathode 5 is annular in shape; the cathode 5 is disposed on N. + Around the outer edge of the upper surface of transport layer 3; cathode 5 and N - Drift layer 4 interval setting;

[0067] S5: In N - The upper surface of the drift layer 4 is etched to form an anode groove 6;

[0068] S6: P is made on the inner wall of the anode groove 6. + Secondary epitaxial layer 7;

[0069] S7: Form a dielectric layer 8 on the upper surface of the bottom of the anode groove 6;

[0070] S8: Inside the anode groove 6 and N - An anode 9 is fabricated on the upper surface of the drift layer 4.

[0071] For S1, such as Figure 3a As shown, sapphire material is selected as substrate layer 1, and its thickness is selected to be 150μm~200μm.

[0072] For S2, such as Figure 3b As shown, a buffer layer 2 is grown on substrate layer 1, and N is sequentially grown on buffer layer 2 using MOCVD process. + Transport layer 3 and N - Drift layer 4.

[0073] Preferably, N + The materials for transport layer 3 include: N-type GaN; N + The thickness of transport layer 3 is 1 μm to 4 μm; N + The doping concentration of transport layer 3 is 8 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 .

[0074] Preferably, N - The materials of drift layer 4 include: N-type GaN; N - The thickness of drift layer 4 is 3 μm to 9 μm; N - The doping concentration of drift layer 4 is 1×10⁻⁶. 16 cm -3 ~4×10 16 cm -3 .

[0075] For S3, the preset angle range is 5° to 30°, which can be broken down into the following steps:

[0076] 3.1) First, a spin coater is used to spin the photoresist at a speed of 3000 rpm to form an elliptical cap shape. The photoresist used is AZ6130. Then, an NSR1755I7A lithography machine is used for exposure to form a mask pattern of a frustum area.

[0077] 3.2) The masked substrate was etched using an ICP98c inductively coupled plasma (ICP) etching machine with Cl2 plasma at an etching rate of 1 nm / s to create mesa etching. A photoresist reflow technique was then used to achieve an etching depth of 9 μm and a preset angle of 30°. (See [link to relevant documentation]). Figure 3c As shown.

[0078] For S4, the specific steps can be divided into the following steps:

[0079] 4.1) The photoresist was spun at a speed of 5000 rpm using a spin coater to obtain a photoresist mask thickness of 0.8 μm.

[0080] 4.2) Bake in a high-temperature oven at 80℃ for 10 minutes, and expose using an NSR1755I7A lithography machine to form a cathode region mask pattern.

[0081] 4.3) The cathode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The ohmic metals were Ti / Al / Ni / Au in sequence, with Ti thickness of 20 nm, Al thickness of 160 nm, Ni thickness of 55 nm, and Au thickness of 45 nm. After the ohmic contact metal of the cathode was evaporated, the metal was stripped to obtain a complete cathode. The resulting cathode 5 was annular in shape. Cathode 5 was placed on an N-type... + Around the outer edge of the upper surface of transport layer 3; cathode 5 and N - Drift layer 4 interval setting.

[0082] 4.4) Using an RTP500 rapid thermal annealing furnace, rapid thermal annealing is performed at 870℃ in a N2 atmosphere for 30 seconds to alloy the ohmic contact metal, completing the cathode fabrication. See the final description. Figure 3d .

[0083] For S5, the specific steps can be divided into the following:

[0084] 5.1) At a rotational speed of 5000 rpm at N - The upper surface of the drift layer 4 is coated with positive resist to obtain a photoresist mask with a thickness of 0.8 μm. It is then baked in a high-temperature oven at 80℃ for 10 min. Finally, it is exposed using an NSR1755I7A lithography machine to obtain an anode groove photoresist mask and complete the development.

[0085] 5.2) Using an ICP98c inductively coupled plasma etching machine, 500 nm of N was removed by etching in Cl2 plasma at an etching rate of 0.5 nm / s. - Drift layer, forming anode groove 6, see Figure 3ePreferably, the depth of the anode groove 6 is 300nm to 500nm. The anode groove 6 can reduce the device turn-on voltage, form multiple anode edges, and reduce the electric field edge concentration effect.

[0086] For S6, P is fabricated on the inner wall of the anode groove 6. + Secondary epitaxial layer 7 includes:

[0087] P is grown on the upper surface of the current device using MOCVD process. + The secondary epitaxial layer was created using ICP etching technology on the bottom of the anode recess 6 and to complete the growth of P. + The upper surface of the secondary epitaxial layer is etched to obtain P located on the inner sidewall of the anode groove 6. + Secondary epitaxial layer 7.

[0088] It can be broken down into the following steps:

[0089] 6.1) A 350nm P+ secondary epitaxial layer was deposited using MOCVD deposition equipment. See [link to MOCVD process]. Figure 3f ;

[0090] 6.2) Spray positive resist onto the surface of the obtained P+ secondary epitaxial layer at a speed of 5000 rpm to obtain a photoresist mask with a thickness of 0.8 μm. Then bake it in a high-temperature oven at 80℃ for 10 min. Then expose the area outside the groove using an NSR1755I7A lithography machine to obtain the photoresist mask and complete the development.

[0091] 6.3) Using an ICP98c inductively coupled plasma etching machine, the 350nm P+ secondary epitaxial layer at the bottom of the anode recess and the device surface was etched in Cl2 plasma at an etching rate of 0.5nm / s to remove the P+ secondary epitaxial layer 7 on the sidewalls. (See [reference]) Figure 3g .

[0092] For S7, the specific steps can be divided into the following:

[0093] 7.1) A photoresist mask is obtained by spinning the photoresist at a speed of 5000 rpm using a spin coater; then it is baked in a high-temperature oven at 80℃ for 10 min, and then exposed using an NSR1755I7A lithography machine to form the mask pattern of the dielectric layer 8 in the anode groove 6.

[0094] 7.2) A dielectric layer 8 with a thickness of 300 nm was deposited in the anode groove 6 using a metal sputtering apparatus, see [reference]. Figure 3h The thickness of dielectric layer 8 is 300nm to 400nm. The material of dielectric layer 8 includes Si3N4.

[0095] For S8, the specific steps can be divided into the following:

[0096] 8.1) A photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm using a spin coater.

[0097] 8.2) Bake in a high-temperature oven at 80℃ for 10 minutes, and expose using an NSR1755I7A lithography machine to form a mask pattern for the anode region.

[0098] 8.3) An Ohmiker-50 electron beam evaporation stage was used at an evaporation rate of 0.1 nm / s inside the anode recess 6 and N - The upper surface of the drift layer 4 is used for evaporation of anolyte metal, which is Ni / Au, with Ni having a thickness of 45 nm and Au having a thickness of 200 nm. After evaporation, the metal is stripped to obtain the complete anode 9. (See [link to documentation]). Figure 3i .

[0099] The invention utilizes the proposed method for fabricating GaN-based vertical junction barrier Schottky diodes, where the anode Schottky metal of the fabricated device is deeply embedded in the anode groove and is protected by P. + Surrounded by a secondary epitaxial layer, the vertically shaped anode Schottky metal effectively disperses the electric field when the device is reverse biased, improving the diode's reverse breakdown voltage and reducing reverse leakage current; N - The slope of the drift layer can effectively disperse the electric field near the anode when the device is reverse biased, enhancing the reverse breakdown voltage capability of the diode; P + The secondary epitaxial layer and the dielectric layer form a PiN structure, which has the advantages of low turn-on voltage, low reverse leakage current, high withstand voltage and high switching speed. At the same time, the dielectric layer can reduce the leakage path and further reduce the reverse leakage current of the device.

[0100] It should be noted that, in the description of this invention, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0102] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0103] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0104] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A GaN-based vertical junction barrier Schottky diode, characterized by, include: Substrate (1), buffer layer (2), N + Transport layer (3), N - Drift layer (4), cathode (5), anode groove (6), P + The secondary epitaxial layer (7), the dielectric layer (8), and the anode (9) are included; among them, The substrate layer (1), the buffer layer (2) and the N + The transport layer (3) is sequentially arranged from bottom to top; The N - The drift layer (4) is disposed on the N + On the transmission layer (3), the shape is a frustum; the N - The center of the bottom surface of the drift layer (4) is set at the N + The center position of the upper surface of the transmission layer (3), the N - The diameter of the bottom surface of the drift layer (4) is larger than the diameter of the top surface, the N - The slope of the drift layer (4) and the N + The included angle of the upper surface of the transmission layer (3) is within a preset angle range; The cathode (5) is annular in shape and is disposed on the N + Around the outer edge of the upper surface of the transport layer (3); the cathode (5) and the N - The drift layer (4) is set at intervals; The anode groove (6) is disposed on the N - On the upper surface of the drift layer (4), the depth of the anode groove (6) does not exceed the depth of the N. - The bottom surface of the drift layer (4); The P + A secondary epitaxial layer (7) is provided on the inner side wall of the anode recess (6). The dielectric layer (8) is disposed on the upper surface of the bottom of the anode groove (6); the N - The drift layer (4), the dielectric layer (8), and the P + The secondary epitaxial layer (7) forms a PiN structure; The anode (9) is disposed inside the anode recess (6) and the N - upper surface of the drift layer (4).

2. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN-based drift layer. The material of the substrate layer (1) includes: Sapphire, silicon (Si), or silicon carbide (SiC).

3. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN-based drift layer. The N + The material of the transport layer (3) includes: N-type GaN; the N + The thickness of the transmission layer (3) is 1 μm to 4 μm; the N + The doping concentration of the transport layer (3) is 8 × 10⁻⁶. 18 cm -3 ~2×10 19 cm -3 .

4. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN buffer layer. The N - The material of the drift layer (4) includes: N-type GaN; the N - The thickness of the drift layer (4) is 3 μm to 9 μm; the N - The doping concentration of the drift layer (4) is: 1×10 16 cm -3 ~4×10 16 cm -3 .

5. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN buffer layer. The preset angle range is 5° to 30°.

6. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN buffer layer. The depth of the anode groove (6) is 300nm to 500nm.

7. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN buffer layer. The P + The thickness of the secondary epitaxial layer (7) is between 300 nm and 400 nm.

8. The GaN-based vertical junction barrier Schottky diode of claim 1, wherein the GaN-based vertical junction barrier Schottky diode is a GaN-based vertical junction barrier Schottky diode with a GaN buffer layer. The thickness of the dielectric layer (8) is 300nm to 400nm.

9. A method for fabricating a GaN-based vertical junction barrier Schottky diode, characterized in that, include: S1: Sapphire, silicon Si or silicon carbide SiC are selected as the substrate layer (1); S2: on the substrate layer (1), a buffer layer (2), an N + transport layer (3) and an N - drift layer (4) are sequentially grown S3: to the N - The drift layer (4) is subjected to photolithography and etching to form a circular truncated cone shape. After etching, the N - The slope of the drift layer (4) and the N + The inner angle of the upper surface of the transport layer (3) is within a preset angle range; the preset angle range is 5°-30°. S4: In the N + A cathode (5) is formed on the outer edge of the upper surface of the transmission layer (3); the cathode (5) is annular in shape; the cathode (5) is disposed on the N + Around the outer edge of the upper surface of the transport layer (3); the cathode (5) and the N - The drift layer (4) is set at intervals; S5: In the N - The upper surface of the drift layer (4) is etched to form an anode groove (6); S6: P is made on the inner side wall of the anode recess (6) + secondary epitaxial layer (7); S7: A dielectric layer (8) is formed on the upper surface of the bottom of the anode groove (6); S8: inside the anode recess (6) and the N - The upper surface of the drift layer (4) is provided with an anode (9).

10. The method of claim 9, wherein the GaN-based vertical junction barrier Schottky diode is prepared by the steps of: S6: P is made on the inner side wall of the anode recess (6) + a secondary epitaxial layer (7) comprising: ​ P is grown on the upper surface of the current device using MOCVD process. + The secondary epitaxial layer was formed by using ICP etching technology to grow P on the bottom of the anode groove (6). + The upper surface of the secondary epitaxial layer is etched to obtain the P layer disposed on the inner sidewall of the anode groove (6). + Secondary epitaxial layer (7).

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