Charge pump circuit, control method of charge pump circuit, and memory

Abstract

The embodiment of the present disclosure provides a charge pump circuit, comprising a first voltage boosting circuit and / or a second voltage boosting circuit, wherein: the first voltage boosting circuit is used for boosting a first node charged to an input voltage through a first voltage boosting capacitor under the control of a first clock signal, obtaining an output voltage, and applying the output voltage to a voltage output end; the second voltage boosting circuit is used for boosting a second node charged to the input voltage through a second voltage boosting capacitor under the control of a second clock signal, obtaining the output voltage, and applying the output voltage to the voltage output end; wherein the first voltage boosting capacitor and the second voltage boosting capacitor are MOS capacitors, and the gate dielectric layer material of the MOS capacitor comprises a high dielectric constant material, and the gate of the MOS capacitor comprises a metal gate. The ESR of the first voltage boosting capacitor and the second voltage boosting capacitor in the embodiment is small and the capacitance value is large, so that the current capacity of the charge pump circuit can be improved, and the current efficiency can be increased.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a charge pump circuit, a control method for the charge pump circuit, and a memory. Background Technology

[0002] A charge pump, also known as a switched-capacitor voltage converter, is a type of DC-DC converter that uses capacitors as energy storage elements. It is often used to generate an output voltage higher than the input voltage or a negative output voltage, and is widely used in integrated circuits and other fields. However, due to device limitations, the current capability and current efficiency of charge pumps are restricted. Summary of the Invention

[0003] This disclosure provides a charge pump circuit, a control method for the charge pump circuit, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a charge pump circuit, including a first boost circuit and / or a second boost circuit. The first boost circuit includes a first boost capacitor, and the second boost circuit includes a second boost capacitor. A first plate of the first boost capacitor is connected to a first node, and a first plate of the second boost capacitor is connected to a second node. The first node and the second node are respectively coupled to a voltage input terminal and a voltage output terminal. A second plate of the first boost capacitor receives a first clock signal, and a second plate of the second boost capacitor receives a second clock signal. Wherein:

[0005] The first boost circuit is used to boost the voltage of the first node charged to the input voltage through the first boost capacitor under the control of the first clock signal, to obtain the output voltage, and to apply the output voltage to the voltage output terminal.

[0006] The second boost circuit is used to boost the voltage of the second node charged to the input voltage through the second boost capacitor under the control of the second clock signal, to obtain the output voltage, and to apply the output voltage to the voltage output terminal;

[0007] Wherein, both the first boost capacitor and the second boost capacitor are MOS capacitors, and the gate dielectric layer material of the MOS capacitor includes a high dielectric constant material, and the gate of the MOS capacitor includes a metal gate.

[0008] In some embodiments, the first boost circuit and the second boost circuit are used to alternately boost the voltage of the first node and the second node to obtain the output voltage, and apply the output voltage to the voltage output terminal.

[0009] In some embodiments, the first boost circuit further includes a first switching circuit and a second switching circuit; the second boost circuit further includes a third switching circuit and a fourth switching circuit; wherein:

[0010] The first switching circuit is connected between the voltage input terminal and the first node, and is used to receive a third clock signal and control the first node to charge to the input voltage according to the third clock signal;

[0011] The second switching circuit is connected between the first node and the voltage output terminal, and is used to connect the first node, which has been boosted to the output voltage, to the voltage output terminal according to the voltage control of the second node;

[0012] The third switching circuit is connected between the voltage input terminal and the second node, and is used to receive the fourth clock signal and control the second node to charge to the input voltage according to the fourth clock signal;

[0013] The fourth switching circuit is connected between the second node and the voltage output terminal, and is used to connect the second node, which has been boosted to the output voltage, to the voltage output terminal according to the voltage control of the first node.

[0014] In some embodiments, the first switching circuit includes a first transistor and a first capacitor; the second switching circuit includes a second transistor; the third switching circuit includes a third transistor and a second capacitor; and the fourth switching circuit includes a fourth transistor; wherein:

[0015] The first terminal of the first transistor and the first terminal of the third transistor are both connected to the voltage input terminal; the second terminal of the first transistor, the first terminal of the second transistor, and the control terminal of the fourth transistor are all connected to the first node; the control terminal of the first transistor is connected to the first plate of the first capacitor, and the second plate of the first capacitor receives the third clock signal; the second terminal of the third transistor, the first terminal of the fourth transistor, and the control terminal of the second transistor are all connected to the second node; the control terminal of the third transistor is connected to the first plate of the second capacitor, and the second plate of the second capacitor receives the fourth clock signal; the second terminal of the second transistor and the second terminal of the fourth transistor are both connected to the voltage output terminal.

[0016] In some embodiments, the rising edge of the second clock signal precedes the rising edge of the third clock signal; the rising edge of the third clock signal precedes the falling edge of the first clock signal; the falling edge of the first clock signal precedes the falling edge of the fourth clock signal; the rising edge of the first clock signal precedes the rising edge of the fourth clock signal; the rising edge of the fourth clock signal precedes the falling edge of the second clock signal; and the falling edge of the second clock signal precedes the falling edge of the third clock signal.

[0017] In some embodiments, the charge pump circuit further includes a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit, wherein:

[0018] The first driving circuit is used to receive a first preset clock signal, perform driving enhancement processing on the first preset clock signal, and obtain the first clock signal.

[0019] The second driving circuit is used to receive a second preset clock signal, perform driving enhancement processing on the second preset clock signal, and obtain the second clock signal.

[0020] The third driving circuit is used to receive a third preset clock signal, perform driving enhancement processing on the third preset clock signal, and obtain the third clock signal.

[0021] The fourth driving circuit is used to receive a fourth preset clock signal, perform driving enhancement processing on the fourth preset clock signal, and obtain the fourth clock signal.

[0022] In some embodiments, the first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit all include an odd number of inverters; and in the first driving circuit and the second driving circuit, the gate dielectric layer material of the transistor in the inverter includes a high dielectric constant material, and the gate of the transistor in the inverter includes a metal gate.

[0023] In some embodiments, the falling edge of the second preset clock signal precedes the falling edge of the third preset clock signal; the falling edge of the third preset clock signal precedes the rising edge of the first preset clock signal; the rising edge of the first preset clock signal precedes the rising edge of the fourth preset clock signal; the falling edge of the first preset clock signal precedes the falling edge of the fourth preset clock signal; the falling edge of the fourth preset clock signal precedes the rising edge of the second preset clock signal; and the rising edge of the second preset clock signal precedes the rising edge of the third preset clock signal.

[0024] In some embodiments, the first preset clock signal, the second preset clock signal, the third preset clock signal, and the fourth preset clock signal all have the same duty cycle and the same clock period; the effective voltage of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is greater than the input voltage.

[0025] In some embodiments, the first boost capacitor and the second boost capacitor are both NMOS transistors or PMOS transistors; the first transistor and the third transistor are both NMOS transistors; the second transistor and the fourth transistor are both PMOS transistors; the first capacitor and the second capacitor are both cylindrical capacitors; the gate oxide layer of the first boost capacitor and the gate oxide layer of the second boost capacitor are thinner than the gate oxide layer of the first transistor, the gate oxide layer of the second transistor, the gate oxide layer of the third transistor, and the gate oxide layer of the fourth transistor.

[0026] In some embodiments, the charge pump circuit further includes a first protection circuit and a second protection circuit, wherein the first protection circuit includes a first protection transistor and a second protection transistor, and the second protection circuit includes a third protection transistor and a fourth protection transistor; wherein:

[0027] The control terminal of the first protection transistor is connected to the second node, and the first terminal of the first protection transistor and the control terminal of the second protection transistor are both connected to the first node; the second terminal of the first protection transistor, the first terminal of the second protection transistor, the substrate of the first protection transistor, and the substrate of the second protection transistor are all connected to the substrate of the second transistor; the second terminal of the second protection transistor is connected to the voltage output terminal.

[0028] The control terminal of the third protection transistor is connected to the first node, and the first terminal of the third protection transistor and the control terminal of the fourth protection transistor are both connected to the second node; the second terminal of the third protection transistor, the first terminal of the fourth protection transistor, the substrate of the third protection transistor, and the substrate of the fourth protection transistor are all connected to the substrate of the fourth transistor; the second terminal of the fourth protection transistor is connected to the voltage output terminal.

[0029] In some embodiments, the first protection transistor, the second protection transistor, the third protection transistor, and the fourth protection transistor are all PMOS transistors.

[0030] In a second aspect, embodiments of this disclosure provide a control method for a charge pump circuit, applied to the charge pump circuit as described in any one of the first aspects, the method comprising:

[0031] Charge the first node to the input voltage; and / or charge the second node to the input voltage;

[0032] Under the control of the first clock signal, the first node charged to the input voltage is boosted through the first boost capacitor to obtain an output voltage, and the output voltage is applied to the voltage output terminal; and / or, under the control of the second clock signal, the second node charged to the input voltage is boosted through the second boost capacitor to obtain an output voltage, and the output voltage is applied to the voltage output terminal.

[0033] Thirdly, embodiments of this disclosure provide a memory including a charge pump circuit as described in any one of the first aspects.

[0034] This disclosure provides a charge pump circuit, a control method for the charge pump circuit, and a memory. The charge pump circuit includes: a first boost circuit and / or a second boost circuit. The first boost circuit includes a first boost capacitor, and the second boost circuit includes a second boost capacitor. The first plate of the first boost capacitor is connected to a first node, and the first plate of the second boost capacitor is connected to a second node. The first node and the second node are respectively coupled to a voltage input terminal and a voltage output terminal. The second plate of the first boost capacitor receives a first clock signal, and the second plate of the second boost capacitor receives a second clock signal. The first boost circuit, under the control of the first clock signal, boosts the voltage of the first node (charged to the input voltage) through the first boost capacitor to obtain an output voltage, and applies the output voltage to the voltage output terminal. The second boost circuit, under the control of the second clock signal, boosts the voltage of the second node (charged to the input voltage) through the second boost capacitor to obtain an output voltage, and applies the output voltage to the voltage output terminal. Both the first and second boost capacitors are MOS capacitors, and the gate dielectric layer material of the MOS capacitor includes a high dielectric constant material, and the gate of the MOS capacitor includes a metal gate. Thus, in this embodiment of the present disclosure, a MOS capacitor with an HKMG structure is used as the first boost capacitor and the second boost capacitor. On the one hand, since the gate dielectric layer of the MOS capacitor includes a high dielectric constant material, the capacitance values ​​of the first boost capacitor and the second boost capacitor are large. On the other hand, since the gate of the MOS capacitor includes a metal gate with excellent conductivity, the conductivity is increased, thereby effectively reducing ESR. In this way, the current capability and current efficiency of the charge pump circuit are improved. Attached Figure Description

[0035] Figure 1 A schematic diagram of the composition structure of a charge pump circuit provided in this embodiment of the present disclosure. Figure 1 ;

[0036] Figure 2 This is a schematic diagram of the structure of a MOS capacitor provided in an embodiment of the present disclosure;

[0037] Figure 3 A schematic diagram of the composition structure of a charge pump circuit provided in this embodiment of the present disclosure. Figure 2 ;

[0038] Figure 4 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0039] Figure 5 This is a schematic diagram of the structure of an NMOS transistor provided in an embodiment of the present disclosure;

[0040] Figure 6 This is a schematic diagram of the structure of a cylindrical capacitor provided in an embodiment of the present disclosure;

[0041] Figure 7 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0042] Figure 8 A schematic diagram of the composition structure of a charge pump circuit provided in this embodiment of the present disclosure. Figure 3 ;

[0043] Figure 9 This is a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0046] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0047] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0048] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms used in the embodiments of this disclosure will be explained. The nouns and terms used in the embodiments of this disclosure shall be interpreted as follows:

[0049] Dynamic Random Access Memory (DRAM);

[0050] Metal-oxide-semiconductor (MOS);

[0051] Metal-oxide-semiconductor field-effect transistor (MOS transistor);

[0052] P-type metal-oxide-semiconductor field-effect transistor (PMOS transistor);

[0053] N-type metal-oxide-semiconductor field-effect transistor (NMOS transistor);

[0054] Equivalent Series Resistance (ESR);

[0055] Circuit supply voltage / power supply voltage (VCC):

[0056] The chip's internal operating voltage (VDD);

[0057] High K Metal Gate (HKMG);

[0058] High dielectric constant (High K).

[0059] In current DRAM manufacturing processes, the available capacitors are limited to MOS capacitors and ni-cap capacitors. MOS capacitors use polysilicon or a combination of polysilicon, titanium nitride, and tungsten for the gate and silicon oxide and other oxides as the dielectric material, resulting in a high ESR. Ni-cap capacitors, on the other hand, consist of many capacitor pillars connected in parallel. Since the lower electrode of each pillar is tungsten and the upper electrode is silicon-germanium, both materials have high resistivity, leading to a relatively high ESR for ni-cap capacitors. In charge pump circuits, currently, due to process limitations, ni-cap capacitors are typically used as boost capacitors. However, this results in a high ESR for the boost capacitor, severely impacting the current-carrying capacity and efficiency of the charge pump.

[0060] Based on this, embodiments of this disclosure provide a charge pump circuit, including: a first boost circuit and / or a second boost circuit, the first boost circuit including a first boost capacitor, and the second boost circuit including a second boost capacitor; the first plate of the first boost capacitor is connected to a first node, the first plate of the second boost capacitor is connected to a second node, the first node and the second node are respectively coupled to a voltage input terminal and a voltage output terminal, the second plate of the first boost capacitor receives a first clock signal, and the second plate of the second boost capacitor receives a second clock signal; wherein: the first boost circuit is used to boost the voltage of the first node charged to the input voltage through the first boost capacitor under the control of the first clock signal to obtain an output voltage, and apply the output voltage to the voltage output terminal; the second boost circuit is used to boost the voltage of the second node charged to the input voltage through the second boost capacitor under the control of the second clock signal to obtain an output voltage, and apply the output voltage to the voltage output terminal; wherein the first boost capacitor and the second boost capacitor are both MOS capacitors, and the gate dielectric layer material of the MOS capacitor includes a high dielectric constant material, and the gate of the MOS capacitor includes a metal gate. Thus, in this embodiment of the present disclosure, a MOS capacitor with an HKMG structure is used as the first boost capacitor and the second boost capacitor. On the one hand, since the gate dielectric layer of the MOS capacitor includes a high dielectric constant material, the capacitance values ​​of the first boost capacitor and the second boost capacitor are large. On the other hand, since the gate of the MOS capacitor includes a metal gate with excellent conductivity, the conductivity is increased, thereby effectively reducing ESR. In this way, the current capability and current efficiency of the charge pump circuit are improved.

[0061] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0062] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 It shows a schematic diagram of the composition structure of a charge pump circuit 10 provided in an embodiment of this disclosure. Figure 1 .like Figure 1As shown, the charge pump circuit 10 includes a first boost circuit 11 and / or a second boost circuit 12; the first boost circuit 11 includes a first boost capacitor cm1, and the second boost circuit 12 includes a second boost capacitor cm2; the first plate of the first boost capacitor cm1 is connected to a first node N1, and the first plate of the second boost capacitor cm2 is connected to a second node N2. Both the first node N1 and the second node N2 are coupled to a voltage input terminal and a voltage output terminal, respectively. The second plate of the first boost capacitor cm1 receives a first clock signal CLK1, and the second plate of the second boost capacitor cm2 receives a second clock signal CLK2; wherein:

[0063] The first boost circuit 11 is used to boost the first node N1, which is charged to the input voltage Vin, through the first boost capacitor cm1 under the control of the first clock signal CLK1, to obtain the output voltage V_pump, and apply the output voltage V_pump to the voltage output terminal.

[0064] The second boost circuit 12 is used to boost the second node N2, which is charged to the input voltage Vin, through the second boost capacitor cm2 under the control of the second clock signal CLK2, to obtain the output voltage V_pump, and apply the output voltage V_pump to the voltage output terminal;

[0065] Among them, the first boost capacitor cm1 and the second boost capacitor cm2 are both MOS capacitors, and the gate dielectric layer material of the MOS capacitor includes a high dielectric constant material, and the gate of the MOS capacitor includes a metal gate.

[0066] It should be noted that a charge pump circuit can boost the input voltage and output it. For example... Figure 1 As shown, the voltage input terminal serves as the input terminal of the charge pump circuit 10, used to receive the input voltage Vin. In this embodiment, the voltage input terminal is connected to VCC, which can provide a power supply voltage vcc, for example, vcc is 1.1V or other voltage values. In other embodiments, the voltage input terminal can also be connected to other circuits or devices to input the input voltage provided by other circuits or devices. This is not specifically limited. This embodiment uses VCC as an example for description.

[0067] It should also be noted that the charge pump circuit 10 includes a first boost circuit 11 and / or a second boost circuit 12. That is, boosting can be achieved by either the first boost circuit 11 or the second boost circuit 12, or boosting can be achieved by both the first boost circuit 11 and the second boost circuit 12.

[0068] Combination Figure 1As shown, the boosting process using the first boost circuit 11 is as follows: First, the first node N1 is charged to the power supply voltage Vcc. Then, the voltage of the first plate of the first boost capacitor cm1 is the same as that of the first node N1, which is the power supply voltage Vcc. At the same time, the first clock signal CLK1 is in a low level state (logic 0), so the voltage of the second plate of the first boost capacitor cm1 is 0. Thus, there is a voltage difference of power supply voltage Vcc between the first plate and the second plate of the first boost capacitor cm1. When the rising edge of the first clock signal CLK1 arrives, the first clock signal CLK1 becomes a high level state (logic 1). Here, taking the high level state voltage values ​​of the first clock signal CLK1 and the subsequent second clock signal CLK2, third clock signal CLK3 and fourth clock signal CLK4 as an example, all are the voltage provided by VDD, vdd = 1.8V. At this time, in order to maintain the voltage difference between the first plate and the second plate of the first boost capacitor cm1 as the power supply voltage Vcc, the voltage of the first node N1 is boosted to Vcc + Vdd and applied to the voltage output terminal. Thus, after processing by the first boost circuit 11, the input voltage Vin has a voltage value of vcc, while the output voltage V_pump has a voltage value of vcc+vdd, achieving boost processing.

[0069] Similarly, the boost process using the second boost circuit 12 is as follows: First, the second node N2 is charged to the power supply voltage vcc. Then, the voltage of the first plate of the second boost capacitor cm2 is the same as the power supply voltage vcc. Simultaneously, the second clock signal CLK2 is at a low level, and the voltage of the second plate of the second boost capacitor cm2 is 0. Therefore, there is a voltage difference of the power supply voltage vcc between the first and second plates of the second boost capacitor cm2. When the rising edge of the second clock signal CLK2 arrives, CLK2 becomes high. At this time, in order to maintain the voltage difference between the first and second plates of the second boost capacitor cm2 at the power supply voltage vcc, the voltage of the second node N2 is boosted to vcc + vdd and applied to the voltage output terminal. Thus, after processing by the second boost circuit N2, the input voltage Vin is vcc, and the output voltage V_pump is vcc + vdd, achieving the boost process.

[0070] Furthermore, when the charge pump circuit 10 includes a first boost circuit 11 and a second boost circuit 12, both the first boost circuit 11 and the second boost circuit 12 participate in the boost process, and the boost process and principle of the first node N1 and the second node N2 are consistent with the foregoing description. Specifically, in this case, the first boost circuit 11 and the second boost circuit 12 are used to alternately boost the first node N1 and the second node N2 to obtain an output voltage V_pump, and apply the output voltage V_pump to the voltage output terminal.

[0071] In this embodiment of the disclosure, both the first boost capacitor cm1 and the second boost capacitor cm2 are MOS capacitors. For example, see [link to example]. Figure 2 It shows a schematic diagram of the composition structure of a MOS capacitor provided in an embodiment of this disclosure, such as... Figure 2 As shown, the MOS capacitor includes a substrate, a gate dielectric layer, and a gate stacked sequentially.

[0072] The substrate contains a P-type well region and two N+ doped regions (N+) forming an NMOS transistor. Specifically, the first boost capacitor cm1 and the second boost capacitor cm2 can both be NMOS transistors. Here, the two N+ doped regions serve as the source and drain, respectively. In this embodiment, the source and drain of each MOS transistor are not specifically distinguished and are referred to as the first terminal and the second terminal, respectively. The specific choice of which of the first terminal and the second terminal serves as the source and which as the drain depends on the actual connection method of the MOS transistor.

[0073] A gate dielectric layer is formed sequentially on the substrate by silicon oxide (SiO), hafnium silicate oxide (HfSiO) and lanthanum oxide (LaO), and a metal gate is formed sequentially on the gate dielectric layer by titanium nitride (TiN) and polysilicon (Poly-Si).

[0074] It should be noted that, in this embodiment, the MOS capacitor has an HKMG structure, and includes a High K material in the gate dielectric layer, for example... Figure 2 The HfSiO and LaO are used; the gate is a metal gate (MG), which can include not only metallic materials but also other materials with good conductivity, such as... Figure 2 TiN in the text. This is understandable. Figure 2 The example shown is only one example of a MOS capacitor and is not limited thereto. The gate dielectric layer may also include high-K materials such as hafnium oxide, zirconium oxide, aluminum oxide, hafnium silicon oxide, and hafnium nitride, and the metal gate may also include materials such as aluminum, copper, silver, and tungsten. No limitation is made in this regard.

[0075] It should also be noted that the capacitance of a capacitor can be characterized by the following formula: C = εS / d, where C represents the capacitance, ε is the dielectric constant of the dielectric between the plates, S is the plate area, and d is the distance between the plates. In this embodiment, since a MOS capacitor with an HKMG structure is used as the first boost capacitor cm1 and the second boost capacitor cm2, the dielectric between the plates of the first boost capacitor cm1 and the second boost capacitor cm2 is a High K material with a high ε value. Therefore, the capacitance of the first boost capacitor cm1 and the second boost capacitor cm2 is large, which is beneficial for improving the current capability and current efficiency of the charge pump, thereby improving the performance of the charge pump.

[0076] Meanwhile, since the gates of the first boost capacitor cm1 and the second boost capacitor cm2 are made of metal gates with excellent conductivity, the conductivity can be increased, thereby effectively reducing ESR, and also improving the current capability and current efficiency of the charge pump, further improving the performance of the charge pump.

[0077] It should also be noted that, in Figure 2 In this example, the MOS capacitor is an NMOS transistor. In other embodiments, the first boost capacitor cm1 and the second boost capacitor cm2 can also be PMOS transistors. In this case, an N-well region and a P+ doped region are formed in the substrate. The specific structure is similar to... Figure 2 Similarly, I will not go into details here.

[0078] Furthermore, in Figure 1 Based on this, see Figure 3 It illustrates a schematic diagram of the composition structure of a charge pump circuit provided in an embodiment of this disclosure. Figure 2 ,like Figure 3 As shown, in some embodiments, the first boost circuit 11 further includes a first switching circuit s1 and a second switching circuit s2; the second boost circuit 12 further includes a third switching circuit s3 and a fourth switching circuit s4; wherein:

[0079] The first switching circuit s1 is connected between the voltage input terminal and the first node N1. It is used to receive the third clock signal CLK3 and control the first node N1 to charge to the input voltage Vin according to the third clock signal CLK3.

[0080] The second switching circuit s2 is connected between the first node N1 and the voltage output terminal, and is used to connect the first node N1, which is boosted to the output voltage V_pump, and the voltage output terminal according to the voltage control of the second node N2.

[0081] The third switching circuit s3 is connected between the voltage input terminal and the second node N2. It is used to receive the fourth clock signal CLK4 and control the second node N2 to charge to the input voltage Vin according to the fourth clock signal CLK4.

[0082] The fourth switching circuit s4 is connected between the second node N2 and the voltage output terminal. It is used to connect the second node N2, which is boosted to the output voltage V_pump, with the voltage output terminal according to the voltage control of the first node N1.

[0083] It should be noted that, taking the input voltage Vin as an example, where the voltage value is the power supply voltage Vcc, for instance... Figure 3 As shown, in the first boost circuit 11, the first switching circuit s1 is used to control whether the first node N1 is charged to the power supply voltage vcc. Under the control of the third clock signal CLK3, the first switching circuit s1 is in the on state or the off state. When the first switching circuit s1 is in the on state, the path between the voltage input terminal and the first node N1 is opened, thereby charging the first node N1 to the power supply voltage vcc. Then, combined with the first clock signal CLK1, under the action of the first boost capacitor cm1, the voltage of the first node N1 is boosted to the output voltage V_pump=vcc+vdd. Then, if the second switching circuit s2 is in the on state, the path between the first node N1 and the voltage output terminal is opened, and the voltage at the first node N1 is applied to the voltage output terminal, so that the voltage at the voltage output terminal reaches vcc+vdd, thereby realizing the boost.

[0084] like Figure 3 As shown, in the second boost circuit 12, the third switch circuit s3 is used to control whether the second node N2 is charged to the power supply voltage vcc. Under the control of the fourth clock signal CLK4, the third switch circuit s3 is in the on state or the off state. When the third switch circuit s3 is in the on state, the path between the voltage input terminal and the second node N2 is opened, thereby charging the second node N2 to the power supply voltage vcc. Then, combined with the second clock signal CLK2, under the action of the second boost capacitor cm2, the voltage of the second node N2 is boosted to the output voltage V_pump=vcc+vdd. Then, if the fourth switch circuit s4 is in the on state, the path between the second node N2 and the voltage output terminal is opened, and the voltage at the second node N2 is applied to the voltage output terminal, so that the voltage at the voltage output terminal reaches vcc+vdd, realizing the boost.

[0085] It should also be noted that, such as Figure 3As shown, the first boost circuit 11 and the second boost circuit 12 can form a cross-coupled structure. The voltage at the second node N2 controls the conduction or disconnection of the second switching circuit s2, and the voltage at the first node N1 controls the conduction or disconnection of the fourth switching circuit s4. Thus, the first boost circuit 11 and the second boost circuit 12 are used to alternately boost the output voltage to vcc+vdd.

[0086] Specifically, when the first node N1 is pre-charged to the power supply voltage Vcc, the second node N2 is connected to the voltage output terminal; when the first node N1 is boosted to the output voltage V_pump, the connection between the second node N2 and the voltage output terminal is disconnected. Similarly, when the second node N2 is pre-charged to the power supply voltage Vcc, the first node N1 is connected to the voltage output terminal; when the second node N2 is boosted to the output voltage V_pump, the connection between the first node N1 and the voltage output terminal is disconnected.

[0087] For the specific composition of each switching circuit, please refer to [link / reference]. Figure 3 In some embodiments, the first switching circuit s1 includes a first transistor m1 and a first capacitor c1; the second switching circuit s2 includes a second transistor m2; the third switching circuit s3 includes a third transistor m3 and a second capacitor c2; and the fourth switching circuit s4 includes a fourth transistor m4; wherein:

[0088] The first terminal of the first transistor m1 and the first terminal of the third transistor m3 are both connected to the voltage input terminal; the second terminal of the first transistor m1, the first terminal of the second transistor m2, and the control terminal of the fourth transistor m4 are all connected to the first node N1; the control terminal of the first transistor m1 is connected to the first plate of the first capacitor c1, and the second plate of the first capacitor c1 receives the third clock signal CLK3; the second terminal of the third transistor m3, the first terminal of the fourth transistor m4, and the control terminal of the second transistor m2 are all connected to the second node N2; the control terminal of the third transistor m3 is connected to the first plate of the second capacitor c2, and the second plate of the second capacitor c2 receives the fourth clock signal; the second terminal of the second transistor m2 and the second terminal of the fourth transistor m4 are both connected to the voltage output terminal.

[0089] It should be noted that, as Figure 3 As shown, the first transistor m1 and the third transistor m3 are both NMOS transistors; the second transistor m2 and the fourth transistor m4 are both PMOS transistors.

[0090] Thus, for the first transistor m1, when the rising edge of the third clock signal CLK3 arrives and the level changes to a high level, the voltage at the control terminal of the first transistor m1 is raised to a high level based on the coupling effect of the first capacitor c1, thereby turning on the first transistor m1 and thus opening the path between the voltage input terminal and the first node N1, thereby charging the first node N1 to the power supply voltage vcc; when the falling edge of the third clock signal CLK3 arrives and the level changes to a low level, the voltage at the control terminal of the first transistor m1 is lowered to a low level based on the coupling effect of the first capacitor c1, thereby turning off the first transistor m1.

[0091] For the third transistor m3, when the rising edge of the fourth clock signal CLK4 arrives and the level changes to a high level, the control terminal voltage of the third transistor m3 is raised to a high level based on the coupling effect of the second capacitor c2, thereby turning on the third transistor m3 and thus opening the path between the voltage input terminal and the second node N2, enabling the second node N2 to be charged to the power supply voltage vcc; when the falling edge of the fourth clock signal CLK4 arrives and the level changes to a low level, the control terminal voltage of the third transistor m3 is lowered to a low level based on the coupling effect of the second capacitor c2, thereby turning off the third transistor m3.

[0092] Furthermore, since the first boost circuit 11 and the second boost circuit 12 form a cross-coupled structure, the voltage at the first node N1 and the voltage at the second node N2 jointly control the conduction and cutoff of the second transistor m2 and the fourth transistor m4. When the voltage at the first node N1 rises to vcc+vdd and the second node N2 is charged to the power supply voltage vcc, the voltage (vcc) at the control terminal of the second transistor m2 is lower than the voltage (vcc+vdd) at the first terminal, thus the second transistor m2 conducts, opening the path between the first node N1 and the voltage output terminal, and applying the boosted output voltage V_pump to the voltage output terminal for output. Similarly, when the voltage at the second node N2 rises to vcc+vdd and the first node N1 is charged to the power supply voltage vcc, the voltage (vcc) at the control terminal of the fourth transistor m4 is lower than the voltage (vcc+vdd) at the first terminal, thus the fourth transistor m4 conducts, opening the path between the second node N2 and the voltage output terminal, and applying the boosted output voltage V_pump to the voltage output terminal for output.

[0093] When the first boost circuit 11 and the second boost circuit 12 alternately boost voltage, in order to ensure that the charge pump circuit 10 works normally and can boost voltage, the timing requirements of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 are required.

[0094] In a preferred implementation, see [link to preferred implementation]. Figure 4 It illustrates a signal timing diagram provided in an embodiment of this disclosure. Figure 1 .

[0095] Combination Figure 3 and Figure 4 As shown, when the fourth clock signal CLK4 is high, the third transistor m3 is turned on, charging the second node N2 to the power supply voltage vcc. During the boost process, the second clock signal CLK2 first shows a rising edge, thus boosting the second node N2 to the output voltage V_pump = vcc + vdd; then the third clock signal CLK3 shows a rising edge, turning on the first transistor m1, charging the first node N1 to the power supply voltage vcc; then the first clock signal CLK1 shows a falling edge and enters a low level, not boosting the first node N1, and the voltage at the first node N1 remains at the power supply voltage vcc; then the fourth clock signal... At the falling edge, the third transistor m3 is turned off, and the voltage at the second node N2 is clamped at vcc + vdd. Meanwhile, for the fourth transistor m4, the voltage at its control terminal is the voltage vcc at the first node N1, and the voltage at its first terminal is the voltage vcc + vdd at the second node N2. Thus, the fourth transistor m4 is turned on, and the voltage at the second node N2 is applied to the voltage output terminal, resulting in an output voltage V_pump of vcc + vdd. Simultaneously, for the second transistor m2, the voltage at its control terminal is the voltage vcc + vdd at the second node N2, and the voltage at its first terminal is the voltage vcc at the first node N1, remaining in the off state. In this way, voltage boosting is achieved using the second boost circuit 12 coupled to the first boost circuit 11.

[0096] After the second boost circuit 12 boosts the output voltage V_pump to vcc + vdd, the first node N1 is already charged to the power supply voltage vcc. During the boosting process of the first boost circuit 11, the first clock signal CLK1 first appears with a rising edge, boosting the first node N1 to the output voltage V_pump = vcc + vdd; then the fourth clock signal CLK4 appears with a rising edge, the third transistor m3 turns on, and the second node N2 is charged to the power supply voltage vcc; then the second clock signal CLK2 appears with a falling edge, enters a low level state, and does not boost the second node N2, the voltage at the second node N2 remains at the power supply voltage vcc; then the third clock signal... When CLK3 experiences a falling edge, the first transistor m1 is turned off, and the voltage at the first node N1 is clamped at vcc + vdd. At this time, for the second transistor m2, the voltage at its control terminal is the voltage vcc at the second node N2, and the voltage at its first terminal is the voltage vcc + vdd at the first node N1. Therefore, the second transistor m2 is turned on, and the voltage at the first node N1 is applied to the voltage output terminal, resulting in an output voltage V_pump of vcc + vdd. Simultaneously, for the fourth transistor m4, the voltage at its control terminal is the voltage vcc + vdd at the first node N1, and the voltage at its first terminal is the voltage vcc at the second node N2, meaning it is in the off state. Thus, voltage boosting is achieved using the first boost circuit 11 coupled with the second boost circuit 12.

[0097] In other words, to ensure the normal operation of the charge pump circuit 10, the clock edges of each clock signal have the following relationship:

[0098] The rising edge of the second clock signal CLK2 is earlier than the rising edge of the third clock signal CLK3;

[0099] The rising edge of the third clock signal CLK3 precedes the falling edge of the first clock signal CLK1;

[0100] The falling edge of the first clock signal CLK1 precedes the falling edge of the fourth clock signal CLK4;

[0101] The rising edge of the first clock signal CLK1 is earlier than the rising edge of the fourth clock signal CLK4;

[0102] The rising edge of the fourth clock signal CLK4 precedes the falling edge of the second clock signal CLK2;

[0103] The falling edge of the second clock signal CLK2 precedes the falling edge of the third clock signal CLK3.

[0104] Based on the aforementioned timing control, the first boost circuit 11 and the second boost circuit 12 alternately boost the voltage of the first node N1 and the second node N2 to obtain the output voltage V_pump, which is then applied to the voltage output terminal to achieve voltage boosting. Furthermore, Figure 4 The timing shown is merely an example. As long as charging, turning on the corresponding transistors, and boosting are performed at the appropriate times, the clock signals can also have other appropriate timing relationships.

[0105] It should also be noted that, in order to ensure accurate control over the on / off states of the first transistor m1 and the third transistor m3, the effective voltage levels of the third clock signal CLK3 and the fourth clock signal CLK4 are greater than the input voltage Vin. Here, the effective voltage level refers to the voltage value of the clock signal when it is at a high logic level (logic 1).

[0106] Taking the high-level voltages of the third clock signal CLK3 and the fourth clock signal CLK4 as vdd = 1.8V, and the input voltage Vin as the power supply voltage vcc = 1.1V as an example, when the third clock signal CLK3 is high, the voltage at the control terminal of the first transistor m1 is higher than the voltage at its first terminal, and the first transistor m1 is turned on. When the third clock signal CLK1 is low, the voltage at the control terminal of the first transistor m1 is lower than the voltage at its first terminal, and the first transistor m1 is turned off. Similarly, when the fourth clock signal CLK4 is high, the voltage at the control terminal of the third transistor m3 is higher than the voltage at its first terminal, and the third transistor m3 is turned on. When the fourth clock signal CLK4 is low, the voltage at the control terminal of the third transistor m3 is lower than the voltage at its first terminal, and the third transistor m3 is turned off.

[0107] In addition, the first clock signal CLK1 and the second clock signal CLK2 have the same high-level and low-level states as the third clock signal CLK3 and the fourth clock signal CLK4, and the effective voltage of the first clock signal CLK1 and the second clock signal CLK2 is also greater than the input voltage Vin.

[0108] In this embodiment, the first boost capacitor cm1 and the second boost capacitor cm2 are MOS capacitors with an HKMG structure, and the specific structure can be referred to Figure 2 The first transistor m1, the second transistor m2, the third transistor m3, and the fourth transistor m4 are polysilicon transistors. For example, using an NMOS transistor, see [link to relevant documentation]. Figure 5 This illustrates a schematic diagram of an NMOS transistor provided in an embodiment of this disclosure. Figure 5As shown, the NMOS transistor includes a substrate, a gate dielectric layer, and a gate stacked sequentially.

[0109] The substrate contains a P-type well region and two N+ doped regions (N+), which serve as the source and drain, respectively.

[0110] Silicon oxide (SiO) formed on the substrate forms the gate dielectric layer, and polysilicon (Poly-Si), titanium nitride (TiN) and tungsten (W) formed sequentially on the gate dielectric layer form the polysilicon gate.

[0111] and Figure 2 Compared to the MOS capacitor with the HKMG structure shown, the gate oxide layer (i.e., SiO) of the MOS capacitor is thinner than that of the NMOS transistor with a polysilicon gate, thus the MOS capacitor has a larger unit capacitance. In other words, in this embodiment, the gate oxide layers of the first boost capacitor cm1 and the second boost capacitor cm2 are thinner than the gate oxide layers of the first transistor m1, the second transistor m2, the third transistor m3, and the fourth transistor m4.

[0112] It is understandable that although the second transistor m2 and the fourth transistor m4 are PMOS transistors, their structures are similar to... Figure 6 The PMOS transistor is similar to the NMOS transistor shown, except for the type of substrate doping. In the PMOS transistor, an N-well region is formed in the substrate, and the source and drain are P+ doped. Figure 5 The structure shown is merely illustrative and is not intended to be specific.

[0113] In this way, the first transistor m1, the second transistor m2, the third transistor m3 and the fourth transistor m4 still use MOS transistors with polysilicon gates, instead of transistors with HKMG structure, to avoid the impact of increased reverse leakage current on current efficiency.

[0114] In this embodiment, both the first capacitor c1 and the second capacitor c2 are cylindrical capacitors. See also Figure 6 This illustrates a schematic diagram of the structural composition of a cylindrical capacitor provided in an embodiment of this disclosure. Figure 6 As shown, the first capacitor c1 and the second capacitor c2 are composed of multiple columnar capacitors connected in parallel. Each columnar capacitor is connected to a capacitor plate in the substrate. From the inside to the outside of the capacitor column, the capacitor column includes a negative electrode, a dielectric layer and a positive electrode in sequence.

[0115] Furthermore, to enhance signal driving capability and avoid signal glitches that could hinder the normal operation of the charge pump circuit 10, this embodiment also utilizes a driving circuit to obtain a clock signal with strong driving capability. Therefore, in some embodiments, such as Figure 3 As shown, the charge pump circuit 10 also includes a first driving circuit Drv1, a second driving circuit Drv2, a third driving circuit Drv3, and a fourth driving circuit Drv4, wherein:

[0116] The first driving circuit Drv1 is used to receive the first preset clock signal CLK01, perform driving enhancement processing on the first preset clock signal CLK01, and obtain the first clock signal CLK1.

[0117] The second driving circuit Drv2 is used to receive the second preset clock signal CLK02, perform driving enhancement processing on the second preset clock signal CLK02, and obtain the second clock signal CLK2.

[0118] The third driving circuit Drv3 is used to receive the third preset clock signal CLK03, perform driving enhancement processing on the third preset clock signal CLK03, and obtain the third clock signal CLK3.

[0119] The fourth driving circuit Drv4 is used to receive the fourth preset clock signal CLK04, perform driving enhancement processing on the fourth preset clock signal CLK04, and obtain the fourth clock signal CLK4.

[0120] It should be noted that, as Figure 3 As shown, the input terminal of the first driving circuit Drv1 receives the first preset clock signal CLK01, and the output terminal of the first driving circuit Drv1 is connected to the second plate of the first boost capacitor cm1; the input terminal of the second driving circuit Drv2 receives the second preset clock signal CLK02, and the output terminal of the second driving circuit Drv2 is connected to the second plate of the second boost capacitor cm2; the input terminal of the third driving circuit Drv3 receives the third preset clock signal CLK03, and the output terminal of the third driving circuit Drv3 is connected to the second plate of the first capacitor c1; the input terminal of the fourth driving circuit Drv4 receives the fourth preset clock signal CLK04, and the output terminal of the fourth driving circuit Drv4 is connected to the second plate of the second capacitor c2.

[0121] In this way, each driving circuit performs driving enhancement processing on each preset clock signal to enhance the driving capability of each clock signal, so as to ensure the normal operation of the charge pump circuit 10.

[0122] In some embodiments, such as Figure 3 As shown, the first driving circuit Drv1, the second driving circuit Drv2, the third driving circuit Drv3, and the fourth driving circuit Drv4 all include an odd number of inverters; and in the first driving circuit Drv1 and the second driving circuit Drv2, the gate dielectric layer material of the transistor in the inverter includes a high dielectric constant material, and the gate of the transistor in the inverter includes a metal gate.

[0123] It should be noted that each drive circuit may contain an odd number of inverters (e.g., Figure 3 (As shown in Figure 1), then the input and output signal levels of each driving circuit are opposite. See details... Figure 7 .like Figure 7 As shown, the clock edges of each preset clock signal can have the following timing relationship: the falling edge of the second preset clock signal CLK02 is earlier than the falling edge of the third preset clock signal CLK03; the falling edge of the third preset clock signal CLK03 is earlier than the rising edge of the first preset clock signal CLK01; the rising edge of the first preset clock signal CLK01 is earlier than the rising edge of the fourth preset clock signal CLK04; the falling edge of the first preset clock signal CLK01 is earlier than the falling edge of the fourth preset clock signal CLK04; the falling edge of the fourth preset clock signal CLK04 is earlier than the rising edge of the second preset clock signal CLK02; and the rising edge of the second preset clock signal CLK02 is earlier than the rising edge of the third preset clock signal CLK03. It can be understood that, similar to the aforementioned clock signals, each preset clock signal can also have other appropriate timing relationships, as long as they can meet the normal operating requirements of the charge pump circuit 10.

[0124] like Figure 7 As shown, the first preset clock signal CLK01, the second preset clock signal CLK02, the third preset clock signal CLK03, and the fourth preset clock signal CLK04 all have the same duty cycle and the same clock period; and within one clock period, the low-level state time of the first preset clock signal CLK01, the second preset clock signal CLK02, the third preset clock signal CLK03, and the fourth preset clock signal CLK04 is longer than the high-level state time.

[0125] Correspondingly, such as Figure 4 As shown, the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 all have the same duty cycle and the same clock period; and within one clock period, the high-level state time of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 is longer than the low-level state time.

[0126] Here, the high-level state can be referred to as the first level state, and the low-level state as the second level state. Thus, by designing the duty cycle of each clock signal / preset clock signal, the charge pump circuit 10 is made to operate normally, achieving voltage boost.

[0127] Alternatively, each driver circuit can contain an even number of inverters. In this case, the input and output signals of each driver circuit have the same level and are delayed. The timing of each preset clock signal can still be referenced. Figure 4 As shown.

[0128] It should also be noted that, in order to further improve the current capability, the transistors that make up each inverter in the first driving circuit Drv1 and the second driving circuit Drv2 also use the HKMG structure, which will further improve the conversion efficiency of the first driving circuit Drv1 and the second driving circuit Drv2.

[0129] In this embodiment, the second transistor m2 and the fourth transistor m4 are four-terminal devices, meaning that in addition to the gate, source, and drain, the substrate terminal also needs to be considered. The second transistor m2 and the fourth transistor m4 are PMOS transistors, and their substrate voltage must always be greater than or equal to the source or drain voltage; otherwise, the parasitic diodes (the parasitic diodes from the source to the substrate or from the drain to the substrate) will conduct in the forward direction, causing a latch-up effect, leading to circuit failure or burnout.

[0130] Therefore, to avoid latch-up effects, this embodiment also utilizes dynamic trap technology to protect the second transistor m2 and the fourth transistor m4, ensuring that the substrate voltages of the second transistor m2 and the fourth transistor m4 meet the requirements. For details, see... Figure 8 , its purpose is Figure 3 Based on this, the present disclosure provides a schematic diagram of the composition structure of a charge pump circuit. Figure 3 In some embodiments, such as Figure 8 As shown, the charge pump circuit 10 also includes a first protection circuit 13 and a second protection circuit 14. The first protection circuit 13 includes a first protection transistor p1 and a second protection transistor p2, and the second protection circuit 14 includes a third protection transistor p3 and a fourth protection transistor p4; wherein:

[0131] The control terminal of the first protection transistor p1 is connected to the second node N2. The first terminal of the first protection transistor p1 and the control terminal of the second protection transistor p2 are both connected to the first node N1. The second terminal of the first protection transistor p1, the first terminal of the second protection transistor p2, the substrate of the first protection transistor p1, and the substrate of the second protection transistor p2 are all connected to the substrate of the second transistor p2. The second terminal of the second protection transistor p2 is connected to the voltage output terminal.

[0132] The control terminal of the third protection transistor p3 is connected to the first node N1. The first terminal of the third protection transistor p3 and the control terminal of the fourth protection transistor p4 are both connected to the second node N2. The second terminal of the third protection transistor p3, the first terminal of the fourth protection transistor p4, the substrate of the third protection transistor p3, and the substrate of the fourth protection transistor p4 are all connected to the substrate of the fourth transistor p4. The second terminal of the fourth protection transistor p4 is connected to the voltage output terminal.

[0133] Furthermore, such as Figure 8 As shown, the first protection transistor p1, the second protection transistor p2, the third protection transistor p3, and the fourth protection transistor p4 are all PMOS transistors.

[0134] It should be noted that, taking the second protection circuit 14 as an example, it is necessary to ensure that the substrate voltage of the fourth transistor m4 is always greater than or equal to its source / drain voltage. After the second node N2 is boosted, the voltage value of the second node N2 is vcc+vdd, which is the highest voltage that the charge pump circuit 10 can achieve. At this time, the voltage of the first terminal of the fourth transistor m4 is the same as the voltage of the second node N2, which is vcc+vdd. It is necessary to connect the substrate of the fourth transistor m4 to the second node N2 as well, so that the substrate voltage of the fourth transistor m4 is also vcc+vdd, ensuring that the substrate voltage of the fourth transistor m4 will not be less than the voltage of its first or second terminal. Since the control terminal of the third protection transistor p3 is connected to the first node N1, when the voltage of the second node N2 is vcc+vdd and the voltage of the first node N1 is vcc, the fourth transistor m4 is turned on. At the same time, the third protection transistor p3 is turned on and the fourth protection transistor p4 is turned off. Thus, the second node N2 and the substrate of the fourth transistor m4 are connected through the third protection transistor p3, so that the substrate voltage of the fourth transistor m4 is vcc+vdd, which plays a protective role.

[0135] After boosting the voltage of the first node N1, the voltage value of the first node N1 is vcc+vdd, the voltage value of the second node N2 is vcc, the fourth transistor m4 is cut off, and the second transistor m2 is turned on, thereby applying the output voltage (vcc+vdd) to the voltage output terminal. At this time, the third protection transistor p3 is cut off, and the fourth protection transistor p4 is turned on, thereby connecting the voltage output terminal with the substrate of the fourth transistor m4 through the fourth protection transistor p4, making the substrate voltage of the fourth transistor m4 vcc+vdd, thus playing a protective role.

[0136] The first protection circuit 13 protects the second transistor m2 in the same way, ensuring that the substrate voltage of the second transistor m2 is always greater than or equal to the voltage of its first or second terminal, which will not be described in detail here.

[0137] Thus, this embodiment incorporates dynamic trap technology into the charge pump circuit 10 to protect the second transistor m2 and the fourth transistor m4, ensuring that the substrate voltage of the second transistor m2 and the fourth transistor m4 is always not lower than their source / drain voltage, avoiding latch-up effects, and thus preventing circuit failure or burnout.

[0138] In short, charge pumps are widely used in memory such as LPDDR. The typical metrics for evaluating charge pumps are current capability and current efficiency. This embodiment provides a technical solution to optimize the current capability and improve the current efficiency of charge pumps. Specifically, refer to... Figure 3 In this embodiment, the first boost capacitor cm1 and the second boost capacitor cm2 used for voltage boosting are replaced with MOS capacitors with an HKMG structure. For the HKMG structure, the use of a metal (or other material with good conductivity) as the gate and a High K material such as hafnium oxide as the gate dielectric layer effectively reduces ESR and increases capacitance. To further improve current capability, the first drive circuit Drv1 and the second drive circuit Drv2 will also use MOS transistors with an HKMG structure, further improving the conversion rate of the first drive circuit Drv1 and the second drive circuit Drv2. Furthermore, the first transistor m1, the second transistor m2, the third transistor m3, and the fourth transistor m4 still use polysilicon gates because using an HKMG structure for these devices would increase reverse leakage current, thus affecting current efficiency.

[0139] Combination Figure 7As shown, the third preset clock signal CLK03 and the first preset clock signal CLK01 are overlapping clocks, and the fourth preset clock signal CLK04 and the second preset clock signal CLK02 are overlapping clocks. The high level of the first preset clock signal CLK01, the second preset clock signal CLK02, the third preset clock signal CLK03, and the fourth preset clock signal CLK04 is vdd. Thus, when the first transistor m1 is turned off, the first node N1 is boosted to vcc + vdd, for example, vcc is 1.1V and vdd is 1.8V. When a voltage boost of V_pump to 2.2V~2.9V is required, only one stage of charge pump can be used. In contrast, when the high level of the third preset clock signal CLK03 and the fourth preset clock signal CLK04 is vcc, a second stage of charge pump is required to boost V_pump to a voltage value of 2.2V~2.9V. This embodiment targets, but is not limited to, applications where V_pump has a voltage value of 2.2V to 2.9V, resulting in a significant improvement in current capability and current efficiency. Furthermore, the third preset clock signal CLK03 and the fourth preset clock signal CLK04 are overlapping clocks, as are the first preset clock signal CLK01 and the second preset clock signal CLK02. The falling edge of the second preset clock signal CLK02 slightly leads the falling edge of the third preset clock signal CLK03. This ensures that after the second node N2 is boosted to Vcc + Vdd, the first transistor m1 is turned on, causing the fourth transistor m4 to conduct, while the second transistor m2 is turned off. Each preset clock signal needs to have the above timing sequence to ensure the normal operation of the charge pump circuit 10, thereby improving both current capability and current efficiency.

[0140] Furthermore, the first transistor m1, the second transistor m2, the third transistor m3, and the fourth transistor m4 are devices with polysilicon gates (e.g., Figure 5 The first boost transistor cm1 and the second boost transistor cm2 are devices with an HKMG structure (e.g., Figure 2 When this charge pump circuit 10 is applied to DRAM, both devices have specific requirements related to DRAM manufacturing processes. For example... Figure 5 As shown, the NMOS transistor has a top-to-bottom structure of w / TiN / Poly-Si / SiO, for example... Figure 2 As shown, the MOS capacitor with the HKMG structure has a top-to-bottom structure of Poly-Si / TiN / LaO / HfSiO / SiO. Notably, the SiO in the HKMG structure is much thinner than the polysilicon gate, which is why its capacitance per unit area can be larger. The first capacitor c1 and the second capacitor c2 are cylindrical capacitors (ni-cap, for example...). Figure 6 ).

[0141] Finally, combining Figure 8As shown, in practical applications, dynamic well technology is incorporated into the second transistor m2 and the fourth transistor m4. Taking the fourth transistor m4 as an example, the gate of the third protection transistor p3 is connected to the first node N1, the gate of the fourth protection transistor p4 is connected to the second node N2, the source of the third protection transistor p3 is connected to the second node N2, and the source of the fourth protection transistor p4 is connected to the voltage output terminal. The drains and substrates of both the third and fourth protection transistors p3 and p4 are connected to the substrate of the fourth transistor m4. This ensures that the substrate voltage of the fourth transistor m4 meets the requirements. The same principle applies to the second transistor m2.

[0142] In another embodiment of this disclosure, based on the aforementioned charge pump circuit 10, this embodiment also provides a control method for the charge pump circuit. The method includes the following steps:

[0143] S101: Charge the first node N1 to the input voltage Vin; and / or charge the second node N2 to the input voltage Vin.

[0144] S102: Under the control of the first clock signal CLK1, the first node N1, which is charged to the input voltage Vin, is boosted through the first boost capacitor cm1 to obtain the output voltage V_pump, and the output voltage V_pump is applied to the voltage output terminal; and / or, under the control of the second clock signal CLK2, the second node N2, which is charged to the input voltage Vin, is boosted through the second boost capacitor cm2 to obtain the output voltage V_pump, and the output voltage V_pump is applied to the voltage output terminal.

[0145] It should be noted that the method provided in this embodiment is applied to the charge pump circuit 10 in the foregoing embodiments. For details not disclosed in this embodiment, please refer to the description of the foregoing embodiments for understanding, and will not be repeated here.

[0146] In another embodiment of this disclosure, see [reference needed]. Figure 9 This illustration shows a schematic diagram of the composition structure of a memory provided in an embodiment of this disclosure. For example... Figure 9 As shown, the memory 90 includes the charge pump circuit 10 described in the foregoing embodiments.

[0147] It should be noted that this memory can be a semiconductor memory such as DRAM, or other types of memory; no specific limitation is made here. Because it includes a charge pump circuit 10, its current capability and current efficiency are improved, thus enhancing the performance of the memory 90.

[0148] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0149] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0150] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0151] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0152] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0153] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0154] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A charge pump circuit, characterized in that, The circuit includes a first boost circuit and / or a second boost circuit. The first boost circuit includes a first boost capacitor, and the second boost circuit includes a second boost capacitor. The first plate of the first boost capacitor is connected to a first node, and the first plate of the second boost capacitor is connected to a second node. Both the first and second nodes are coupled to a voltage input terminal and a voltage output terminal, respectively. The second plate of the first boost capacitor receives a first clock signal, and the second plate of the second boost capacitor receives a second clock signal. Wherein: The first boost circuit is used to boost the voltage of the first node charged to the input voltage through the first boost capacitor under the control of the first clock signal, to obtain the output voltage, and to apply the output voltage to the voltage output terminal. The second boost circuit is used to boost the voltage of the second node charged to the input voltage through the second boost capacitor under the control of the second clock signal, to obtain the output voltage, and to apply the output voltage to the voltage output terminal; Wherein, both the first boost capacitor and the second boost capacitor are MOS capacitors, and the gate dielectric layer material of the MOS capacitor includes a high dielectric constant material, and the gate of the MOS capacitor includes a metal gate. The first boost circuit further includes a first switching circuit and a second switching circuit; the second boost circuit further includes a third switching circuit and a fourth switching circuit. The first switching circuit includes a first transistor and a first capacitor; the second switching circuit includes a second transistor; the third switching circuit includes a third transistor and a second capacitor; the fourth switching circuit includes a fourth transistor; wherein: The first terminal of the first transistor and the first terminal of the third transistor are both connected to the voltage input terminal; the second terminal of the first transistor, the first terminal of the second transistor, and the control terminal of the fourth transistor are all connected to the first node; the control terminal of the first transistor is connected to the first plate of the first capacitor, and the second plate of the first capacitor receives a third clock signal; the second terminal of the third transistor, the first terminal of the fourth transistor, and the control terminal of the second transistor are all connected to the second node; the control terminal of the third transistor is connected to the first plate of the second capacitor, and the second plate of the second capacitor receives a fourth clock signal; the second terminal of the second transistor and the second terminal of the fourth transistor are both connected to the voltage output terminal. Both the first boost capacitor and the second boost capacitor are NMOS transistors or PMOS transistors; both the first transistor and the third transistor are NMOS transistors; both the second transistor and the fourth transistor are PMOS transistors; both the first capacitor and the second capacitor are cylindrical capacitors; the gate oxide layer of the first boost capacitor and the gate oxide layer of the second boost capacitor are thinner than the gate oxide layer of the first transistor, the gate oxide layer of the second transistor, the gate oxide layer of the third transistor, and the gate oxide layer of the fourth transistor.

2. The charge pump circuit according to claim 1, characterized in that, The first boost circuit and the second boost circuit are used to alternately boost the voltage of the first node and the second node to obtain the output voltage, and apply the output voltage to the voltage output terminal.

3. The charge pump circuit according to claim 2, characterized in that, The first switching circuit is connected between the voltage input terminal and the first node, and is used to receive the third clock signal and control the first node to charge to the input voltage according to the third clock signal; The second switching circuit is connected between the first node and the voltage output terminal, and is used to connect the first node, which has been boosted to the output voltage, to the voltage output terminal according to the voltage control of the second node; The third switching circuit is connected between the voltage input terminal and the second node, and is used to receive the fourth clock signal and control the second node to charge to the input voltage according to the fourth clock signal; The fourth switching circuit is connected between the second node and the voltage output terminal, and is used to connect the second node, which has been boosted to the output voltage, to the voltage output terminal according to the voltage control of the first node.

4. The charge pump circuit according to claim 1, characterized in that, The rising edge of the second clock signal is earlier than the rising edge of the third clock signal; The rising edge of the third clock signal is earlier than the falling edge of the first clock signal; The falling edge of the first clock signal is earlier than the falling edge of the fourth clock signal; The rising edge of the first clock signal is earlier than the rising edge of the fourth clock signal; The rising edge of the fourth clock signal is earlier than the falling edge of the second clock signal; The falling edge of the second clock signal is earlier than the falling edge of the third clock signal.

5. The charge pump circuit according to claim 1, characterized in that, The charge pump circuit further includes a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit, wherein: The first driving circuit is used to receive a first preset clock signal, perform driving enhancement processing on the first preset clock signal, and obtain the first clock signal. The second driving circuit is used to receive a second preset clock signal, perform driving enhancement processing on the second preset clock signal, and obtain the second clock signal. The third driving circuit is used to receive a third preset clock signal, perform driving enhancement processing on the third preset clock signal, and obtain the third clock signal. The fourth driving circuit is used to receive a fourth preset clock signal, perform driving enhancement processing on the fourth preset clock signal, and obtain the fourth clock signal.

6. The charge pump circuit according to claim 5, characterized in that, The first driving circuit, the second driving circuit, the third driving circuit, and the fourth driving circuit all include an odd number of inverters; and in the first driving circuit and the second driving circuit, the gate dielectric layer material of the transistor in the inverter includes a high dielectric constant material, and the gate of the transistor in the inverter includes a metal gate.

7. The charge pump circuit according to claim 5, characterized in that, The falling edge of the second preset clock signal is earlier than the falling edge of the third preset clock signal; The falling edge of the third preset clock signal is earlier than the rising edge of the first preset clock signal; The rising edge of the first preset clock signal is earlier than the rising edge of the fourth preset clock signal; The falling edge of the first preset clock signal is earlier than the falling edge of the fourth preset clock signal; The falling edge of the fourth preset clock signal is earlier than the rising edge of the second preset clock signal; The rising edge of the second preset clock signal is earlier than the rising edge of the third preset clock signal.

8. The charge pump circuit according to claim 5, characterized in that, The first preset clock signal, the second preset clock signal, the third preset clock signal, and the fourth preset clock signal all have the same duty cycle and the same clock period; The effective voltage levels of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the input voltage.

9. The charge pump circuit according to any one of claims 1 to 8, characterized in that, The charge pump circuit further includes a first protection circuit and a second protection circuit. The first protection circuit includes a first protection transistor and a second protection transistor, and the second protection circuit includes a third protection transistor and a fourth protection transistor; wherein: The control terminal of the first protection transistor is connected to the second node, and the first terminal of the first protection transistor and the control terminal of the second protection transistor are both connected to the first node; the second terminal of the first protection transistor, the first terminal of the second protection transistor, the substrate of the first protection transistor, and the substrate of the second protection transistor are all connected to the substrate of the second transistor; the second terminal of the second protection transistor is connected to the voltage output terminal. The control terminal of the third protection transistor is connected to the first node, and the first terminal of the third protection transistor and the control terminal of the fourth protection transistor are both connected to the second node; the second terminal of the third protection transistor, the first terminal of the fourth protection transistor, the substrate of the third protection transistor, and the substrate of the fourth protection transistor are all connected to the substrate of the fourth transistor; the second terminal of the fourth protection transistor is connected to the voltage output terminal.

10. The charge pump circuit according to claim 9, characterized in that, The first protection transistor, the second protection transistor, the third protection transistor, and the fourth protection transistor are all PMOS transistors.

11. A control method for a charge pump circuit, characterized in that, Applied to a charge pump circuit as described in any one of claims 1 to 10, the method comprises: Charge the first node to the input voltage; and / or charge the second node to the input voltage; Under the control of the first clock signal, the first node charged to the input voltage is boosted through the first boost capacitor to obtain an output voltage, and the output voltage is applied to the voltage output terminal; and / or, under the control of the second clock signal, the second node charged to the input voltage is boosted through the second boost capacitor to obtain an output voltage, and the output voltage is applied to the voltage output terminal.

12. A memory, characterized in that, Includes the charge pump circuit as described in any one of claims 1 to 10.

Images