A CMOS thyristor double edge delay circuit

Abstract

The application provides a CMOS thyristor double-edge delay circuit, which comprises a rising edge extension module and a falling edge extension module, the rising edge extension module comprises two PMOS tubes, five NMPS tubes, a current source Iref1, a capacitor C1 and three inverters, and the falling edge extension module comprises six PMOS tubes, two NMPS tubes, a current source Iref2, a capacitor C2 and four inverters. The application improves signal integrity, reduces power consumption and increases delay range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a CMOS thyristor bilateral delay circuit. Background Technology

[0002] Both digital and analog circuits require control timing adjustments, but current methods, such as rising-edge delay circuits, are insufficient for all scenarios. Existing delay circuits suffer from low waveform integrity; the output waveform differs from the input signal not only in terms of delay but also in other aspects. These differences include glitches, high-frequency pulses, and other noise, as well as non-square waves. However, using these non-square waves as square waves creates dead zones. Furthermore, existing delay circuits, such as inverter chains, RC delay circuits, and differential pair delays, consume significant power, with power consumption directly proportional to the delay time. Summary of the Invention

[0003] The purpose of this invention is to provide a CMOS thyristor bilateral delay circuit that improves signal integrity, reduces power consumption, and increases the delay range.

[0004] To achieve the above objectives, the technical solution adopted by this invention is: a CMOS thyristor bilateral delay circuit, comprising a rising edge extension module and a falling edge extension module. The rising edge extension module includes two PMOS transistors, five NMPS transistors, a current source Iref1, a capacitor C1, and three inverters. The input signal Vin is connected to the gates of MP1, MN4, and MN7, respectively. An inverter is also provided between the input signal Vin and the gate of MN7. The drain of MP1 is connected to the drain of MN4, the source of MN4 is connected to the drain of MN5, and the gate of MN5 is connected to... The gate of MN3 and the drain of MN3 are connected to the negative terminal of the reference current source Iref1. The lower stage board of capacitor C1 is connected to the drain of MN6 and the drain of MP1. The lower stage board of capacitor C1 is connected to the gate of MP2 after passing through two stages of inverters. The drain of MP2 outputs a rising edge delay circuit to output a signal VT, which is connected to the gate of MN6 and the drain of MN7 respectively. The power interface is connected to the source of MP1, the positive terminal of the current source Iref1, the upper stage board of capacitor C1, and the source of MP2 respectively. The ground terminal is connected to the source of MN5, the source of MN3, the source of MN6, and the source of MN7 respectively. The falling edge extension module includes six PMOS transistors, two NMPS transistors, a current source Iref2, a capacitor C2, and four inverters. The rising edge delay circuit output signal VT is connected to the gates of MP10, MN14, and MP12, respectively. An inverter is also provided between the rising edge delay circuit output signal VT and the gate of MP12. The gate and drain of MP8 are connected to the positive terminal of the reference current source Iref2. The gate of MP9 is connected to the gate of MP8, the drain of MP9 is connected to the source of MP10, and the drain of MP10 is connected to the drain of MN14. The drain of MP11 is connected to capacitor C. The upper stage board of 2 and the drain of MN14, the drain of MP12 is connected to the gate of MP11 and the drain of MN15; the upper stage board of capacitor C2 is connected to the gate of MN15 through two stages of inverters; the drain of MP13 outputs the dual-sided delay circuit output signal Vout, which is connected to the gate after passing through an inverter, and the drain of MP13 is connected to the drain of MP12; the power interface is connected to the source of MP8, the source of MP9, the source of MP11, the source of MP12, and the source of MP13 respectively; the ground terminal is connected to the negative terminal of the reference current source Iref2, the source of MN14, the lower stage board of capacitor C2, and the source of MN15 respectively.

[0005] Beneficial effects: This invention extends the rising edge delay circuit to a double-edge delay circuit, transforming single-trigger control within a single clock signal into double-trigger control, thus expanding application functionality. Utilizing a two-stage inverter structure, the voltage across the capacitor is transmitted to the MOSFET gate only at high and low levels, resulting in only two states for the MOSFET: cutoff and saturation. This eliminates the leakage current effect caused by subthreshold states, improving transistor switching speed. The falling edge delay circuit eliminates the charge injection effect of the preceding stage, and a feedback branch composed of MP13 is added to the falling edge delay circuit, allowing redundant charge to be re-injected into the power supply without affecting the output voltage, improving signal accuracy. Compared to inverter chains, RC delay circuits, and differential pair delay circuits, the power consumption of this invention is inversely proportional to the delay time. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the CMOS thyristor bilateral delay circuit of the present invention.

[0007] Figure 2 This is a timing waveform diagram of the circuit of the present invention.

[0008] Figure 3 This is a simulation diagram of the elimination of subthreshold leakage current according to the present invention.

[0009] Figure 4 This is a simulation diagram of the elimination of rising edge charge injection effect according to the present invention.

[0010] Figure 5This is a graph showing the relationship between the control current Iref and the circuit delay time in this invention.

[0011] Figure 6 The diagram shows the circuit delay time of the present invention when Iref is 0.1nA and 10uA respectively.

[0012] Figure 7 This is a simulation diagram of the elimination of rising edge charge injection effect according to the present invention.

[0013] Figure 8 This is a graph showing the relationship between the control current Iref and the average power consumption of the present invention.

[0014] Figure 9 This is a PVT simulation diagram of the bilateral delay circuit of the present invention. Detailed Implementation

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0016] The structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0017] It should be noted that any parts not described in detail in this application are prior art.

[0018] This invention proposes a CMOS thyristor bilateral delay circuit, such as... Figure 1 As shown, its principle is to delay the signal edges separately. The input signal, after being processed by the rising edge delay circuit, serves as the input signal for the next-stage falling edge delay circuit, which then delays the falling edge, ultimately achieving the function of bilateral delay. In this specification and accompanying drawings, MP and MN represent PMOS and NMOS transistors, respectively.

[0019] The specific working process of this circuit is as follows: Figure 2As shown: When the input signal Vin is low, MP1 and MN7 are turned on, and MN4 is turned off. The rising edge delay circuit output signal VT is pulled low through MN7, and MN6 is turned off. The lower-level board voltage Vcap1 of capacitor C1 is charged to VDD through MP1, while MP2 is turned off, completing the pre-charging process of capacitor C1. When VT is low, MP10 is turned on, and MN14 and MP12 are turned off. The upper-level board voltage Vcap2 of capacitor C2 is charged to VDD through the MP10 and MP9 circuit. When Vcap2 increases to the threshold voltage VTHn of the NMOS transistor, Vcap2 is calibrated to a high level through two stages of inverters, that is, Vcap2 will have a low-level jump to a high level, turning on MN15, thereby pulling the circuit output signal Vout low. The time it takes for Vcap2 to gradually rise from GND to the threshold voltage VTHn is... This is the falling edge delay time. When the input signal Vin changes from low to high, MN4 is turned on, and MP1 and MN7 are turned off. The lower-level board voltage Vcap1 of capacitor C0 discharges with the current replicated by the current mirror formed by MN3 and MN5. The smaller the current, the slower the discharge speed and the linear change. When Vcap1 drops to less than the threshold voltage VTHp of the PMOS transistor, Vcap1 is calibrated through two stages of inverters, making Vcal1 low. MP2 is turned on, making the rising edge delay circuit output signal VT high. The time for Vcap1 to discharge from VDD to VTHp is the rising edge delay time. When the VT signal is high, MP10 is turned off, and MN14 is turned on, providing a discharge path for capacitor C2, making Vcap2 low. At the same time, Vcal2 will also become low, turning off MN15. MP12 is turned on, directly pulling the bilateral delay circuit output signal Vout high.

[0020] This circuit aims to improve signal integrity, reduce power consumption, and increase delay range. Two optimizations are made to the bilateral delay circuit: eliminating the additional power consumption caused by subthreshold leakage current and eliminating waveform distortion caused by charge injection effects.

[0021] 1. Eliminating Subthreshold Current: Two inverters are added between MP2, MN15, and the capacitor to eliminate subthreshold leakage current on the rising and falling edges, respectively. The principle is the same for both; the following analysis uses the elimination of rising-edge subthreshold leakage current as an example. The effect of capacitor charging and discharging on the conduction of MP2 is canceled out by the two inverters, thus preventing subthreshold current from flowing through the source and drain of MP2 when the gate is in a high input state. When VCAP1 is less than the inverter's reversing voltage as the capacitor discharges, the inverter shapes Vcap and transmits it to the MP2 gate, ensuring that MP2 remains in the off state during capacitor discharge and does not generate subthreshold current. The final result is as follows... Figure 3 The output waveform is shown.

[0022] 2. Eliminate charge injection effect; because when Vin changes from low to high, the MN7 transistor changes from on to off, which will trigger a charge injection effect, causing the VT signal waveform to be distorted. Figure 4 The VT waveform is shown in the diagram. To maintain signal integrity and address the charge injection effect of the VT signal, the VT signal is used as the input signal of the falling edge circuit. The next stage circuit then shapes the waveform of the previous stage circuit. During the charge injection effect phase, Vcap2 is at a high potential, which turns on MN15 and pulls the output Vout signal to GND. This results in the output signal being a delay of the original input signal, thus eliminating the influence of the charge injection effect.

[0023] In a falling-edge delay circuit, the on / off state of MP12 also produces a charge injection effect, such as... Figure 5 As shown in the Voutb waveform, this paper addresses this by adding a PMOS transistor in parallel with MP12, with the gate input being the inverted Vout signal. When MP12 is turned off, the generated charge flows back to the power supply through MP13, thus eliminating the charge injection effect. The final optimized waveform is shown below. Figure 4 , 5 As shown in Vout.

[0024] This invention employs SMIC 0.18μm standard CMOS technology to complete the overall bilateral delay circuit design. Under experimental conditions of low supply voltage (0.9V), equal control currents for both sides of the bilateral delay circuit, temperature (25℃), and standard process angle tt, the circuit was simulated and verified using the commercial IC design tool Cadence.

[0025] like Figure 6 As shown, changing the magnitude of the control current Iref controls the charging and discharging time of the capacitor, thereby altering the delay. By varying Iref from 5nA to 100nA, the delay time of the bilateral delay circuit gradually decreases from 176µs to 10µs. Within the Iref range of 5nA to 100nA, a delay time variation of 166µs can be achieved. This circuit can expand the magnitude of Iref to achieve larger or smaller delays. Simulation results demonstrate this. Figure 7 As shown, the circuit delay is 614µs when Iref is 0.1nA and 18.5ns when Iref is 10µA. The circuit proposed in this paper can achieve a delay in the range of 18.5ns to 614µs, and the delay time is still adjustable. Changing the capacitor value or adjusting Iref can meet the application requirements of digital circuits or communication fields.

[0026] Figure 8The relationship between the average power consumption of the proposed bilateral delay circuit and Iref is shown. As Iref gradually increases, the average power consumption also gradually increases. When Iref is between 0.1nA and 10nA, the average power consumption of the circuit remains relatively constant at 13.2nW. Afterward, with further increases in Iref, the average power consumption increases linearly, reaching 84.29nW when Iref is 100nA. The power consumption of this circuit is in the nW range, meeting the requirements for low-power, long standby applications.

[0027] Figure 9 PVT simulations were performed on the bilateral delay circuit with an Iref of 100nA. The circuit was tested at three process corners (tt, ss, and ff) and temperatures ranging from -45℃ to 75℃. At the ff process corner and 75℃, the minimum delay time was 167µs; at the ss process corner and -45℃, the maximum delay time was 185.78µs. The maximum delay variation error with changing PVT was 18.78µs.

[0028] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should be covered within the protection scope of the present invention.

Claims

1. A CMOS thyristor bilateral delay circuit, characterized in that: It includes a rising edge extension module and a falling edge extension module. The rising edge extension module includes two PMOS transistors, five NMPS transistors, a current source Iref1, a capacitor C1, and three inverters. The input signal Vin is connected to the gates of MP1, MN4, and MN7, respectively. An inverter is also provided between the input signal Vin and the gate of MN7. The drain of MP1 is connected to the drain of MN4, the source of MN4 is connected to the drain of MN5, the gate of MN5 is connected to the gate of MN3, and the drain of MN3 is connected to its gate. Connect the negative terminal of the reference current source Iref1; the lower stage board of capacitor C1 is connected to the drain of MN6 and the drain of MP1. The lower stage board of capacitor C1 is connected to the gate of MP2 after passing through two stages of inverters. The rising edge delay circuit outputs the signal VT from the drain of MP2 and connects to the gate of MN6 and the drain of MN7 respectively; the power interface is connected to the source of MP1, the positive terminal of current source Iref1, the upper stage board of capacitor C1, and the source of MP2 respectively; the ground terminal is connected to the source of MN5, the source of MN3, the source of MN6, and the source of MN7 respectively. The falling edge extension module includes six PMOS transistors, two NMPS transistors, a current source Iref2, a capacitor C2, and four inverters. The rising edge delay circuit output signal VT is connected to the gates of MP10, MN14, and MP12, respectively. An inverter is also provided between the rising edge delay circuit output signal VT and the gate of MP12. The gate and drain of MP8 are connected to the positive terminal of the reference current source Iref2. The gate of MP9 is connected to the gate of MP8. The drain of MP9 is connected to the source of MP10. The drain of MP10 is connected to the drain of MN14. The drain of MP11 is connected to the upper stage of capacitor C2 and the drain of MN14. The drain of MP12 is connected to the gate of MP11 and the drain of MN15. The upper stage of capacitor C2 is connected to the gate of MN15 through two stages of inverters. The drain of MP13 outputs the dual-sided delay circuit output signal Vout, which is connected to the gate after passing through an inverter. The drain of MP13 is connected to the drain of MP12. The power interfaces are connected to the sources of MP8, MP9, MP11, MP12, and MP13, respectively; the ground terminals are connected to the negative terminal of the reference current source Iref2, the source of MN14, the lower stage board of capacitor C2, and the source of MN15, respectively.

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