Multi-chip system with synchronization module and applicable phase-locked loop circuit

Abstract

A synchronization module includes a first digital circuit, a second digital circuit, and a phase-locked loop circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The phase-locked loop circuit is coupled between the first digital circuit and the second digital circuit. The phase-locked loop circuit includes a delay coupled between a phase frequency detector and a frequency divider. The delay outputs an output signal of the frequency divider to the phase frequency detector after a delay compensation. The delay compensation is based on at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.

Description

Technical Field

[0001] This invention relates to a synchronization module, a multi-chip system, and a suitable phase-locked loop circuit; particularly to a synchronization module, a multi-chip system, and a suitable phase-locked loop circuit with delay compensation. Background Technology

[0002] As products evolve, the complexity and scale of their internal systems also increase. To minimize errors between systems, the efficiency of clock synchronization is crucial. This is especially true in multi-chip systems, where differences in manufacturing processes or circuitry can lead to clock asynchrony even when using the same reference clock. This also limits system expansion and integration.

[0003] In view of this, overcoming the lack of clock synchronization caused by differences in process or other design between chips / subsystems in multi-chip systems (e.g., temperature or wiring) will be a key factor in the development of products in this field. Summary of the Invention

[0004] This invention provides a synchronization module comprising a first digital circuit, a second digital circuit, and a phase-locked loop (PLL) circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The PLL circuit is coupled between the first digital circuit and the second digital circuit. The PLL circuit includes a delay unit coupled between a phase-frequency detector and a frequency divider. The delay unit performs a delay compensation on an output signal from the frequency divider before outputting it to the phase-frequency detector. The delay compensation is based at least on one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.

[0005] In one embodiment, the delayer is a digitally controlled delayer (DCDL).

[0006] In one embodiment, the delay device receives a control signal to adjust the delay compensation.

[0007] In one embodiment, a delay detector is further included, coupled between the first digital circuit and the second digital circuit, and provides the control signal to the delay unit according to the input clock signal and the output clock signal.

[0008] In one embodiment, the second digital circuit further includes a clock-controlled switch configured to receive a synchronous gate signal.

[0009] This invention provides a multi-chip system comprising a reference clock module and multiple chip modules. Each chip module includes a first digital circuit, a second digital circuit, and a phase-locked loop (PLL) circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The PLL circuit is coupled between the first digital circuit and the second digital circuit. The PLL circuit includes a delay unit coupled between a phase-frequency detector and a frequency divider. The delay unit performs a delay compensation on an output signal from the frequency divider before outputting it to the phase-frequency detector. The delay compensation is based at least on one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.

[0010] In one embodiment, the delayers are digitally controlled delayers.

[0011] In one embodiment, the delay units each receive a control signal to adjust the corresponding delay compensation.

[0012] In one embodiment, the multi-chip system further includes an inter-chip delay detector coupled to the chip modules, which provides control signals to the delay units according to the output clock signals of the chip modules.

[0013] In one embodiment, the chip modules each include a clock-controlled switch configured to receive a synchronous gate signal.

[0014] This invention provides a phase-locked loop circuit comprising a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), a frequency divider, and a delay unit. The phase frequency detector is configured to receive an input signal. The charge pump is coupled to the phase frequency detector. The loop filter is coupled to the charge pump. The VCO is coupled to the loop filter and configured to output an output signal. The frequency divider is coupled to the VCO and configured to perform frequency division processing on the output signal to output a divided signal. The delay unit is coupled to the frequency divider and the phase frequency detector and configured to perform delay compensation on the divided signal before outputting it to the phase frequency detector.

[0015] As described above, delay compensation is provided by the delay unit coupled between the phase frequency detector and the frequency divider in the phase-locked loop circuit to eliminate timing asynchrony problems between clock input and output caused by hardware differences. Attached Figure Description

[0016] Figure 1 This is an example block diagram of a synchronization module in one embodiment of the present invention.

[0017] Figure 2A This is an example block diagram of a phase-locked loop circuit in one embodiment of the present invention.

[0018] Figure 2B for Figure 2A Example clock signals for each node.

[0019] Figure 3 This is an example block diagram of a synchronization module with a delay detector in one embodiment of the present invention.

[0020] Figure 4 This is an example block diagram of a synchronization module with a clock gate switch, as described in one embodiment of the present invention.

[0021] Figure 5 This is an example block diagram of a multi-chip system in one embodiment of the present invention.

[0022] Figure 6 This is an example block diagram of an inter-chip delay detector in one embodiment of the present invention.

[0023] Figure 7 This is an example block diagram of a multi-chip system with a clock gate switch, as described in one embodiment of the present invention.

[0024] Explanation of key component symbols:

[0025] 100 Synchronization Module

[0026] 110 First Digital Circuit

[0027] 120 Second Digital Circuit

[0028] 121 Clock gate switch

[0029] 130 Phase-locked Loop Circuit

[0030] 131 Phase Frequency Detector

[0031] 132 frequency divider

[0032] 133 Delay Unit

[0033] 134 Charge Pump

[0034] 135-loop filter

[0035] 136 Voltage-Controlled Oscillator

[0036] 140 Delay Detector

[0037] 200+ chip system

[0038] 210 Reference Clock Module

[0039] 221, 222, 223, 224 Chip Modules

[0040] 230 Inter-chip Delay Detector

[0041] 2211, 2221, 2231, 2241 Clock gate switch

[0042] Nodes A, B, C, D

[0043] cki input clock signal

[0044] cko output clock signal

[0045] Cn control signal

[0046] sys synchronous gate control signal Detailed Implementation

[0047] The spirit of the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. Any person skilled in the art, after understanding the embodiments of the present invention, can make changes and modifications based on the techniques taught in the present invention without departing from the spirit and scope of the present invention.

[0048] The terms "first," "second," etc., used herein are not intended to specifically refer to any order or sequence, nor are they intended to limit the invention; they are merely used to distinguish elements or operations described using the same technical terms. The terms "comprising," "including," "having," "containing," etc., used herein are open-ended terms, meaning that they include, but are not limited to, these terms.

[0049] Unless otherwise specified, the terms used herein generally have their ordinary meaning in the context of this art, the disclosure, and the specific content. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.

[0050] In the accompanying drawings, the thickness of layers, plates, regions, or spaces is enlarged for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, plate, region, or space is referred to as being "on" or "connected to" another element, it can be interpreted as being directly on or connected to the other element, or as having or having an intermediate element between the element and the other element. As used herein, "connection" or "coupling" can refer to physical and / or electrical connections. Furthermore, to simplify the drawings and highlight their intended presentation, existing structures or elements in the drawings may be depicted schematically or omitted.

[0051] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral, used to differentiate between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, without regard to the second reference numeral or other subsequent reference numerals.

[0052] like Figure 1 As shown, a synchronization module 100 includes a first digital circuit 110, a second digital circuit 120, and a phase-locked loop (PLL) circuit 130. The first digital circuit 110 is configured to receive an input clock signal cki. The second digital circuit 120 is configured to output an output clock signal cko. The PLL circuit 130 is coupled between the first digital circuit 110 and the second digital circuit 120. The PLL circuit 130 includes a delay unit 133 coupled between a phase frequency detector 131 and a frequency divider 132. The delay unit 133 outputs the output signal Do from the frequency divider 132 after delay compensation (i.e., the delayed signal Do') to the phase frequency detector 131. The delay compensation is based at least on one of a first delay time of the first digital circuit 110 and a second delay time of the second digital circuit 120.

[0053] Specifically, the first digital circuit 110 is coupled to the input side of the phase-locked loop circuit 130 (e.g., the input terminal of the phase-frequency detector 131). The first digital circuit 110 receives the input clock signal cki and outputs it to the input terminal of the phase-frequency detector 131 of the phase-locked loop circuit 130. The input clock signal cki will experience a slight delay (i.e., a first delay time) after passing through the first digital circuit 110. On the other hand, the second digital circuit 120 is coupled to the output side of the phase-locked loop circuit 130 (e.g., the output terminal of the voltage-controlled oscillator 136). The second digital circuit 120 receives the output of the phase-locked loop circuit 130 and outputs the output clock signal cko after a slight delay (i.e., a second delay time). It should be noted that the values ​​and / or lengths of the first delay time of the first digital circuit 110 and the second delay time of the second digital circuit 120 may vary due to differences in process, temperature, and / or path.

[0054] like Figure 2A As shown, the phase-locked loop circuit 130 may include, for example, a phase frequency detector 131, a charge pump 134, a loop filter 135, a voltage-controlled oscillator 136, a frequency divider 132, and a delay unit 133. The charge pump 134 is coupled to the phase frequency detector 131 (at... Figure 2AIn this embodiment, the charge pump 134 may be integrated with the phase-frequency detector 131. A loop filter 135 is coupled to the charge pump 134. A voltage-controlled oscillator 136 is coupled to the loop filter 135. A frequency divider 132 is coupled to the voltage-controlled oscillator 136 and configured to perform frequency division processing on the output signal of the voltage-controlled oscillator 136 to output a frequency-divided signal (i.e., output signal Do). A delay unit 133 is coupled to the frequency divider 132 and the phase-frequency detector 131 and configured to perform delay compensation on the output signal Do of the frequency divider 132 before outputting it to the phase-frequency detector 131. In one embodiment, the delay unit 133 is preferably a digitally controlled delay unit (DCDL). It should be noted that the components and / or configurations described in the above-described phase-locked loop circuit 130 are merely examples and are not intended to limit the invention. Any conventional circuit adjustments made by those skilled in the art should fall within the scope of this invention.

[0055] like Figure 2B As shown, Figure 2B for Figure 2A The diagram shows example clock signals for each node of the phase-locked loop circuit 130. Node A is the input clock signal cki delayed by a first delay time td1 after passing through the first digital circuit 110. Node B is the signal after delay compensation CMP by delay unit 133 after passing through node C. Node C is the signal after frequency divider 132 after passing through node D. It should be noted that... Figure 2B The frequency division values ​​shown are merely examples and are not intended to limit the invention. Node D is the signal output by the voltage-controlled oscillator 136. The output clock signal cko is the signal from node D delayed by a second delay time td2 after passing through the second digital circuit 120. It should be noted that... Figure 2B The CMP (Current Performance Compensation) values ​​shown are merely examples. The CMP values ​​can be based on at least one of the first delay time td1 and the second delay time td2. For example, one can compensate for either the first delay time td1 or the second delay time td2 alone. Alternatively, a suitable compensation value can be selected after simulation based on both the first delay time td1 and the second delay time td2.

[0056] In one embodiment, the delay unit 133 can receive a control signal Cn to adjust the value of the delay compensation. In this embodiment, the control signal Cn can be a digital signal. For example, after storing the digital control signal Cn in a register (which can be written to the register in advance or adjusted according to the actual situation before being written), the delay unit 133 reads the control signal Cn from the register. In one embodiment, the control signal Cn can be provided by any controller (e.g., a microprocessor, FPGA, etc.). Figure 3As shown, the synchronization module 100 also includes a delay detector 140 coupled between the first digital circuit 110 and the second digital circuit 120, and provides a control signal Cn to the delay unit 133 based on the input clock signal cki and the output clock signal cko. Specifically, the delay detector 140 can determine the required delay compensation CMP value based on the asynchrony and / or delay between the input clock signal cki and the output clock signal cko, and generate a control signal Cn according to the value of the delay compensation CMP and output it to the delay unit 133. The delay unit 133 can change its own delay parameters according to the control signal Cn to achieve the required delay compensation CMP. In this way, the value of the delay compensation CMP can be dynamically adjusted according to the line conditions or component conditions.

[0057] In one embodiment, such as Figure 4 As shown, the second digital circuit 120 of the synchronization module 100 also includes a clock gate switch 121 configured to receive a synchronization gate signal sys. Specifically, the synchronization gate signal sys can be a clock signal different from the input clock signal cki (e.g., an external clock). The clock gate switch 121 can control the second digital circuit 120 to output an output clock signal cki based on the synchronization gate signal sys. For example, when the synchronization gate signal sys is high (digit 1), the second digital circuit 120 can output the output clock signal cki. Conversely, when the synchronization gate signal sys is low (digit 0), the second digital circuit 120 cannot output the output clock signal cki. The synchronization of the synchronization module 100 can be made more precise by using the synchronization gate signal sys and the clock gate switch 121. Specifically, when there are many systems that need to be synchronized (e.g., a multi-chip system), the synchronization gate signal sys and the clock gate switch 121 are used as coarse adjustments to ensure that each chip in the multi-chip system can operate within approximately the same clock interval. At this point, fine-tuning can be performed using the phase-locked loop circuit 130 with delay unit 133, thereby making the synchronization of the synchronization module 100 more accurate. It should be noted that the configuration of the clock gate switch 121 described above is merely an example and does not limit the invention. The clock gate switch 121 can also be placed at any appropriate node position in the synchronization module 100.

[0058] In one embodiment, such as Figure 5 As shown, Figure 5A multi-chip system 200 is described, comprising a reference clock module 210 and multiple chip modules 221-224. Each of the chip modules 221-224 includes a first digital circuit 110, a second digital circuit 120, and a phase-locked loop (PLL) circuit 130, as described in the synchronization module 100. The first digital circuit 110 is configured to receive the input clock signal cki generated by the reference clock module 210. The second digital circuit 120 is configured to output clock signals cko1-cko4. Synchronization between the output clock signals cko1-cko4 is thus achieved through the PLL circuits 130 of each of the chip modules 221-224.

[0059] Specifically, the clock inputs of chip modules 221-224 are all the input clock signal cki generated by reference clock module 210. However, due to hardware differences such as process technology or circuitry (e.g., the delays generated by the first and / or second digital circuits of each chip module 221-224 are not the same), differences (i.e., asynchrony) occur between the output clock signals cko1-cko4 of chip modules 221-224. The phase-locked loop circuits of each chip module 221-224 can perform delay compensation based on the delays of their respective first and / or second digital circuits through their delay units, thereby achieving clock synchronization among chip modules 221-224. For example, the phase-locked loop circuit of chip module 221 can have a first delay compensation, the value of which is determined based on the delays of the first and / or second digital circuits of chip module 221. On the other hand, the phase-locked loop circuit of chip module 222 can have a second delay compensation, the value of which is determined based on the delays of the first and / or second digital circuits of chip module 222. The value of the first delay compensation may be the same as or different from the value of the second delay compensation, and can be adjusted according to the actual situation. In one embodiment, the delay units of each of the chip modules 221-224 can also receive different control signals to adjust the corresponding delay compensation values. For example, the delay unit in chip module 221 that generates the first delay compensation can receive the first control signal; the delay unit in chip module 222 that generates the second delay compensation can receive the second control signal. It should be noted that the present invention is not limited to... Figure 5 The number of chip modules can be adjusted by those skilled in the art based on actual needs.

[0060] On the other hand, such as Figure 6As shown, the multi-chip system 200 may include an inter-chip delay detector 230 coupled between chip modules 221-224. The inter-chip delay detector 230 provides control signals Cn1-Cn4 to the corresponding delay units based on the output clock signals cko1-cko4 of the chip modules 221-224. Specifically, the output clock signals cko1-cko4 may correspond to the input clock signal cki generated by the reference clock module 210, and the inter-chip delay detector 230 can determine the difference or asynchrony ratio between the output clock signals cko1-cko4 and the input clock signal cki. Therefore, it provides control signals Cn1-Cn4 to the corresponding delay units to adjust the delay compensation values. For example, control signal Cn1 is provided to the delay unit of chip module 221 to adjust the first delay compensation value; control signal Cn2 is provided to the delay unit of chip module 221 to adjust the second delay compensation value. This achieves clock synchronization between chip modules 221-224. It should be noted that the control signals Cn1-Cn4 can also be determined through simulation or relevant process parameters.

[0061] In one embodiment, such as Figure 7 As shown, chip modules 221-224 may each include clock gate switches 2211-2241 configured to receive a synchronization gate signal sys. Specifically, clock gate switches 2211-2241 can control the input or output of clock signals of chip modules 221-224 based on the synchronization gate signal sys. For example, when clock gate switches 2211-2241 are configured in the second digital circuits of each of chip modules 221-224, when the synchronization gate signal sys is high (digit 1), the second digital circuit can output clock signals cko1-cko4. Conversely, when the synchronization gate signal sys is low (digit 0), the second digital circuit cannot output clock signals cko1-cko4. On the other hand, when clock gate switches 2211-2241 are configured in the first digital circuits of each of the chip modules 221-224, when the synchronization gate signal sys is high (digit 1), the chip modules 221-224 can receive the input clock signal cki; when the synchronization gate signal sys is low (digit 0), the chip modules 221-224 cannot receive the input clock signal cki. The synchronization gate signal sys and the clock gate switches 2211-2241 enable more precise clock synchronization among the chip modules 221-224 of the multi-chip system 200.

[0062] The present invention has been described by the above-described embodiments; however, these embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the present invention. Conversely, modifications and equivalents encompassing the spirit and scope of the claims are all included within the scope of the present invention.

Claims

1. A synchronization module, characterized in that, Include: A first digital circuit is configured to receive an input clock signal; A second digital circuit, configured to output an output clock signal; and A phase-locked loop circuit, coupled between the first digital circuit and the second digital circuit, includes: A delay unit is coupled between a phase frequency detector and a frequency divider. The delay unit performs a delay compensation on an output signal of the frequency divider and outputs it to the phase frequency detector. The delay compensation is based on at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit; The second digital circuit is coupled to an output terminal of the phase-locked loop circuit, and the output terminal is an output of a voltage-controlled oscillator in the phase-locked loop circuit.

2. The synchronization module as described in claim 1, characterized in that, This delay unit is a digitally controlled delay unit.

3. The synchronization module as described in claim 1, characterized in that, The delay unit receives a control signal to adjust the delay compensation.

4. The synchronization module as described in claim 3, characterized in that, Also includes: A delay detector is coupled between the first digital circuit and the second digital circuit, and provides the control signal to the delay unit based on the input clock signal and the output clock signal.

5. The synchronization module as described in claim 1, characterized in that, The second digital circuit also includes a clock-controlled switch configured to receive a synchronous gate signal.

6. A multi-chip system, characterized in that, Include: A reference clock module is configured to generate an input clock signal; as well as Multiple chip modules; Each of the plurality of chip modules includes: A first digital circuit is configured to receive the input clock signal; A second digital circuit, configured to output an output clock signal; and A phase-locked loop circuit, coupled between the first digital circuit and the second digital circuit, includes: A delay unit is coupled between a phase frequency detector and a frequency divider. The delay unit performs a delay compensation on an output signal of the frequency divider and outputs it to the phase frequency detector. The delay compensation is based on at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit; The second digital circuit is coupled to an output terminal of the phase-locked loop circuit, and the output terminal is an output of a voltage-controlled oscillator in the phase-locked loop circuit.

7. The multi-chip system as described in claim 6, characterized in that, These delayers are digitally controlled delayers.

8. The multi-chip system as described in claim 6, characterized in that, Each of these delay units receives a control signal to adjust the corresponding delay compensation.

9. The multi-chip system as described in claim 8, characterized in that, This multi-chip system also includes: An inter-chip delay detector is coupled to the chip modules. The inter-chip delay detector provides control signals to the delay units respectively based on the output clock signals of the chip modules.

10. The multi-chip system as described in claim 6, characterized in that, Each of these chip modules includes a clock-controlled switch configured to receive a synchronous gate control signal.

Images