Fault tolerant synchronous clock transmission system

CN116961866BActive Publication Date: 2026-09-18NOREL SYSTEMS LIMITED
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Patent Information

Application Number
CN202310754895.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-06-26
Publication Date
2026-09-18
Estimated Expiration
2043-06-26

AI Technical Summary

Technical Problem

[0005]在车载串行数据传输系统中,由于车内环境可能存在噪声干扰,同步头可能出现误码情况,若同步头因误码被漏检,有可能引起时钟恢复错误

Benefits of technology

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

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Abstract

The application discloses a fault-tolerant synchronous clock transmission system, which comprises a first transmission terminal, a second transmission terminal and a first transmission channel, the first transmission terminal is connected with the second transmission terminal through the first transmission channel, the first transmission terminal sends a first transmission frame to the second transmission terminal through the first transmission channel at a preset time interval, the first transmission frame contains a first synchronization header, the second transmission terminal uses the position of the received first synchronization header to generate a local clock through clock recovery, the first synchronization header is composed of n1 start symbols, n1>=3, the start symbols are coded through line coding, the second transmission terminal uses the received start symbols to determine the position of the first synchronization header, and when at most two start symbols are wrong in the n1 start symbols, the second transmission terminal can still use the received start symbols to determine the position of the first synchronization header where the start symbols are located.
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Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a fault-tolerant synchronous clock transmission system. Background Technology

[0002] In serial data transmission systems, to save on wiring, communication lines often lack a dedicated clock line for transmitting clock signals. To ensure correct data reception at the receiving end, a common method is to encode the data using line codes before transmission. Line coding increases the transitions between transmitted data bits. At the receiving end, a clock and data recovery circuit reconstructs the clock for data sampling. This method is used in transmission protocols such as PCIe, USB 3.0, and DisplayPort. This method requires continuous, uninterrupted data transmission; otherwise, the clock recovery process will be interrupted, leading to errors in the received data.

[0003] In another type of time-division transmission system based on time slices, such as in common in-vehicle audio transmission systems, time-division transmission is often used to transmit audio data. Each time slice transmits one or more audio sample points, and the system does not transmit data between time slices. In other words, the clock recovery circuit cannot rely on the continuous transmission of data.

[0004] To perform clock recovery, the transmitting end can add a special character as a synchronization header before the data of a time slice. After receiving the synchronization header, the receiving end can use the synchronization header position to perform clock recovery and generate a local clock. The synchronization header position is the time after the receiving end receives the last bit of the synchronization header. The receiving end uses the generated local clock to sample the data, thereby achieving the purpose of correctly receiving the data.

[0005] In vehicle-mounted serial data transmission systems, noise interference may occur in the vehicle interior environment, which may cause bit errors in the synchronization header. If the synchronization header is missed due to bit errors, it may cause clock recovery errors.

[0006] Currently, there is a lack of a method that can both recover the clock from the received sync header position and ensure that the sync header position detection is unaffected by sync header errors. Summary of the Invention

[0007] The technical problem to be solved by the present invention is how to recover the clock from the received synchronization header position, while the synchronization header position detection is not affected by synchronization header errors.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: As a fault-tolerant synchronous clock transmission system of the present invention, it includes a first transmission terminal, a second transmission terminal, and a first transmission channel. The first transmission terminal is connected to the second transmission terminal through the first transmission channel. The first transmission terminal sends a first transmission frame to the second transmission terminal through the first transmission channel at a preset time interval. The first transmission frame includes a first synchronization header. The second transmission terminal uses the received position of the first synchronization header to perform clock recovery and generate a local clock. The first synchronization header consists of n1 start symbols, where n1≥3. The start symbols are encoded using line codes. The second transmission terminal uses the received start symbols to determine the position of the first synchronization header. Among the n1 start symbols, when at most two start symbols are erroneous, the second transmission terminal can still use the received start symbols to determine its position in the first synchronization header.

[0009] The n1 start symbols contain at least 3 unique K codes.

[0010] The three unique K codes are K1, K2, and K3, and the three K codes are all different; or, the three unique K codes are K1, K1, and K1, and the three K codes are the same, and n1≥4, in addition to the three unique K codes, the n1 start symbols also include D code D1, and D1 is not the first or last start symbol in the first synchronization header; or, the three unique K codes are K1, K1, and K2, two K1 codes are the same, and K1 and K2 are different, and n1≥4, in addition to the three unique K codes, the n1 start symbols also include D code D1; or, the three unique K codes are K1, K1, and K1, and the three K codes are the same, and n1≥5, in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 and D2 are different.

[0011] Preferably, the first transmission frame further includes a first data field for transmitting data.

[0012] Preferably, the synchronous clock transmission system further includes a second transmission channel and a third transmission terminal. The second transmission channel is connected to the second transmission terminal. The second transmission terminal sends a second transmission frame to the third transmission terminal through the second transmission channel. The second transmission frame includes a second synchronization header, which is synchronized with the first synchronization header. The third transmission terminal uses the received position of the second synchronization header to perform clock recovery and generate a local clock. The second synchronization header consists of n² start symbols, where n² ≥ 3. The start symbols are encoded using line codes. The third transmission terminal uses the received start symbols to determine the position of the second synchronization header. Among the n² start symbols, if at most two start symbols are incorrect, the third transmission terminal can still use the received start symbols to determine its position in the second synchronization header.

[0013] The n2 start symbols contain at least 3 unique K codes.

[0014] The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, K1, and the three K codes are the same. The n2 ≥ 4, in addition to the three unique K codes, the n2 start symbols also include the D code D1, and D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n2 ≥ 4, in addition to the three unique K codes, the n2 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, K1, and the three K codes are the same. The n2 ≥ 5, in addition to the three unique K codes, the n2 start symbols also include D codes D1 and D2, and D1 and D2 are different.

[0015] Preferably, the second transmission frame further includes a second data field for transmitting data.

[0016] Preferably, the second transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

[0017] Preferably, the line code is encoded in 8b / 10b encoding.

[0018] Preferably, the line code is 9b / 10b encoded.

[0019] As a transmission terminal of the present invention, it is connected to a first transmission channel. The transmission terminal receives a first transmission frame transmitted at a preset time interval from the first transmission channel. The first transmission frame includes a first synchronization header. The transmission terminal uses the received position of the first synchronization header to perform clock recovery and generate a local clock. The first synchronization header consists of n1 start symbols, where n1≥3. The start symbols are encoded by line code. The transmission terminal uses the received start symbols to determine the position of the first synchronization header. Among the n1 start symbols, when at most two start symbols are incorrect, the transmission terminal can still use the received start symbols to determine its position in the first synchronization header.

[0020] The n1 start symbols contain at least 3 unique K codes.

[0021] The three unique K codes are K1, K2, and K3, and the three K codes are all different; or, the three unique K codes are K1, K1, and K1, and the three K codes are the same, and n1≥4, in addition to the three unique K codes, the n1 start symbols also include D code D1, and D1 is not the first or last start symbol in the first synchronization header; or, the three unique K codes are K1, K1, and K2, two K1 codes are the same, and K1 and K2 are different, and n1≥4, in addition to the three unique K codes, the n1 start symbols also include D code D1; or, the three unique K codes are K1, K1, and K1, and the three K codes are the same, and n1≥5, in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 and D2 are different.

[0022] Preferably, the first transmission frame further includes a first data field for transmitting data.

[0023] Preferably, the transmission terminal is further connected to a second transmission channel, through which the transmission terminal sends a second transmission frame. The second transmission frame includes a second synchronization header, which consists of n² start characters, where n² ≥ 3. Preferably, the start symbol is encoded with a line code, the second synchronization head is synchronized with the first synchronization head, the terminal receiving the second synchronization head uses the received position of the second synchronization head to perform clock recovery and generate a local clock, the terminal receiving the second synchronization head uses the received start symbol to determine the position of the second synchronization head, and when at most two start symbols in the n2 start symbols of the second synchronization head are incorrect, the terminal receiving the second synchronization head can still use the received start symbol to determine its position in the second synchronization head.

[0024] The n2 start symbols contain at least 3 unique K codes.

[0025] The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, K1, and the three K codes are the same. The n2 ≥ 4, in addition to the three unique K codes, the n2 start symbols also include the D code D1, and D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n2 ≥ 4, in addition to the three unique K codes, the n2 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, K1, and the three K codes are the same. The n2 ≥ 5, in addition to the three unique K codes, the n2 start symbols also include D codes D1 and D2, and D1 and D2 are different.

[0026] Preferably, the second transmission frame further includes a second data field for transmitting data.

[0027] Preferably, the transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

[0028] Preferably, the line code is encoded in 8b / 10b encoding.

[0029] Preferably, the line code is 9b / 10b encoded. Attached Figure Description

[0030] Figure 1 This is a block diagram of a fault-tolerant synchronous clock transmission system according to the present invention; Figure 2 This is a schematic diagram of a first transmission terminal sending a first transmission frame in a fault-tolerant synchronous clock transmission system of the present invention. Figure 3 This is a structural diagram of the first transmission frame and a schematic diagram of the position of the first synchronization header in a fault-tolerant synchronous clock transmission system of the present invention. Figure 4 This is a schematic diagram of a type of synchronization header in a fault-tolerant synchronous clock transmission system of the present invention; Figure 5 This is a schematic diagram of another type of synchronization head in a fault-tolerant synchronous clock transmission system of the present invention; Figure 6 This is a schematic diagram of another type of synchronization head in a fault-tolerant synchronous clock transmission system of the present invention; Figure 7 This is a schematic diagram of another type of synchronization head in a fault-tolerant synchronous clock transmission system of the present invention; Figure 8 This is a block diagram of another fault-tolerant synchronous clock transmission system of the present invention.

[0031] Figure 9 This is a schematic diagram of a first transmission terminal sending a first transmission frame and a second transmission terminal sending a second transmission frame in another fault-tolerant synchronous clock transmission system of the present invention. Figure 10 This is a block diagram of another fault-tolerant synchronous clock transmission system of the present invention.

[0032] in: 1 First transmission terminal 2 Second transmission terminal 3 First transmission channel 4 Third transmission terminal 5 Second transmission channel Detailed Implementation

[0033] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] like Figure 1 As shown, in one application embodiment of the present invention, as a fault-tolerant synchronous clock transmission system of the present invention, it is used to transmit a synchronous clock. The transmission system includes a first transmission terminal 1, a second transmission terminal 2, and a first transmission channel 3. The first transmission terminal 1 is connected to the second transmission terminal 2 through the first transmission channel 3.

[0035] like Figure 2 As shown, in this embodiment, the first transmission terminal 1 sends a first transmission frame to the second transmission terminal 2 through the first transmission channel 3 at a preset time interval T1. A0, A1, A2, ... are all first transmission frames.

[0036] like Figure 3 As shown, in this embodiment, the first transmission frame includes a first synchronization header. The second transmission terminal 2 uses the received first synchronization header position to perform clock recovery and generate a local clock. The first synchronization header position is the time when the second transmission terminal 2 receives and identifies the first synchronization header. After receiving and identifying the synchronization header, synchronization header position information is generated. This information is sent to the phase-locked loop circuit to generate a clock signal with the same frequency as the synchronization header.

[0037] This invention does not limit the implementation method of the synchronization head receiving circuit, nor does it limit how to use the synchronization head position information to recover the clock. Various methods can be used to receive the synchronization head; for example, an oversampling receiving circuit can be used, where the oversampling clock is much larger than the transmission rate (at least three times). After the synchronization head is detected, synchronization head position information is generated, and this information is then sent to a phase-locked loop circuit to generate a clock signal with the same frequency as the synchronization head.

[0038] The first synchronization header consists of n1 start symbols, where n1 ≥ 3. The start symbols are encoded using line codes and then sent to the first transmission channel 3. Common line codes include 4b / 5b, 8b / 10b, and 9b / 10b codes. Encoding the start symbols with line codes ensures sufficient "0" and "1" transitions in the synchronization header, reducing or eliminating the DC component of the signal during synchronization header transmission. This reduces the design complexity of the receiving circuit and lowers the receiving error rate, facilitating clock recovery at the receiving end. Line codes consist of K-codes and D-codes. Typically, K-codes are used to encode control characters, and D-codes are used to encode data. A K-code is called a unique K-code when its binary sequence appears only in the control characters it encodes and not in any D-code or combination of D-codes. For example, in the 8b / 10b encoding standards widely used in protocols such as SATA, PCIe, RapidIO, and USB 3.0, K28.1, K28.5, and K28.7 are unique K-codes. Using a unique K-code as a start symbol can prevent false detection of synchronization headers in the data field. This embodiment uses 8b / 10b line codes, but this invention does not limit the line codes used. A symbol before 8b / 10b encoding is 8 bits, and a symbol after 8b / 10b encoding is 10 bits.

[0039] like Figure 3 As shown, in this embodiment, the first transmission frame further includes a first data field, which is used to transmit data. In other embodiments, the first transmission frame may not include a first data field.

[0040] In this embodiment, the second transmission terminal 2 uses the received start symbol to determine the position of the first synchronization header. In the international standard ISO 7637-2 fast short pulse interference test, each fast short pulse can interfere with the signal on the transmission line for up to 50 ns. Taking a data transmission rate of 100 Mbps as an example, five consecutive bits of error will occur on the transmission channel. When these five bits belong to two start symbols, it can cause two start symbols to malfunction. Among the n1 start symbols of the first synchronization header, even when at most two start symbols malfunction, the second transmission terminal can still use the received start symbol to determine its position within the first synchronization header. To achieve this, the n1 start symbols must contain at least three unique K codes.

[0041] like Figure 4 As shown in (a), n1=3, the first synchronization header consists of three distinct unique K codes K1, K2, and K3. Figure 4 (b) to Figure 4 (d) Three scenarios are given when two start characters in the first synchronization header are incorrect (shaded areas represent incorrect start characters), namely, detecting "K1", "K2", and "K3" respectively. These three scenarios are independent and can be distinguished by the second transmission terminal 2. Figure 4 (b) Taking the example of errors in K2 and K3, the time when the second transmission terminal 2 detects "K1" and then waits for 20 bits (the start symbol after 8b / 10b encoding is 10 bits) is the time when the first synchronization header ends.

[0042] like Figure 5 As shown in (a), n1=4, and the first synchronization header consists of three identical unique K codes K1, K1, K1 and D code D1. D1 is neither the first nor the last start character in the first synchronization header. Figure 5 (b) to Figure 5 (g) Six scenarios are given when two start characters in the first synchronization header are incorrect (the shaded area represents the incorrect start character, and "X" indicates an incorrect start character after 8b / 10b encoding), namely, detecting "K1D1", "K1XK1", "K1XXK1", "D1K1", "D1XK1", and "K1K1" respectively. These six scenarios are independent of each other and can be distinguished by the second transmission terminal 2. Figure 5 (c) shows an error in D1 and the third K1. When the second transmission terminal 2 detects "K1XK1" and then 10 bits pass, it is the time when the first synchronization header ends.

[0043] like Figure 6 As shown in (a), n1=4. The first synchronization header consists of three unique K codes K1, K1, K2 and D code D1. The two K1 codes are the same, and K1 and K2 are different. Figure 6 (b) to Figure 6 (g) Six scenarios are given when two start characters in the first synchronization header are incorrect (the shaded area represents the incorrect start character, and "X" indicates an incorrect start character after 8b / 10b encoding), namely, detecting "K1K1", "K1XK2", "K1XXD1", "K1K2", "K1XD1", and "K2D1" respectively. These six scenarios are independent of each other and can be distinguished by the second transmission terminal 2. Figure 6 (b) shows an example of an error in K2 and D1. When the second transmission terminal 2 detects "K1K1" and then 20 bits pass, it is the time when the first synchronization header ends.

[0044] like Figure 7 As shown in (a), n1=5, the first synchronization header consists of 3 identical unique K codes K1, K1, K1 and 2 different D codes D1, D2. Figure 7 (b) to Figure 7(k) presents 10 scenarios where two start characters in the first synchronization header are incorrect (shaded areas represent incorrect start characters, and "X" indicates an incorrect start character after 8b / 10b encoding), namely, detecting "K1K1K1", "K1K1XD1", "K1K1XXD2", "K1XK1D1", "K1XK1XD2", "K1XXD1D2", "K1K1D1", "K1K1XD2", "K1XD1D2", and "K1D1D2". These 10 scenarios are independent and can be distinguished by the second transmission terminal 2. Figure 7 (b) Taking the example of errors in D1 and D2, when the second transmission terminal 2 detects "K1K1K1" and then 20 bits pass, it is the time when the first synchronization header ends.

[0045] out Figures 4 to 7 The embodiments shown are merely preferred embodiments of the first synchronization head in this invention, and the scope of protection of this invention is not limited to these embodiments.

[0046] In this embodiment, either or both of the first transmission terminal 1 and the second transmission terminal 2 can exist in the form of an integrated circuit chip.

[0047] like Figure 8 In another application embodiment of the present invention shown, as a fault-tolerant synchronous clock transmission system of the present invention, it is used to transmit a synchronous clock, and... Figure 1 Compared to the illustrated embodiment, the transmission system includes not only a first transmission terminal 1, a second transmission terminal 2, and a first transmission channel 3, but also a third transmission terminal 4 and a second transmission channel 5. The first transmission terminal 1 is connected to the second transmission terminal 2 through the first transmission channel 3, and the second transmission terminal 2 is connected to the third transmission terminal 4 through the second transmission channel 5.

[0048] like Figure 9 As shown, in this embodiment, the first transmission terminal 1 sends a first transmission frame to the second transmission terminal 2 through the first transmission channel 3 at a preset time interval T1. A0, A1, A2, ... are all first transmission frames. After receiving the first transmission frame, the second transmission terminal 2 uses the generated local clock to send a second transmission frame at a preset time interval T2. B0, B1, B2, ... are all second transmission frames.

[0049] In this embodiment, the structure of the first transmission frame is as follows: Figure 3 As shown. With Figure 3The structure of the first transmission frame is similar. The second transmission frame includes a second synchronization header. The third transmission terminal 4 uses the received position of the second synchronization header to perform clock recovery and generate a local clock. The position of the second synchronization header is the time when the third transmission terminal 4 receives the second synchronization header. The second synchronization header consists of n² start characters, where n² ≥ 3. The start characters are encoded using line code and then sent to the third transmission terminal 4. In this embodiment, the second transmission frame also includes a second data field, which is used to transmit data. In other embodiments, the second transmission frame may not include a second data field.

[0050] In this embodiment, the third transmission terminal 4 uses the received start symbols to determine the position of the second synchronization header. Among the n² start symbols of the second synchronization header, even if at most two start symbols are incorrect, the third transmission terminal 4 can still use the received start symbols to determine its position within the second synchronization header. To achieve this, the n² start symbols must contain at least three unique K codes. An embodiment where the third transmission terminal 4 can still determine its position within the second synchronization header even if two of the n² start symbols are incorrect can be found elsewhere. Figures 4 to 7 .

[0051] like Figure 9 As shown, in this embodiment, in order for the third transmission terminal 4 to correctly perform clock recovery and generate a local clock, the second synchronization header is synchronized with the first synchronization header, that is, the time interval T1 for the first transmission terminal 1 to send the first synchronization header is the same as the time interval T2 for the second transmission terminal 2 to send the second synchronization header, T1=T2.

[0052] In this embodiment, any one or more of the first transmission terminal 1, the second transmission terminal 2, and the third transmission terminal 4 can exist in the form of an integrated circuit chip.

[0053] In such Figure 10 In another application embodiment of the present invention, as a fault-tolerant synchronous clock transmission system of the present invention, more transmission terminals are included, showing a more complex topology. In this embodiment, each transmission terminal has at most one upstream transmission terminal, but may have multiple downstream transmission terminals. Each transmission terminal receives a synchronization header from its upstream transmission terminal (except transmission terminal 11) and sends a synchronization header to its downstream transmission terminals (except transmission terminals 41, 42, and 43). The synchronization header sent to the downstream transmission terminals is synchronized with the synchronization header received from the upstream transmission terminals.

[0054] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A fault-tolerant synchronous clock transmission system, comprising a first transmission terminal, a second transmission terminal, and a first transmission channel, wherein the first transmission terminal is connected to the second transmission terminal through the first transmission channel. Its features are: The first transmission terminal sends a first transmission frame to the second transmission terminal through the first transmission channel at preset time intervals. The first transmission frame includes a first synchronization header. The second transmission terminal uses the received first synchronization header position to perform clock recovery and generate a local clock. The first synchronization header consists of n1 start symbols, where n1 ≥ 3, and each of the n1 start symbols contains at least 3 unique K codes. The start symbol is encoded using line code. The second transmission terminal uses the received start symbol to determine the position of the first synchronization header. Among the n1 start symbols, even if at most two start symbols are incorrect, the second transmission terminal can still use the received start symbols to determine its position in the first synchronization header. The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1=4, and in addition to the three unique K codes, the n1 start symbols also include the D code D1. D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n1=4, and in addition to the three unique K codes, the n1 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1=5, and in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, and D1 and D2 are different.

2. The fault-tolerant synchronous clock transmission system according to claim 1, characterized in that: The first transmission frame also includes a first data field for transmitting data.

3. The fault-tolerant synchronous clock transmission system according to claim 1, characterized in that: The synchronous clock transmission system also includes a second transmission channel and a third transmission terminal. The second transmission channel connects to the second transmission terminal, and the second transmission terminal sends the second transmission frame to the third transmission terminal through the second transmission channel. The second transmission frame includes a second synchronization header. The second synchronization header is synchronized with the first synchronization header. The third transmission terminal uses the received second synchronization header position to recover the clock and generate a local clock. The second synchronization header consists of n² start symbols, where n² ≥ 3, and each of the n² start symbols contains at least three unique K-codes. The start symbol is encoded using line code. The third transmission terminal uses the received start symbol to determine the position of the second synchronization header. Among the n² start symbols, even if at most two start symbols are incorrect, the third transmission terminal can still use the received start symbols to determine its position in the second synchronization header. The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2=4, in addition to the three unique K codes, the n2 start symbols also include the D code D1, and D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n2=4, and in addition to the three unique K codes, the n2 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2=5, in addition to the three unique K codes, the n2 start symbols also include D codes D1 and D2, and D1 and D2 are different.

4. The fault-tolerant synchronous clock transmission system according to claim 3, characterized in that: The second transmission frame also includes a second data field for transmitting data.

5. A fault-tolerant synchronous clock transmission system according to claim 3, characterized in that: The second transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

6. A fault-tolerant synchronous clock transmission system according to claim 1 or 3, characterized in that: The line code is encoded in 8b / 10b format.

7. A fault-tolerant synchronous clock transmission system according to claim 1 or 3, characterized in that: The line code is encoded in 9b / 10b.

8. A transmission terminal, connected to a first transmission channel, characterized in that: The transmission terminal receives a first transmission frame transmitted at a preset time interval from the first transmission channel. The first transmission frame includes a first synchronization header. The transmission terminal uses the received first synchronization header position to perform clock recovery and generate a local clock. The first synchronization header consists of n1 start symbols, where n1 ≥ 3, and each of the n1 start symbols contains at least 3 unique K codes. The start symbol is encoded using line code. The transmission terminal uses the received start symbol to determine the position of the first synchronization header. Among the n1 start symbols, if at most two start symbols are incorrect, the transmission terminal can still use the received start symbols to determine its position in the first synchronization header. The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n1=4, and in addition to the three unique K codes, the n1 start symbols also include the D code D1. D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n1=4, and in addition to the three unique K codes, the n1 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, and K1, and these three K codes are identical. The n1 = 5, and in addition to the three unique K codes, the n1 start symbols also include D codes D1 and D2, where D1 and D2 are different. The transmission terminal exists in the form of an integrated circuit chip.

9. A transmission terminal according to claim 8, characterized in that: The first transmission frame also includes a first data field for transmitting data.

10. A transmission terminal according to claim 8, characterized in that: The transmission terminal is also connected to a second transmission channel, through which the transmission terminal sends a second transmission frame. The second transmission frame includes a second synchronization header, which consists of n² start characters, where n² ≥ 3, and each of the n² start characters contains at least three unique K-codes. The start symbol is encoded using line code. The second synchronization header is synchronized with the first synchronization header. The terminal receiving the second synchronization header uses the received second synchronization header position to perform clock recovery and generate a local clock. The terminal receiving the second synchronization header uses the received start symbol to determine the position of the second synchronization header. In the second synchronization header, if at most two start symbols are incorrect, the terminal receiving the second synchronization header can still use the received start symbols to determine its position within the second synchronization header. The three unique K codes are K1, K2, and K3, and the three K codes are all different from each other; Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2=4, in addition to the three unique K codes, the n2 start symbols also include the D code D1, and D1 is not the first or last start symbol in the first synchronization header. Alternatively, the three unique K codes are K1, K1, and K2, with two K1 codes being the same and K1 and K2 being different. The n2=4, and in addition to the three unique K codes, the n2 start symbols also include the D code D1. Alternatively, the three unique K codes are K1, K1, and K1, and the three K codes are the same. The n2=5, in addition to the three unique K codes, the n2 start symbols also include D codes D1 and D2, and D1 and D2 are different.

11. A transmission terminal according to claim 10, characterized in that: The second transmission frame also includes a second data field for transmitting data.

12. A transmission terminal according to claim 10, characterized in that: The transmission terminal uses the received first synchronization header position to perform clock recovery to generate a local clock, and then uses the generated local clock to send the second transmission frame.

13. A transmission terminal according to claim 8 or 10, characterized in that: The line code is encoded in 8b / 10b format.

14. A transmission terminal according to claim 8 or 10, characterized in that: The line code is encoded in 9b / 10b.

Citation Information

Patent Citations

  • Asynchronous serial data recovery method based on 8B / 10B coding

    CN114416626A