一种解调码元时钟生成方法及系统
By sampling the demodulated symbols at different levels and correcting their duration, high and low level clock signals are generated, which solves the problem of clock jitter during FSK signal transmission and improves the accuracy and stability of data decoding.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
- Filing Date
- 2023-06-25
- Publication Date
- 2026-07-17
AI Technical Summary
Existing symbol clock generation methods are subject to various interferences during FSK signal transmission, causing jitter in the symbol clock and data transmission clock signals, which affects the data decoding accuracy.
By sampling the demodulated symbols at different levels, calculating and sampling the levels using a counter based on the duration of several levels, and comparing the level duration with a time threshold, high and low level clock signals are generated. In special cases, the clock output is adjusted by correcting the level duration.
It effectively reduces the probability of a mismatch between the number of clock cycles and the number of symbols, improves the accuracy and stability of data decoding, and reduces the overall deviation of the clock strategy.
Smart Images
Figure CN116961867B_ABST