differential pair inner side impedance compensation

Abstract

An information handling system includes a first differential pair and a second differential pair on a printed circuit board. The first differential pair includes a first trace and a second trace and a first set of impedance compensation traces and a second set of impedance compensation traces. The first impedance compensation traces are routed only on an inside of the first trace. The second impedance compensation traces are routed only on an inside of the second trace, and the first impedance compensation traces and the second impedance compensation traces are substantially aligned. The second differential pair includes a third trace and a fourth trace and a third set of impedance compensation traces and a fourth set of impedance compensation traces. The third set of impedance compensation traces are routed only on an inside of the third trace. The fourth impedance compensation traces are routed only on an inside of the fourth trace, and the third impedance compensation traces and the fourth impedance compensation traces are substantially aligned.

Description

Technical Field

[0001] This disclosure generally relates to information processing systems, and more specifically to differential pair inner impedance compensation. Background Technology

[0002] As the value and use of information continue to grow, individuals and businesses seek additional ways to process and store information. One option is an information processing system. Information processing systems typically process, compile, store, or transmit information or data for business, personal, or other purposes. The technology and information processing needs and requirements may vary between different applications. Therefore, information processing systems may also differ in terms of what information is processed, how it is processed, how much information is processed, stored, or transmitted, and how quickly and efficiently it can be processed, stored, or transmitted. Variations in information processing systems allow them to be general-purpose or configured for specific users or purposes (such as financial transaction processing, airline ticketing, enterprise data storage, or global communications). Furthermore, information processing systems can include a variety of hardware and software resources that can be configured to process, store, and transmit information, and may include one or more computer systems, graphical interface systems, data storage systems, networking systems, and mobile communication systems. Information processing systems can also implement various virtualization architectures. Data and voice communications in information processing systems can be conducted via networks, which can be wired, wireless, or a combination thereof. Summary of the Invention

[0003] An information processing system includes a first differential pair and a second differential pair on a printed circuit board. The first differential pair includes a first trace and a second trace, as well as a first set of impedance compensation traces and a second set of impedance compensation traces. The first impedance compensation trace may be located only inside the first trace. The second impedance compensation trace may be located only inside the second trace, and the first and second impedance compensation traces may be substantially aligned. The second differential pair includes a third trace and a fourth trace, as well as a third set of impedance compensation traces and a fourth set of impedance compensation traces. The third set of impedance compensation traces may be located only inside the third trace. The fourth impedance compensation trace may be located only inside the fourth trace, and the third and fourth impedance compensation traces may be substantially aligned. Attached Figure Description

[0004] It should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others. The accompanying drawings illustrate and describe embodiments incorporating the teachings of this disclosure, in which:

[0005] Figure 1 is a schematic diagram of a differential pair with dual-sided impedance compensation according to the prior art;

[0006] Figure 2 This is a schematic diagram of a differential pair with internal impedance compensation according to at least one embodiment of the present disclosure;

[0007] Figure 3 These are two impedance curves according to at least one embodiment of the present disclosure, and each impedance curve is associated with the impedance of a different corresponding differential pair based on a different impedance compensation scheme.

[0008] Figure 4 These are two return loss curves according to at least one embodiment of this disclosure, and each return loss curve is associated with the return loss of a different corresponding differential pair based on a different impedance compensation scheme.

[0009] Figure 5 These are two crosstalk curves according to at least one embodiment of this disclosure, and each crosstalk curve is associated with crosstalk between differential pairs based on different impedance compensation schemes; and

[0010] Figure 6 This is a flowchart of a method for implementing an internal impedance compensation scheme for a differential pair according to at least one embodiment of the present disclosure; and

[0011] Figure 7 This is a block diagram of a common information processing system according to the implementation scheme of this disclosure;

[0012] Using the same reference numerals in different figures indicates similar or identical items. Detailed Implementation

[0013] The following description, taken in conjunction with the accompanying drawings, is provided to aid in understanding the teachings disclosed herein. The description focuses on specific implementations and methods of the teachings and is provided to help describe these teachings. This description should not be construed as limiting the scope or applicability of these teachings.

[0014] Figure 1 illustrates an information processing system (such as...) according to existing technology in the art. Figure 7 The information processing system 700 includes a printed circuit board (PCB) 100. For the purposes of this disclosure, the information processing system may include any tool or set of tools operable to calculate, classify, process, transmit, receive, retrieve, generate, switch, store, display, indicate, detect, record, reproduce, dispose of, or utilize information, intelligence, or data of any form for commercial, scientific, control, entertainment, or other purposes. For example, the information processing system may be a personal computer, laptop computer, smartphone, tablet device or other consumer electronic device, network server, network storage device, switch, router, or other network communication device, or any other suitable device, and may vary in size, shape, performance, function, and price.

[0015] PCB 100 includes differential pairs 102 and 104. Differential pair 102 includes traces 110 and 112, and differential pair 104 includes traces 114 and 116. The traces 110 of differential pair 102 and 114 of differential pair 104 can be substantially straight based on the layout requirements within the ball grid array (BGA) pin field. However, the spacing or space within the BGA pin field may be limited. In this case, high-speed differential signals transmitted along traces 110 and 112 in differential pair 102 and along traces 114 and 116 in differential pair 104 can both have dynamic phase matching requirements to improve signal transmission quality along the differential pair. Based on the phase matching requirements, traces 112 in differential pair 102 and 116 in differential pair 104 may include phase tuning bump regions 118 to provide phase skew tuning within the respective differential pair. The signal integrity of high-speed signals transmitted along differential pairs 102 and 104 can be improved by other compensation schemes beyond the phase offset tuning described above, such as impedance compensation.

[0016] Impedance compensation along differential pairs 102 and 104 of PCB 100 can be implemented by increasing the width of the differential pair traces in the phase tuning region of the differential pair. As shown in Figure 1, the width of trace 110 in differential pair 102 is increased by both outer compensation 120 and inner compensation 122 in the phase tuning region of differential pair 102. As used herein, outer compensation refers to the side of the trace furthest from the other trace in the differential pair, while inner compensation refers to the side of the trace closest to the other trace in the differential pair. For clarity, only a few outer compensations 120 and a few inner compensations 122 are labeled. However, those skilled in the art will recognize that trace 110 may include both outer compensation 120 and inner compensation 122 at each of the phase tuning regions of differential pair 102.

[0017] As described above regarding trace 110, the width of trace 112 in differential pair 102 is increased by outer compensation 124 and inner compensation 126 in phase tuning bump region 118. For clarity, only a few outer compensations 124 and a few inner compensations 126 are labeled. However, those skilled in the art will recognize that trace 112 may include outer compensation 124 and inner compensation 126 at each of the phase tuning bump regions 118 of differential pair 102. The combination of outer compensation and inner compensation can reduce return loss within differential pair 102.

[0018] As shown in Figure 1, the width of the trace 114 in the differential pair 104 is increased by both outer compensation 130 and inner compensation 132 in the phase tuning region of the differential pair 104. For clarity, only a few outer compensations 130 and a few inner compensations 132 are labeled. However, those skilled in the art will recognize that the trace 114 may include both outer compensation 130 and inner compensation 132 at each location in the phase tuning region of the differential pair 104.

[0019] As described above regarding trace 114, the width of trace 116 in differential pair 104 is increased by outer compensation 134 and inner compensation 136 in phase tuning bump region 118. For clarity, only a few outer compensations 134 and a few inner compensations 136 are labeled. However, those skilled in the art will recognize that trace 116 may include outer compensation 134 and inner compensation 136 at each of the phase tuning bump regions 118 of differential pair 104. The combination of outer compensation and inner compensation can reduce return loss within differential pair 104.

[0020] Crosstalk between the differential signals on differential pair 102 and differential pair 104 can be generated or altered by any suitable structural characteristics of the differential pairs on PCB 100. One such structural characteristic is the distance between differential pairs 102 and 104. As shown in Figure 1, there are two distinct distances 140 and 142 between differential pairs 102 and 104. Distance 140 is the maximum distance between trace 112 in differential pair 102 and trace 114 in differential pair 104, and this distance can be located at any point or location on trace 112 except for the phase tuning bump region 118. Distance 140 can be any suitable distance, including but not limited to thirteen and eight-hundredths mils. Distance 142 is the minimum distance between trace 112 in differential pair 102 and trace 114 in differential pair 104, and this distance can be located within the phase tuning bump region 118 of trace 112. Specifically, distance 142 is the distance between the outer compensation 130 of trace 114 and the outer compensation 124 on the phase tuning bump region 118 of trace 112. Distance 142 can be any suitable distance, including but not limited to nine mils. Those skilled in the art will recognize that a mil is a unit of measurement used for layout on a PCB, and one mil is equal to one-thousandth of an inch or one two-million-forty-thousandth of a millimeter.

[0021] In this scenario, distance 142 likely has the greatest impact on crosstalk between differential pairs 102 and 104. Therefore, while the combination of outer and inner compensations on traces 110, 112, 114, and 116 can reduce return loss within the corresponding differential pairs 102 and 104, outer compensation 124 on trace 112 and outer compensation 130 on trace 114 may increase crosstalk between differential pairs 102 and 104. The width of outer compensation 124 on trace 112 and outer compensation 130 on trace 114 can reduce distance 142, which in turn may increase crosstalk between differential pairs 102 and 104.

[0022] Traces 110 and 112 in difference pair 102 and traces 114 and 116 in difference pair 104 have widths or spacings that can be substantially similar between the difference pairs. For clarity and brevity, the widths and spacings will be described with respect to traces 110 and 112 in difference pair 102. Traces 110 and 112 may have an inter-edge width 144, compensation widths 146 and 148, and a compensation spacing 150. The inter-edge width 144 may be the distance from the outermost edge of the outer compensation 120 of trace 110 to the outermost edge of the outer compensation 124 of trace 112. Therefore, the inter-edge width 144 may vary based on the widths of the outer compensations 120 and 124. The inter-edge width 244 may be any suitable distance, including but not limited to fifteen and eight-hundredths mils.

[0023] The compensation width 146 is the width of trace 112 plus the widths of outer compensation 134 and inner compensation 136. Therefore, the compensation width 146 can vary based on different widths of outer compensation 134 and inner compensation 136. As shown in Figure 1, the compensation width 146 can be measured or determined at the phase tuning bump region 118 of trace 112. The compensation width 148 is the width of trace 110 plus the widths of outer compensation 120 and inner compensation 122, and the compensation width 148 can be measured or determined at the phase tuning bump region of trace 110. Therefore, the compensation width 148 can vary based on different widths of outer compensation 120 and inner compensation 122. In differential pairs 102 and 104 on PCB 100, compensation widths 146 and 148 can be the same width, such as four and six-tenths mils. However, in different layouts of differential pairs 102 and 104, compensation widths 146 and 148 can be different widths.

[0024] The compensation spacing 150 is the width between the inner compensation 122 of trace 110 and the inner compensation 126 of trace 112. Therefore, the compensation spacing 150 can vary based on different widths of the inner compensation 122 and the inner compensation 126. The compensation spacing 150 can be any suitable distance between the inner compensation 122 of trace 110 and the inner compensation 126 of trace 112, such as six and six-tenths mils.

[0025] As described above, while the combination of outer and inner compensation on traces 110, 112, 114, and 116 can reduce return loss within the corresponding differential pair 104, outer compensation 124 on trace 112 and outer compensation 130 on trace 114 may increase crosstalk between differential pairs 102 and 104. The width of outer compensation 124 on trace 112 and outer compensation 130 on trace 114 can reduce distance 142, which may in turn increase crosstalk between differential pairs 102 and 104.

[0026] The inventors of this disclosure have discovered an impedance compensation scheme that maintains the same impedance characteristics and return loss performance as differential pairs 102 and 104, but improves crosstalk performance, as will be discussed below. Figure 2 As described.

[0027] Figure 2 A PCB 200 including differential pairs 202 and 204 is shown according to at least one embodiment of the present disclosure. Differential pair 202 includes traces 210 and 212, and differential pair 204 includes traces 214 and 216. Traces 210, 212, 214, and 216 can be understood as representing information processing systems (such as...) Figure 7 The information processing system 700) includes signal traces that carry data signals between components, and may include portions that are provided as needed or desired on the top or bottom surface of the PCB 200, within one or more layers of the PCB, and within one or more through-holes between the layers of the PCB.

[0028] The traces 210 in differential pair 202 and 214 in differential pair 204 can be substantially straight based on the layout requirements within the BGA pin field. However, the spacing or space within the BGA field may be limited. In this case, high-speed differential signals transmitted along traces 210 and 212 in differential pair 202 and along traces 214 and 216 in differential pair 204 can both have dynamic phase matching requirements to improve signal transmission quality along the differential pair. Based on the phase matching requirements, traces 212 in differential pair 202 and 216 in differential pair 204 may include phase tuning bump regions 218 to provide phase skew tuning within the respective differential pair. The signal integrity of high-speed signals transmitted along differential pairs 202 and 204 can be improved via other compensation schemes beyond the phase skew tuning described above, such as impedance compensation.

[0029] Impedance compensation for differential pairs 202 and 204 along PCB 200 can be implemented by increasing the differential pair trace width in the phase tuning region of the differential pair. For example... Figure 2 As shown, the width of trace 210 in differential pair 202 can be increased solely by inner compensation 222 in the phase tuning region of differential pair 202. In the example, the width of inner compensation 222 of trace 210 can be greater than the width of inner compensation 122 of trace 110 to provide similar impedance compensation for trace 210 compared to trace 110 of FIG. 1. In some examples, the increased width of inner compensation 222 compared to inner compensation 122 can be any suitable amount up to the combined width of outer compensation 120 and inner compensation 122 of trace 110 of FIG. 1. For clarity, only a few inner compensations 222 are labeled. However, those skilled in the art will recognize that trace 210 can include inner compensation 222 at each of the phase tuning regions of differential pair 202.

[0030] As described above regarding trace 210, the width of trace 212 in differential pair 202 can be increased solely by the inner compensation 226 in phase tuning bump region 218. In the example, the width of the inner compensation 226 of trace 212 can be greater than the width of the inner compensation 126 of trace 112 to provide similar impedance compensation for trace 212 compared to trace 112 of FIG. 1. In some examples, the increased width of the inner compensation 226 compared to the inner compensation 126 can be any suitable amount up to the combined width of the outer compensation 124 and the inner compensation 126 of trace 112 of FIG. 1. For clarity, only a few inner compensations 226 are labeled. However, those skilled in the art will recognize that trace 212 can include inner compensation 226 at each of the phase tuning bump regions 218 of differential pair 202. The inner compensation 222 of trace 210 and the inner compensation 226 of trace 212 can reduce return loss within the differential pair 202. In some examples, the widths of the inner compensations 222 and 226 can be varied depending on the desired impedance compensation of the differential pair 202. For example, if the widths of the inner compensations 222 and 226 are reduced, smaller impedance compensation can be provided, while if the widths of the inner compensations 222 and 226 are increased, larger impedance compensation can be provided.

[0031] As described above, compared to differential pair 102, the inner compensation 222 of trace 210 and the inner compensation 226 of trace 212 can maintain the impedance compensation of differential pair 202 in a basically similar manner. Figure 3 Shown and described.

[0032] Figure 3 Two impedance curves 302 and 304 according to at least one embodiment of the present disclosure are shown, and each impedance curve is based on a different impedance compensation scheme and a different corresponding differential pair (such as differential pair 102 and 104 in Figure 1). Figure 2 The differential pair (202) is related to the impedance. For example... Figure 3 As shown, the vertical axis indicates the impedance of the differential pair, while the horizontal axis indicates the amount of time measured in picoseconds. In this example, impedance compensation for the differential pair can be used to keep the impedance variation of the differential pair trace within 1 ohm, such as... Figure 3 The resistance is between 88 ohms and 89 ohms.

[0033] Impedance curve 302 can be associated with differential pairs 102 or 104 of Figure 1. Impedance curve 302 can be controlled based on impedance compensation added to the traces of a particular differential pair. As described above, impedance compensation along differential pairs 102 and 104 of PCB 100 can be implemented by increasing the width of the differential pair traces in the phase tuning region of the differential pair. As shown in Figure 1, the width of trace 110 in differential pair 102 is increased by both outer compensation 120 and inner compensation 122 in the phase tuning region of differential pair 102. Similarly, the width of trace 112 in differential pair 102 is increased by both outer compensation 124 and inner compensation 126 in the phase tuning region of differential pair 102. Therefore, the outer compensations 120 and 124 and the inner compensations 122 and 126 within differential pair 102 can give the differential pair an impedance curve 302 and limit the impedance variation to less than 1 ohm, as... Figure 3 As shown.

[0034] Impedance curve 304 can be compared with Figure 2 The differential pairs 202 and 204 are associated. The impedance profile 304 can be controlled based on impedance compensation added to the traces of a particular differential pair. As described above, impedance compensation along differential pairs 202 and 204 of PCB 200 can be implemented by increasing the differential pair trace width in the phase tuning region of the differential pair. Figure 2 As shown, the width of trace 210 in differential pair 202 is increased only by inner compensation 222 in the phase tuning region of differential pair 202. Similarly, the width of trace 212 in differential pair 202 is increased only by inner compensation 226 in the phase tuning region of differential pair 202. Therefore, the inner compensations 222 and 226 within differential pair 202 can give the differential pair an impedance curve 304 and an impedance variation limited to less than 1 ohm, as... Figure 3 As shown.

[0035] Return to reference Figure 2 Compared to differential pair 102, the inner compensation 222 of trace 210 and the inner compensation 226 of trace 212 can maintain a basically similar return loss for differential pair 202. (The last sentence appears to be incomplete and possibly contains errors.) Figure 4 Shown and described.

[0036] Figure 4 Two return loss curves 402 and 404 according to at least one embodiment of the present disclosure are shown, and each return loss curve is based on Figure 1 and Figure 2 Different impedance compensation schemes and different corresponding differential pairs (such as differential pair 102 in Figure 1 and...) Figure 2 The differential pair (202) is associated with the return loss. For example... Figure 4As shown, the vertical axis indicates the amount of return loss, while the horizontal axis indicates the frequency in gigahertz (GHz). In the example, impedance compensation for the differential pair can be used to maintain a specific return loss for the differential pair at a given frequency.

[0037] The return loss curve 402 can be associated with differential pairs 102 or 104 of Figure 1. The return loss curve 402 can be controlled based on impedance compensation added to the traces of a particular differential pair. As described above, impedance compensation along differential pairs 102 and 104 of PCB 100 can be implemented by increasing the width of the differential pair traces in the phase tuning region of the differential pair. As shown in Figure 1, the width of trace 110 in differential pair 102 is increased by both outer compensation 120 and inner compensation 122 in the phase tuning region of differential pair 102. Similarly, the width of trace 112 in differential pair 102 is increased by both outer compensation 124 and inner compensation 126 in the phase tuning region of differential pair 102. Therefore, the outer compensations 120 and 124 and the inner compensations 122 and 126 within the differential pair 102 can give the differential pair a return loss curve 402, which has a specific return loss at a given frequency, such as at 21.58 GHz, where the return loss is essentially -30 dB. Figure 4 Point 410 is indicated.

[0038] The return loss curve 404 can be compared with Figure 2 The differential pairs 202 and 204 are associated. The return loss curve 404 can be controlled based on impedance compensation added to the traces of a particular differential pair. As described above, impedance compensation along differential pairs 202 and 204 of PCB 200 can be implemented by increasing the differential pair trace width in the phase tuning region of the differential pair. Figure 2 As shown, the width of trace 210 in differential pair 202 is increased only by inner compensation 222 in the phase tuning region of differential pair 202. Similarly, the width of trace 212 in differential pair 202 is increased only by inner compensation 226 in the phase tuning region of differential pair 202. Therefore, the inner compensations 222 and 226 within differential pair 202 can give the differential pair a return loss curve 402, where at the same frequency as return loss curve 502, the return loss is essentially equal to the return loss at point 510, such as at 21.58 GHz, the return loss is essentially -30 dB. Figure 4 Point 420 in the diagram indicates this.

[0039] Return to reference Figure 2The width of trace 214 in differential pair 204 can be increased solely by inner compensation 232 in the phase tuning region of differential pair 204. In an example, the width of inner compensation 232 of trace 214 can be greater than the width of inner compensation 122 of trace 114 to provide similar impedance compensation to trace 214 compared to trace 114 of FIG. 1. In some examples, the increased width of inner compensation 232 compared to inner compensation 132 can be any suitable amount up to the combined width of outer compensation 130 and inner compensation 132 of trace 114 of FIG. 1.

[0040] The width of trace 216 in differential pair 204 is increased only by the inner compensation 236 in phase tuning bump region 218. In the example, the width of the inner compensation 236 of trace 216 can be greater than the width of the inner compensation 136 of trace 116 to provide similar impedance compensation to trace 216 compared to trace 116 of FIG. 1. The increased width of the inner compensation 236 compared to the inner compensation 136 can be any suitable amount up to the combined width of the outer compensation 134 and the inner compensation 136 of trace 116 of FIG. 1. For clarity, only a few inner compensations 232 and 236 are labeled. However, those skilled in the art will recognize that trace 214 can include inner compensation 232 at each of the phase tuning regions of differential pair 204, and trace 216 can include inner compensation 236 at each of the phase tuning bump regions 218. The inner compensation 232 of trace 214 and the inner compensation 236 of trace 216 can reduce return loss within the differential pair 204. In some examples, the widths of the inner compensations 232 and 236 can be varied depending on the desired impedance compensation of the differential pair 204. For example, if the widths of the inner compensations 232 and 236 are reduced, smaller impedance compensation can be provided, while if the widths of the inner compensations 232 and 236 are increased, larger impedance compensation can be provided.

[0041] Crosstalk between the differential signals on differential pair 202 and differential pair 204 can be generated or altered by any suitable structural characteristics of the differential pairs on PCB 200. One such structural characteristic is the distance between differential pairs 202 and 204. For example... Figure 2 As shown, there are two distinct distances, 240 and 242, between differential pairs 202 and 204. Distance 240 is the maximum distance between trace 212 in differential pair 202 and trace 214 in differential pair 204, and this distance can be located at any point or location on trace 212 except for the phase tuning bump region 218. Distance 240 can be any suitable distance, including but not limited to thirteen and eight-hundredths mils. In this example, distance 240 between differential pairs 202 and 204 can be substantially equal to distance 140 between differential pairs 102 and 104 on PCB 100 of Figure 1.

[0042] Distance 242 is the minimum distance between trace 212 in differential pair 202 and trace 214 in differential pair 204, and this distance can be located within the phase tuning bump region 218 of trace 212. Specifically, distance 242 is the distance between the outer edge of trace 214 and the outer edge of the phase tuning bump region 218 of trace 212. In this example, the outer edges of traces 212 and 214 can be the edges of the traces themselves, without adding an outer compensation trace to the traces. Distance 242 can be any suitable distance, including but not limited to ten mils. In this example, the distance 240 between differential pairs 202 and 204 can be greater than the distance 140 between differential pairs 102 and 104 on PCB 100 of FIG. 1.

[0043] In this scenario, distance 242 can improve the far-end crosstalk (FEXT) performance of differential pairs 202 and 204 compared to the crosstalk performance of differential pairs 102 and 204. In the example, the combination of inner compensations 222 and 226 on the corresponding traces 210 and 212 can reduce return loss within differential pair 202. Similarly, the combination of inner compensations 232 and 236 on the corresponding traces 214 and 216 can reduce return loss within differential pair 204. Furthermore, based on traces 210, 212, 214, and 216 that only include the corresponding inner compensations 222, 226, 232, and 236, the FEXT between differential pairs 202 and 204 can be reduced. In this example, the inner compensations 222, 226, 232, and 236 do not affect the distance 242 between difference pairs 202 and 204, which, compared to difference pairs 102 and 104, can in turn reduce or suppress the FEXT between difference pairs 202 and 204, as will be referred to Figure 5 Shown and described.

[0044] Figure 5 Crosstalk curves 502 and 504 are shown according to at least one embodiment of the present disclosure, said crosstalk curves being correlated with crosstalk between differential pairs based on different impedance compensation schemes. Figure 4 As shown, the vertical axis indicates the amount of crosstalk loss between differential pairs, while the horizontal axis indicates the frequency in gigahertz (GHz). In the example, impedance compensation of the differential pairs may affect the crosstalk between differential pairs at a given frequency.

[0045] Crosstalk curve 502 can be associated with differential pairs 102 and 104 of FIG1. ​​Crosstalk curve 502 can be affected based on impedance compensation added to the traces of the differential pairs. As described above, impedance compensation along differential pairs 102 and 104 of PCB 100 can be implemented by increasing the width of the differential pair traces in the phase tuning region of the differential pairs. As shown in FIG1, the width of trace 110 in differential pair 102 is increased by both outer compensation 120 and inner compensation 122 in the phase tuning region of differential pair 102. Similarly, the width of trace 112 in differential pair 102 is increased by both outer compensation 124 and inner compensation 126 in the phase tuning region of differential pair 102. Therefore, outer compensations 120 and 124 and inner compensations 122 and 126 within differential pair 102 may create a distance 142 between differential pairs 102 and 104.

[0046] A distance of 142 may result in crosstalk curve 402 for differential pairs 102 and 104, with specific crosstalk at the corresponding frequency. Differential pairs 102 and 104 can be used to provide high-speed signals, such as 16 GHz or 28 GHz signals. Figure 5 As indicated by point 510, differential pairs 102 and 104 can achieve power and far-end crosstalk (PSFEXT) suppression of approximately -42 dB at 16 GHz. Similarly, as Figure 5 As indicated by point 512, differential pairs 102 and 104 can have power and far-end crosstalk (PSFEXT) suppression of approximately -38 dB at 28 GHz.

[0047] Crosstalk curve 504 can be compared with Figure 2 Differential pairs 202 and 204 are associated. Crosstalk curve 504 can be affected based on impedance compensation added to the traces of a particular differential pair. As mentioned above, impedance compensation along differential pairs 202 and 204 of PCB 200 can be implemented by increasing the differential pair trace width in the phase tuning region of the differential pair. Figure 2 As shown, the width of trace 210 in differential pair 202 is increased only by inner compensation 222 in the phase tuning region of differential pair 202. Similarly, the width of trace 212 in differential pair 202 is increased only by inner compensation 226 in the phase tuning region of differential pair 202. Therefore, inner compensations 222 and 226 within differential pair 202 may create a distance 242 between differential pairs 202 and 204.

[0048] As described above, distance 242 can be greater than distance 142 of differential pairs 102 and 104, allowing for improved FEXT performance of differential pairs 202 and 204 compared to differential pairs 102 and 104. In the example, distance 242 may result in differential pairs 202 and 204 having a crosstalk curve 504, with a specific FEXT at the corresponding frequency. Differential pairs 202 and 204 can be used to provide high-speed signals substantially similar to those of differential pairs 102 and 104. Figure 5 As shown, compared to crosstalk curve 502, crosstalk curve 504 exhibits greater PSFEXT loss or suppression across all frequencies of the signal. For example, crosstalk curve 504 indicates that differential pairs 202 and 204 can have PSFEXT suppression of approximately -45 dB at 16 GHz, as... Figure 5 Point 520 in the diagram indicates that, compared to difference pairs 102 and 104, this PSFEXT suppression is essentially equal to the 3dB PSFEXT suppression improvement of difference pairs 202 and 204. Similarly, as... Figure 5 As indicated by point 514, differential pairs 202 and 204 can achieve PSFEXT suppression of approximately -41 dB at 28 GHz. This PSFEXT suppression is approximately equivalent to the 3 dB PSFEXT suppression improvement of differential pairs 202 and 204 compared to differential pairs 102 and 104.

[0049] Traces 210 and 212 in difference pair 202 and traces 214 and 216 in difference pair 204 have widths or spacings that can be substantially similar between the difference pairs. For clarity and brevity, the widths and spacings will be described with respect to traces 210 and 212 in difference pair 202. Traces 210 and 212 may have an inter-edge width 244, compensation widths 246 and 248, and a compensation spacing 250. The inter-edge width 244 may be the distance from the outermost edge of trace 210 to the outermost edge of trace 212. Therefore, the inter-edge width 244 may vary based on the widths of traces 210 and 212. The inter-edge width 244 may be any suitable distance, including but not limited to fourteen and eight-hundredths mils. In the example, the edge-to-edge width 244 of traces 210 and 212, and the edge-to-edge width of traces 214 and 216, can all be smaller than the edge-to-edge width 144 of traces 110 and 112, and the edge-to-edge width of traces 114 and 116 in FIG. 1. In this example, the amount of space consumed or covered by traces 210 and 212 in differential pair 202 and traces 214 and 216 in differential pair 204 on PCB 200 can be smaller than the amount of space consumed or covered by differential pairs 102 and 104 on PCB 100 of FIG. 1.

[0050] The compensation width 246 is the width of trace 212 plus the width of inner compensation 236. Therefore, the compensation width 246 can vary based on different widths of inner compensation 236. Figure 2 As shown, the compensation width 246 can be measured or determined at the phase tuning bump region 218 of trace 212. The compensation width 248 is the width of trace 210 plus the inner compensation 222, and the compensation width 248 can be measured or determined at the phase tuning bump region of trace 210. Therefore, the compensation width 248 can vary based on different widths of the outer compensation 220 and the inner compensation 222. In differential pairs 202 and 204 on PCB 200, compensation widths 246 and 248 can be the same width, such as four and four-tenths mils. However, in different layouts of differential pairs 202 and 204, compensation widths 246 and 248 can be different widths.

[0051] The compensation spacing 250 is the width between the inner compensation 222 of trace 210 and the inner compensation 226 of trace 212. Therefore, the compensation spacing 250 can vary based on different widths of the inner compensation 222 and the inner compensation 226. The compensation spacing 250 can be any suitable distance between the inner compensation 222 of trace 210 and the inner compensation 226 of trace 212, such as six mils.

[0052] As described above, compared to differential pair 102, the inner compensation 222 of trace 210 and the inner compensation 226 of trace 212 can maintain substantially similar impedance compensation and return loss for differential pair 202. Similarly, compared to differential pair 104, the inner compensation 232 of trace 214 and the inner compensation 236 of trace 216 can maintain substantially similar impedance compensation and return loss for differential pair 204. Furthermore, compared to differential pairs 102 and 104, traces 210, 212, 214, and 216, having only the corresponding inner compensations 222, 226, 232, and 236, can improve the crosstalk performance of differential pairs 202 and 204, as shown in the figure. Figure 6 Shown and described.

[0053] Figure 6 This is a flowchart of a method 600 for implementing an internal impedance compensation scheme for a differential pair according to at least one embodiment of the present disclosure, which begins at block 602. It should be readily understood that not every method step illustrated in this flowchart is always necessary, but certain steps of the method may be combined, performed simultaneously, performed in different orders, or may be omitted without departing from the scope of the present disclosure. Figure 6 It can be used, in whole or in part, for operational purposes. Figure 6 Any other type of controller, device, module, processor, or any combination thereof, in whole or in part, of the method.

[0054] At block 604, a first trace of the differential pair is provided or laid out on the PCB. In the example, the first trace can be of any suitable length and can be provided on the PCB in any suitable direction. For example, the orientation of the first trace on the PCB can be based on the layout requirements within the BGA pin field of the PCB. At block 606, a second trace of the differential pair is provided or laid out on the PCB. In the example, the second trace can be laid out at a specific distance from the first trace to create a differential pair of the first and second traces. In some examples, the spacing or space within the BGA pin field may be limited. In this case, high-speed differential signals transmitted along the first and second traces in the differential pair may have dynamic phase matching requirements to improve the signal transmission quality along the differential pair. Based on the phase matching requirements, the second trace in the differential pair may include a phase tuning bump region to provide phase skew tuning within the respective differential pair.

[0055] At box 608, a first set of impedance compensation traces may be provided or laid out inside the first trace. In the example, the first impedance compensation traces may be located at any suitable location along the first trace. For example, the first impedance compensation traces may be located inside the first trace at the phase tuning bump region of the differential pair.

[0056] At block 610, a second set of impedance compensation traces may be provided or laid out inside the first trace, and the process ends at block 612. In the example, the second impedance compensation traces may be located at any suitable location along the second trace. For example, the second impedance compensation trace may be located inside the phase tuning bump region on the second trace. In some examples, compared to a previous impedance compensation scheme, the first and second impedance compensation traces may maintain specific impedance and return loss along the first and second traces, and may provide improved crosstalk performance between the differential pair and nearby differential pairs.

[0057] Figure 7A common embodiment of the information processing system 700 is illustrated. For the purposes of this disclosure, the information processing system may include any tool or set of tools operable to calculate, classify, process, transmit, receive, retrieve, generate, switch, store, display, indicate, detect, record, reproduce, dispose of, or utilize information, intelligence, or data of any form for commercial, scientific, control, entertainment, or other purposes. For example, the information processing system 700 may be a personal computer, laptop computer, smartphone, tablet device or other consumer electronic device, network server, network storage device, switch, router, or other network communication device, or any other suitable device, and may vary in size, shape, performance, functionality, and price. Furthermore, the information processing system 700 may include processing resources for executing machine-executable code, such as a central processing unit (CPU), a programmable logic array (PLA), an embedded device such as a system-on-a-chip (SoC), or other control logic hardware. The information processing system 700 may also include one or more computer-readable media for storing machine-executable code such as software or data. Additional components of the information processing system 700 may include one or more storage devices capable of storing machine-executable code, one or more communication ports for communicating with external devices, and various input and output (I / O) devices (such as a keyboard, mouse, and video display). The information processing system 700 may also include one or more buses operable to transfer information between various hardware components.

[0058] Information processing system 700 may include devices or modules embodying one or more of the following means or modules, and operates to perform one or more of the following methods. Information processing system 700 includes processors 702 and 704, input / output (I / O) interfaces 710, memory 720 and 725, graphics interface 730, basic input / output system / generic extensible firmware interface (BIOS / UEFI) module 740, disk controller 750, hard disk drive (HDD) 754, optical disk drive (ODD) 756, disk emulator 760 connected to external solid-state drive (SSD) 762, I / O bridge 770, one or more additional resources 774, trusted platform module (TPM) 776, network interface 780, management device 790, and power supply 795. Processors 702 and 704, I / O interface 710, memory 720, graphics interface 730, BIOS / UEFI module 740, disk controller 750, HDD 754, ODD 756, disk emulator 760, SSD 762, I / O bridge 770, additional resources 774, TPM 776, and network interface 780 operate together to provide a host environment for information processing system 700, which operates to provide the data processing functionality of the information processing system. The host environment operates to execute machine-executable code, including platform BIOS / UEFI code, device firmware, operating system code, applications, programs, etc., to perform data processing tasks associated with information processing system 700.

[0059] In a host environment, processor 702 is connected to I / O interface 710 via processor interface 706, while processor 704 is connected to I / O interface 708. Memory 720 is connected to processor 702 via memory interface 722. Memory 725 is connected to processor 704 via memory interface 727. Graphics interface 730 is connected to I / O interface 710 via graphics interface 732 and provides video display output 736 to video display 734. In a particular embodiment, information processing system 700 includes separate memory dedicated to each of processors 702 and 704 via separate memory interfaces. Examples of memories 720 and 730 include random access memory (RAM), such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), read-only memory (ROM), another type of memory, or a combination thereof.

[0060] The BIOS / UEFI module 740, disk controller 750, and I / O bridge 770 are connected to the I / O interface 710 via I / O channel 712. Examples of I / O channels 712 include a Peripheral Component Interconnect (PCI) interface, a PCI-Extend (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry-standard or proprietary communication interface, or a combination thereof. The I / O interface 710 may also include one or more other I / O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. The BIOS / UEFI module 740 includes BIOS / UEFI code operable to detect resources within the information processing system 700, provide drivers for the resources, initialize the resources, and access the resources. The BIOS / UEFI module 740 includes code operable to detect resources within the information processing system 700, provide drivers for the resources, initialize the resources, and access the resources.

[0061] The disk controller 750 includes a disk interface 752 that connects the disk controller to an HDD 754, an ODD 756, and a disk emulator 760. Examples of disk interfaces 752 include an Integrated Drive Electronics (IDE) interface, an Advanced Technology Accessory (ATA) interface such as a Parallel ATA (PATA) interface or a Serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. The disk emulator 760 allows an SSD 764 to be connected to the information processing system 700 via an external interface 762. Examples of external interfaces 762 include a USB interface, an IEEE 1394 (FireWire) interface, a proprietary interface, or a combination thereof. Alternatively, the solid-state drive 764 may be located within the information processing system 700.

[0062] I / O bridge 770 includes a peripheral interface 772 that connects the I / O bridge to additional resources 774, TPM 776, and network interface 780. Peripheral interface 772 can be the same type as I / O channel 712, or it can be a different type of interface. Thus, when peripheral interface 772 and I / O channel 712 are of the same type, I / O bridge 770 extends the capabilities of the I / O channel; when they are of different types, I / O bridge converts information from a format suitable for the I / O channel to a format suitable for peripheral bridge 772. Additional resources 774 may include a data storage system, an additional graphics interface, a network interface card (NIC), a voice / video processing card, another additional resource, or a combination thereof. Additional resources 774 may be located on the main circuit board, on a separate circuit board or additional card disposed within the information processing system 700, on a device external to the information processing system, or a combination thereof.

[0063] Network interface 780 represents a NIC, which is disposed within information processing system 700, located on the main circuit board of information processing system, integrated into another component such as I / O interface 710, located in another suitable location, or a combination thereof. Network interface device 780 includes network channels 782 and 784 that provide interfaces to devices outside information processing system 700. In certain embodiments, network channels 782 and 784 are of a different type from peripheral channel 772, and network interface 780 converts information from a format suitable for the peripheral channel to a format suitable for external devices. Examples of network channels 782 and 784 include InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or combinations thereof. Network channels 782 and 784 can connect to external network resources (not shown). Network resources may include another information processing system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

[0064] Management device 790 refers to one or more processing devices operating together to provide a management environment for information processing system 700, such as a dedicated board management controller (BMC), a system-on-a-chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), etc. Specifically, management device 790 connects to various components of the host environment via various internal communication interfaces (such as low pin count (LPC) interfaces, internal integrated circuit (I2C) interfaces, PCIe interfaces, etc.) to provide out-of-band (OOB) mechanisms to retrieve information related to the operation of the host environment, provide BIOS / UEFI or system firmware updates, and manage non-processing components of information processing system 700, such as system cooling fans and power supplies. Management device 790 may include a network connection to an external management system, and the management device can communicate with the management system to report status information of information processing system 700, receive BIOS / UEFI or system firmware updates, or perform other tasks for managing and controlling the operation of information processing system 700. The management device 790 can operate outside the power plane of components in the host environment, allowing it to receive power to manage the information processing system 700 when the information processing system is otherwise shut down. Examples of the management device 790 include commercially available BMC products or other devices operating according to the Intelligent Platform Management Initiative (IPMI) specification, the Network Services Management (WSMan) interface, the Redfish application programming interface (API), another Distributed Management Task Force (DMTF), or other management standards, and may include integrated Dell Remote Access Controller (iDRAC), embedded controllers (EC), etc. The management device 790 may also include associated memory devices, logic devices, security devices, etc., as needed or desired.

[0065] Although only a few exemplary embodiments have been described in detail herein, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the embodiments of this disclosure. Therefore, all such modifications are intended to be included within the scope of the embodiments of this disclosure as defined in the appended claims. In the claims, the device plus function clause is intended to cover not only structural equivalents but also equivalent structures as described herein.

[0066] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments falling within the scope of this invention. Therefore, to the fullest extent permitted by law, the scope of this invention will be determined by the broadest permissible interpretation of the following claims and their equivalents, and should not be construed as limited by the foregoing detailed description.

Claims

1. An information processing system, comprising: The first differential pair on the printed circuit board of the information processing system includes: First trace and second trace; A first set of impedance compensations, wherein the first set of impedance compensations is only disposed inside the first trace, wherein the first width of the first trace increases at the location of each of the first set of impedance compensations; and The second group of impedance compensation is only arranged inside the second trace, wherein the second width of the second trace increases at the position of each of the second group of impedance compensations, wherein the first group of impedance compensations and the second group of impedance compensations are substantially aligned. The second differential pair on the printed circuit board includes a third trace and a fourth trace, wherein a first distance separates the first differential pair and the second differential pair based on the distance between the outer edge of the second trace at the phase tuning bump region of the first differential pair and the outer edge of the third trace at the phase tuning bump region of the second differential pair. The third differential pair on the printed circuit board includes a fifth trace and a sixth trace; The fourth differential pair on the printed circuit board includes a seventh trace and an eighth trace, wherein a second distance separates the third differential pair and the fourth differential pair based on the distance between the outer edge of the sixth trace at the phase tuning bump region of the third differential pair and the outer edge of the seventh trace at the phase tuning bump region of the fourth differential pair, wherein the first distance is greater than the second distance.

2. The information processing system according to claim 1, wherein the second differential pair comprises: The third group of impedance compensation is only arranged inside the third trace. as well as The fourth group of impedance compensation is only arranged inside the fourth trace, wherein the third group of impedance compensation and the fourth group of impedance compensation are basically aligned.

3. The information processing system according to claim 1, wherein the first distance affects the crosstalk performance of the first differential pair and the second differential pair.

4. The information processing system according to claim 1, wherein the third difference pair comprises: The fifth group of impedance compensation is arranged inside the fifth trace; The sixth group of impedance compensation is arranged outside the fifth trace, wherein the fifth group of impedance compensation and the sixth group of impedance compensation are basically aligned. The seventh group of impedance compensation is arranged inside the sixth trace. as well as The eighth group of impedance compensation is arranged outside the sixth trace, wherein the seventh group of impedance compensation and the eighth group of impedance compensation are basically aligned. The fourth difference pair includes: The ninth group of impedance compensation is arranged inside the seventh trace. The tenth group of impedance compensation is arranged outside the seventh trace, wherein the ninth group of impedance compensation and the tenth group of impedance compensation are basically aligned. The eleventh group of impedance compensation is arranged inside the eighth trace; and The twelfth group of impedance compensation is located outside the eighth trace, wherein the eleventh group of impedance compensation and the twelfth group of impedance compensation are basically aligned.

5. The information processing system according to claim 1, wherein, based on the fact that the first distance is greater than the second distance, the first difference pair and the second difference pair have greater crosstalk suppression compared to the third difference pair and the fourth difference pair.

6. The information processing system according to claim 1, wherein the first differential pair and the second differential pair have substantially equal impedance compensation compared to the third differential pair and the fourth differential pair.

7. An information processing system, comprising: The first differential pair on the printed circuit board of the information processing system includes: First trace and second trace; A first set of impedance compensations is disposed only inside the first trace, wherein the first set of impedance compensations is located inside the first trace at the phase tuning bump region of the first differential pair, wherein the first width of the first trace increases at the location of each of the first set of impedance compensations; and The second set of impedance compensations is located only inside the second trace, wherein the second set of impedance compensations is situated inside the second trace at the phase tuning bump region of the first differential pair, wherein the second width of the second trace increases at the position of each of the second set of impedance compensations, and wherein the first set of impedance compensations and the second set of impedance compensations are substantially aligned; and The second differential pair on the printed circuit board, wherein the second differential pair includes: The third and fourth traces; A third set of impedance compensations is provided only on the inner side of the third trace, wherein the third set of impedance compensations is located on the inner side of the third trace at the phase tuning bump region of the second differential pair; and The fourth group of impedance compensation is provided only on the inner side of the fourth trace, wherein the fourth group of impedance compensation is located on the inner side of the fourth trace at the phase tuning bump region of the second differential pair, wherein the third group of impedance compensation and the fourth group of impedance compensation are substantially aligned, wherein the first distance is based on the distance between the outer edge of the second trace at the phase tuning bump region of the first differential pair and the outer edge of the third trace at the phase tuning bump region of the second differential pair to separate the first differential pair and the second differential pair; The third differential pair on the printed circuit board includes: a fifth trace and a sixth trace; and The fourth differential pair on the printed circuit board includes a seventh trace and an eighth trace, wherein a second distance separates the third differential pair and the fourth differential pair based on the distance between the outer edge of the sixth trace at the phase tuning bump region of the third differential pair and the outer edge of the seventh trace at the phase tuning bump region of the fourth differential pair, wherein the first distance is greater than the second distance.

8. The information processing system according to claim 7, wherein the first distance affects the crosstalk performance of the first differential pair and the second differential pair.

9. The information processing system according to claim 7, wherein the third difference pair comprises: The fifth group of impedance compensation is arranged inside the fifth trace; The sixth group of impedance compensation is arranged outside the fifth trace, wherein the fifth group of impedance compensation and the sixth group of impedance compensation are basically aligned. The seventh group of impedance compensation is arranged inside the sixth trace. as well as The eighth group of impedance compensation is arranged outside the sixth trace, wherein the seventh group of impedance compensation and the eighth group of impedance compensation are basically aligned. The fourth difference pair includes: The ninth group of impedance compensation is arranged inside the seventh trace. The tenth group of impedance compensation is arranged outside the seventh trace, wherein the ninth group of impedance compensation and the tenth group of impedance compensation are basically aligned. The eleventh group of impedance compensation is arranged inside the eighth trace; and The twelfth group of impedance compensation is located outside the eighth trace, wherein the eleventh group of impedance compensation and the twelfth group of impedance compensation are basically aligned.

10. The information processing system according to claim 7, wherein, based on the fact that the first distance is greater than the second distance, the first difference pair and the second difference pair have greater crosstalk suppression compared to the third difference pair and the fourth difference pair.

11. The information processing system according to claim 9, wherein the first differential pair and the second differential pair have substantially equal impedance compensation compared to the third differential pair and the fourth differential pair.

12. A method for laying out a printed circuit board in an information processing system, comprising: The first trace of the first differential pair is laid out on the printed circuit board of the information processing system; The second trace of the first differential pair is laid out on the printed circuit board of the information processing system; A first set of impedance compensations is laid along the first trace, wherein the first set of impedance compensations is laid only inside the first trace, wherein the first width of the first trace increases at the position of each of the first set of impedance compensations. A second set of impedance compensations is laid along the second trace, wherein the second set of impedance compensations is laid only inside the second trace, wherein the second width of the second trace increases at the position of each of the second set of impedance compensations. A third and a fourth trace of a second differential pair are laid out on a printed circuit board of an information processing system, wherein a first distance separates the first differential pair and the second differential pair based on the distance between the outer edge of the second trace at the phase tuning bump region of the first differential pair and the outer edge of the third trace at the phase tuning bump region of the second differential pair. The fifth and sixth traces of the third differential pair are laid out on the printed circuit board of the information processing system. as well as The seventh and eighth traces of the fourth differential pair are laid out on the printed circuit board of the information processing system, wherein the second distance is based on the distance between the outer edge of the sixth trace at the phase tuning bump region of the third differential pair and the outer edge of the seventh trace at the phase tuning bump region of the fourth differential pair to separate the third differential pair and the fourth differential pair, wherein the first distance is greater than the second distance.

13. The method for laying out a printed circuit board in an information processing system according to claim 12, wherein the first set of impedance compensations is located inside the first trace at the phase tuning bump region of the first differential pair, and the second set of impedance compensations is located inside the second trace at the phase tuning bump region of the first differential pair.

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