A three-dimensional memory array and methods of making the same

Abstract

The application provides a three-dimensional memory array architecture and a preparation method thereof, and belongs to the technical field of micro-nano electronics. In the three-dimensional 1T1R array provided by the application, each source line SL is composed of a column of transistors in series, and a word line WL corresponding to the column of transistors is connected to the gate of the column of transistors to control the switching state of the column of transistors. When the array of the application works, the column of transistors where the accessed device is located is turned on, and the transistors of the remaining columns are turned off; the SL and the bit line BL where the device is located apply corresponding access or operation voltages, and the voltages of the non-selected BL and SL remain consistent, so that any device in the array can be accessed. Correspondingly, a plurality of BLs are simultaneously selected or a plurality of SLs are simultaneously selected to realize parallel access. By using the application, the storage density of the 1T1R array can be improved to the level of the current 3D-Nand Flash memory, which is much higher than the current 1T1R array density.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and CMOS hybrid integrated circuit technology, specifically relating to an array architecture based on emerging memory that is compatible with existing CMOS processes and integrated with CMOS, and its fabrication method. Background Technology

[0002] With the rapid development of information technology, the amount of data in modern society is growing exponentially. In order to efficiently store, access, and compute such massive amounts of data, novel memory types such as resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM) have received widespread attention and research.

[0003] The array architectures of these new types of memories can generally be divided into three categories: 1R, 1S1R, and 1T1R. 1R arrays refer to crossbar or crosspoint arrays composed of memory cells themselves. Although this type of array can achieve high-density stacking in terms of structure, it has various problems such as leakage paths and write crosstalk, and is not suitable for large-scale arrays in principle.

[0004] The 1S1R array, based on the 1R array, adds a selector in series with each memory cell, which can suppress leakage paths and crosstalk to some extent. However, the material system of the selector is complex and fluctuates greatly, and the selector increases the read voltage threshold of the memory, while leakage current of the half-selector is still serious. These problems limit the practical application of the 1S1R array.

[0005] 1T1R arrays are currently the most common array architecture. In this type of array, transistors are used as the gating units for the memory, completely shutting off leakage paths. However, the density of current 1T1R arrays is limited by the transistor density, and it is difficult to form a three-dimensional stacked structure like 1S1R and 1R arrays. Summary of the Invention

[0006] To improve the storage density of 1T1R array architectures for novel memory types such as resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM), this invention proposes a three-dimensional 1T1R array architecture and its fabrication method. This method can increase the storage density of the 1T1R array to a level comparable to, and far exceeding, current 3D-Nand Flash memory densities.

[0007] The technical solution of the present invention is as follows:

[0008] A three-dimensional 1T1R array is characterized by comprising upper and lower alternating isolation dielectric layers and memory-bit line layers, as well as several vertical structures. The center of each vertical structure is a gate material of a transistor, which is wrapped by dielectric layers and channel materials to form a series-connected column of transistors. This column of transistors serves as the source line SL of the three-dimensional 1T1R array. One end of the memory in each memory-bit line layer is connected to the source line SL, and the other end of the memory is connected to the bit line BL. A word line WL is provided to connect to the gate of the column of transistors to control the switching state of the column of transistors. When the array is working, the transistor in the column containing the accessed memory is turned on, and the transistors in the other columns are turned off. The source line SL and the bit line BL where the device is located are applied with corresponding access or operation voltages, and the voltage of the non-selected bit line BL is consistent with that of the source line SL.

[0009] Meanwhile, the present invention also provides a method for fabricating a three-dimensional 1T1R array, comprising the following steps:

[0010] 1) Fabricate alternating isolation dielectric layers and bit line structures on a substrate;

[0011] 2) Photolithography etching of the alternating layers prepared in 1) forms several vertical vias;

[0012] 3) Erosion of the bit line edge to form a groove;

[0013] 4) A memory material layer is prepared within the groove to form a memory structure;

[0014] 5) Erode away redundant connections in the memory structure to isolate each memory cell;

[0015] 6) Fabricating transistor channel material within vertical vias;

[0016] 7) Grow the transistor gate dielectric layer material on the inner wall of the transistor channel material in step 6);

[0017] 8) Fabricate the gate material of the transistor at the center of the vertical via to complete the vertical structure.

[0018] Furthermore, in step 1) above, the isolation dielectric layer is preferably silicon oxide (SiO2) or a low dielectric constant material (Low-K dielectric), such as porous SiO2, porous SiCOH, etc. The preferred preparation process is plasma-enhanced chemical vapor deposition (PECVD), and the dielectric layer thickness is 10-1000 nm.

[0019] Furthermore, in step 1) above, the preferred materials for the median line are tantalum (Ta), titanium (Ti), hafnium (Hf), iridium (Ir), or doped polycrystalline silicon. The preferred preparation process is physical vapor deposition (PVD) or plasma-enhanced chemical vapor deposition (PECVD), and the dielectric layer thickness is 10-1000 nm.

[0020] Furthermore, in step 2) above, the etching process is preferably RIE, ICP, etc. In steps 3) and 5) above, the etching process is preferably wet etching.

[0021] Furthermore, in step 4) above, the memory is preferably resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive memory (MRAM), or ferroelectric memory (FeRAM). For resistive random access memory, the preferred materials are tantalum (Ta), tantalum oxide (TaOx), titanium (Ti), titanium oxide (TiOx), hafnium (Hf), and hafnium oxide (HfOx). The preferred fabrication process is oxidation or atomic layer deposition (ALD). For phase change memory, the preferred material is germanium-antimony-tellurium alloy (GeTeSb), and the preferred fabrication process is ALD. For magnetoresistive memory, the preferred materials are magnesium oxide (MgO) and aluminum oxide (AlOx), and the preferred fabrication process is ALD. For ferroelectric memory, the preferred materials are hafnium zirconium oxide (HfZrO) and hafnium aluminum oxide (HfAlO), and the preferred fabrication process is ALD.

[0022] Furthermore, the channel material in step 6) above is preferably IGZO, doped polycrystalline silicon, or other similar materials, and the preparation process is preferably plasma-enhanced chemical vapor deposition (PECVD).

[0023] Furthermore, the gate dielectric material in step 7) above is preferably HfO2, SiO2, etc., and the preparation process is preferably atomic layer deposition, chemical vapor deposition (CVD), and thermal oxidation.

[0024] Furthermore, the gate material in step 8) above is preferably doped polycrystalline silicon, and the fabrication process is preferably PECVD.

[0025] The present invention has the following advantages:

[0026] In the three-dimensional 1T1R array proposed in this invention, each source line SL consists of a column of transistors connected in series, with a corresponding word line WL connected to the gate of this column of transistors to control its switching state. When the array is operating, the transistors in the column containing the accessed device are turned on, while the transistors in the other columns are turned off. Appropriate access or operation voltages are applied to the SL and bit lines BL of the device; the voltages of non-selected BL and SL remain consistent, allowing access to any device in the array. Correspondingly, multiple BLs or multiple SLs can be selected simultaneously to achieve parallel access. Using this invention, the storage density of the 1T1R array can be increased to a level comparable to current 3D-Nand Flash memories, far exceeding the current 1T1R array density. Attached Figure Description

[0027] Figure 1 This is the circuit schematic diagram of the present invention.

[0028] Figure 2This is a vertical structural cross-sectional view of the present invention:

[0029] Figure 3 This is a horizontal structural cross-sectional view of the present invention;

[0030] Figure 4 This is the correspondence between the structure and the schematic diagram of the present invention;

[0031] Figures 5 to 13 This is a schematic diagram of the process preparation of the present invention;

[0032] Figure 5 This represents the growth process of multilayer stacked dielectric layers and bit lines;

[0033] Figure 6 This indicates that a vertical deep hole structure is formed after photolithography etching.

[0034] Figure 7 This indicates the bitline structure erosion process;

[0035] Figure 8 This describes the process of growing and fabricating the memory structure.

[0036] Figure 9 Representing the process of erosion isolation memory structure

[0037] Figure 10 This indicates the process of growing and preparing transistor channel materials.

[0038] Figure 11 This indicates the process of growing and preparing transistor gate dielectric materials.

[0039] Figure 12 This indicates the process of growing and preparing transistor gate materials.

[0040] Figure 13 This describes the process of fabricating a memory using the method of oxidizing bit lines.

[0041] Figure 14 yes Figure 2 — Figure 13 Legend of the diagram. Detailed Implementation

[0042] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0043] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

[0044] Figure 1This is a schematic diagram of the architecture of this invention. (For example...) Figure 1 As shown, the 1T1R array proposed in this invention includes upper and lower alternating isolation dielectric layers and memory-bit line layers, as well as several vertical structures. The center of each vertical structure is the gate material of a transistor, which is encased by dielectric layers and channel materials to form a series-connected column of transistors. This column of transistors serves as the source line SL of the three-dimensional 1T1R array. One end of the memory in each memory-bit line layer is connected to the source line SL, and the other end is connected to the bit line BL. A word line WL is also provided, connected to the gate of the column of transistors, controlling the switching state of that column. When the array is operating, the transistors in the column containing the accessed device are turned on, while the transistors in the other columns are turned off. Appropriate access or operation voltages are applied to the SL and BL of the device; the voltages of non-selected BL and SL remain consistent. Through this operation method, any device in the array can be accessed. Correspondingly, multiple BLs or multiple SLs can be selected simultaneously to achieve parallel access.

[0045] Figure 2 This is a schematic cross-sectional view of the structure of the present invention, wherein one end of the vertically oriented multilayer memory is connected to the channel of the vertical transistor, and the other end is connected to the bit line in the horizontal direction. The gate of the transistor is wrapped in a dielectric layer and channel material at the center of the vertical structure. Figure 3 This is a top view of the structure of the present invention. The 1T1R multi-layer vertical structure can achieve high-density arrangement in a horizontal area. Figure 4 This shows the correspondence between the schematic diagram and the structural diagram of this invention. The gate WL at the center of the vertical transistor controls the selection of the entire vertical transistor channel SL, and the memory of each layer can be accessed by the BL of the layer in which it is located.

[0046] Taking a resistive switching memory based on tantalum oxide (TaOx) as an example, the fabrication method of the 1T1R array of the present invention includes:

[0047] 1) Multilayer silicon oxide (SiO2) and tantalum (Ta) stacks are alternately fabricated on a substrate using plasma-enhanced chemical vapor deposition (PECVD) and sputtering, respectively. Figure 5 As shown;

[0048] 2) Deep holes are formed using photolithography and reactive ion etching (RIE), such as... Figure 6 As shown;

[0049] 3) Erosion of the bit line edge to form a groove, such as Figure 7 As shown.

[0050] 4) Fabricate memory material layers to form a memory structure, such as... Figure 8 As shown

[0051] 5) Use wet etching to remove the excessively grown TaOx layer, making the sidewalls smoother, such as... Figure 9 As shown;

[0052] 6) Polycrystalline silicon channels are fabricated using plasma-enhanced chemical vapor deposition (PECVD), such as... Figure 10 As shown;

[0053] 7) Hafnium oxide (HfO2) is deposited as the gate dielectric layer using ALD, such as... Figure 11 As shown;

[0054] 8) Polysilicon gates are deposited using PECVD, such as... Figure 12 As shown.

[0055] Steps 3) and 4) above can utilize the tantalum Ta on the sidewalls of the deep hole to form a tantalum oxide TaOx layer, thereby forming a memory, such as... Figure 13 As shown.

[0056] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A three-dimensional 1T1R array, characterized in that, The array includes alternating upper and lower isolation dielectric layers and memory-bit line layers, as well as several vertical structures. The center of each vertical structure is the gate material of a transistor, which is wrapped by dielectric layers and channel materials to form a series of transistors. This series of transistors serves as the source line SL of a three-dimensional 1T1R array. One end of the memory in each memory-bit line layer is connected to the source line SL, and the other end of the memory is connected to the bit line BL. A word line WL is also provided to connect to the gate of the column of transistors to control the switching state of the column of transistors. When the array is working, the transistors in the column containing the accessed memory are turned on, and the transistors in the other columns are turned off. Access or operation voltages are applied to the source line SL and the bit line BL where the device is located. The voltages of the non-selected bit line BL and the source line SL are kept consistent.

2. The three-dimensional 1T1R array as described in claim 1, characterized in that, The isolation dielectric layer is silicon oxide (SiO2) or a low dielectric constant material, and the thickness of the isolation dielectric layer is 10-1000 nm.

3. The three-dimensional 1T1R array as described in claim 1, characterized in that, The bit line material is tantalum (Ta), titanium (Ti), hafnium (Hf), iridium (Ir), or doped polycrystalline silicon.

4. The three-dimensional 1T1R array as described in claim 1, characterized in that, The memory is a resistive switching memory, a phase-change memory, a magnetoresistive memory, or a ferroelectric memory.

5. The three-dimensional 1T1R array as described in claim 1, characterized in that, The channel material is IGZO and doped polycrystalline silicon.

6. The three-dimensional 1T1R array as described in claim 1, characterized in that, The dielectric layer is HfO2 or SiO2.

7. The three-dimensional 1T1R array as described in claim 1, characterized in that, The gate material is doped polycrystalline silicon.

8. A method for fabricating a three-dimensional 1T1R array as described in claim 1, comprising the following steps: (1) An alternating upper and lower isolation dielectric layer and bit line structure are prepared on a substrate; (2) The alternating layers prepared in the photolithography etching step (1) form several vertical through holes; (3) Etch the edge of the bit line to form a groove; (4) A memory material layer is prepared in the groove to form a memory structure; (5) Erode away redundant connections in the memory structure to isolate each memory cell; (6) Fabricating transistor channel material within vertical vias; (7) Grow the transistor gate dielectric layer material on the inner wall of the transistor channel material in step (6); (8) Prepare the gate material of the transistor at the center of the vertical via to complete the vertical structure.

9. The method for fabricating a three-dimensional 1T1R array as described in claim 8, characterized in that, Steps (3) and (4) are combined to prepare a memory structure from the chemical reaction products of bit line materials.

10. The method for fabricating a three-dimensional 1T1R array as described in claim 8, characterized in that, The preparation process in step (1) is physical vapor deposition (PVD) or plasma-enhanced chemical vapor deposition (PECVD).

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