RF power detector

Abstract

The RF power detector controls the amplitude of the replica input signal so that the power of the replica input signal is substantially equal to the power of the input signal to the RF power detector. The signal generator generates the replica input signal in response to a digital control word. The feedback circuit adjusts the digital control word in response to a comparison of the output signal from the analog power sensor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Patent Application No. 17 / 207121, filed March 19, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This application relates to radio frequency applications, and more specifically, to radio frequency (RF) signal power detectors. Background Technology

[0004] RF transceivers can use RF power detectors to monitor both transmit (TX) and receive (RX) signal power. For example, a base station can allocate specific transmit power to a user equipment (UE), such as a cellular phone, to prevent uplink signals from that UE from interfering with transmissions from other UEs. By using an RF power detector to monitor transmit signal power, the UE can ensure that it is transmitting using the allocated signal power. Similarly, RF receivers can use RF power detectors to control their automatic gain control (AGC) level.

[0005] Although RF power detection is required in both the TX and RX paths, the performance of existing RF power detectors may be limited by a number of issues, such as DC offset, limited dynamic range, and variations in conversion characteristics (RF power levels are measured to form corresponding digital outputs) at process, voltage, and temperature (PVT) angles. Summary of the Invention

[0006] A power detector is disclosed, comprising: an analog power sensor; a comparator configured to compare a first power signal from the analog power sensor with a second power signal; a signal generator configured to generate a replica input signal with amplitude in response to a digital control word; and feedback logic circuitry configured to generate a digital control word in response to an output signal from the comparator.

[0007] Furthermore, a power detection method is disclosed, comprising: during a first phase of a clock signal, passing a radio frequency input signal through an analog power sensor to generate a first power signal; during a second phase of the clock signal, generating a duplicate input signal in response to a digital control word; passing the duplicate input signal through the analog power sensor to generate a second power signal; and adjusting the digital control word to measure the power of the radio frequency input signal. Additionally, a power detector is disclosed, comprising: an analog power sensor; a switching network configured to: pass an input signal to the analog power sensor during a first phase of operation and to pass a duplicate input signal to the analog power sensor during a second phase of operation; a signal generator configured to generate the duplicate input signal in response to a digital control word; and a feedback circuit configured to generate the digital control word.

[0008] Finally, a power detector is disclosed, comprising: an analog power sensor; a signal generator configured to generate a duplicated input signal in response to a digital control word; a switching network configured to: pass the input signal to the analog power sensor during a first phase of operation and to pass the duplicated input signal to the analog power sensor during a second phase of operation; and an analog-to-digital converter configured to: digitize a reference power signal from the analog power sensor during the second phase of operation and to digitize a first power signal from the analog power sensor during the first phase of operation.

[0009] These and other advantageous features can be better understood through the following detailed description. Attached Figure Description

[0010] Figure 1 An example RF power detector according to one aspect of this disclosure is illustrated.

[0011] Figure 2A The diagram illustrates a signal generator according to one aspect of the present disclosure, wherein an attenuator attenuates a replicated input signal generated by the signal generator.

[0012] Figure 2B The illustration shows a signal generator according to one aspect of the present disclosure, wherein an attenuator attenuates a reference voltage used for the signal generator.

[0013] Figure 3 The figure illustrates a logarithmic resistive voltage divider with equal decay steps according to one aspect of the present disclosure.

[0014] Figure 4 The figure illustrates a cascaded logarithmic resistor divider having coarse and fine attenuation steps according to one aspect of the present disclosure.

[0015] Figure 5 The illustration shows a transmitter including a power detector according to one aspect of this disclosure.

[0016] Figure 6 This is a flowchart of an example method for power detection according to one aspect of this disclosure.

[0017] The embodiments and advantages of this disclosure can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify one or more of the same elements illustrated in the figures. Detailed Implementation

[0018] One type of RF power detector includes an analog power sensor that converts the measured RF input signal into an analog output signal (e.g., an analog voltage output signal). In this RF power detector, an analog-to-digital converter (ADC) digitizes the analog output signal into a digital output, which is a digital representation of the power of the RF input signal. The analog power sensor can be a square-law detector that produces an analog power signal as a function of the square of the RF input signal. More generally, analog power sensors are used to generate analog power signals that are functions of the RF input signal power or indicate the power level of the RF input signal. However, both the analog power sensor and the ADC may require accurate characterization at the PVT angle, which makes the design of the RF power detector quite complex and adds a burden. Furthermore, the DC offset of the analog power sensor affects its accuracy. However, this paper provides an RF power detector in which the PVT variation of the analog power sensor is substantially insignificant to the resulting power measurement and practically requires no calibration. Figure 1 An example RF power detector 100 is shown. An analog power sensor 105 receives an RF input signal (RFin) via a switch S2, and the power of the RF input signal (RFin) is detected. The analog power sensor 105 includes a detector 135, such as a diode or a metal-oxide-semiconductor field-effect transistor (MOSFET), which converts the RF input signal into an analog first power signal, which is a function of the power of the RF input signal. The analog power sensor 105 may also include a low-pass filter, such as one formed by a series combination of a resistor and a capacitor C1, to filter the first power signal. In the analog power sensor 105, the power signal is a voltage signal, but in alternative embodiments it can be a current signal or a charge signal. More generally, the analog power sensor 105 is used to convert an input signal into a power signal.

[0019] The storage and comparison circuit 110 is used for digitization to compare a first power signal from the analog power sensor 105 with a second power signal to generate a digital output signal. For example, the digital output signal can be a binary output signal, the binary state of which depends on whether the second power signal is greater than or less than the first power signal. Such a digital output signal can be generated in various ways. In one embodiment, the circuit 110 includes a comparator 130 that compares the second power signal with the first power signal stored on capacitor C2. In some embodiments, the comparator 130 receives the second power signal at its positive input terminal and receives the stored first power signal at its negative input terminal. The negative input terminal of the comparator 130 is coupled to the output terminal of the comparator 130 via switch S4. A clock signal from a clock source is used during the clock phase. and clock phase They alternate between each other to control switches S2 and S4. For example, during the clock phase. This can correspond to the time when the clock signal is asserted as the supply voltage, and the clock phase. This can correspond to the time when the clock signal is grounded, but these clock phases can be reversed in alternative implementations. Since both switches S2 and S4 are configured to be in the clock phase... The period is closed, therefore the clock phase This can be considered a sampling phase. Therefore, during the sampling phase, the RF input signal is coupled through switch S2 to be converted by the analog power sensor 105 into a first power signal received at comparator 130. Since switch S4 is closed, feedback through comparator 130 makes the signal stored on capacitor C2 equal to the first power signal. Therefore, the RF input signal power is sampled during the sampling phase to be stored as a first power signal across capacitor C2. It should be understood that comparator 130 during the clock phase... During this period, it is used as an operational amplifier to establish a virtual ground between its inverting and non-inverting input terminals. For this purpose, the terms "comparator" and "operational amplifier" are used interchangeably herein. However, it should be understood that in alternative embodiments, comparator 130 can be strictly a comparator. During the clock phase... The voltage stored in the intermediate capacitor C2 includes not only the first power signal but also the DC offset of comparator 130. As will be further described herein, this DC offset occurs during the clock phase. The period was effectively eliminated.

[0020] With clock phase In comparison, clock phase This can be considered a measurement or detection clock phase. During the measurement phase, both switches S2 and S4 are open, and switch S3 is closed so that the first power signal can be measured by comparison with the second power signal. Switch S3 is coupled between the signal generator 120 and the input terminal of the analog power sensor 105. Therefore, during the measurement phase, the analog power sensor 105 is used to detect the input power of the replicated input signal 145 generated by the signal generator 120. The feedback logic circuit 115 controls the signal generator 120 via a digital control word 125 to increase or decrease the amplitude of the replicated input signal 145 such that the power of the replicated input signal 145 is substantially equal to the power of the RF input signal sampled and stored on the capacitor C2. The feedback logic circuit 115 can be implemented using a state machine, microcontroller, microprocessor, or other suitable digital logic circuit. The signal generator 120 responds to the digital control word 125 to generate the replicated input signal 145. For example, in one implementation, signal generator 120 may attenuate a reference signal, such as a reference voltage Vref, in response to digital control word 125 to form a replicated input signal 145. During the clock phase... During this period, comparator 130 compares the second power signal from analog power sensor 105 with the stored voltage on capacitor C2 minus the DC offset voltage. Therefore, the DC offset voltage of comparator 130 during the clock phase... and The spaces between them are eliminated.

[0021] The replicated input signal 145 from signal generator 120 oscillates according to a signal frequency that does not need to match the frequency of the RF input signal. It is convenient if the replicated input signal 145 oscillates from a low value (e.g., ground) to a high value in the manner of a digital clock signal, the high value being equal to the reference voltage Vref multiplied by a scaling constant adapted by feedback logic circuitry 115. The reference voltage Vref can have an amplitude greater than the maximum expected amplitude of the RF input signal. Based on feedback from feedback logic circuitry 115, signal generator 120 then reduces the amplitude of its replicated input signal 145 so that the signal power of the replicated input signal 145 is substantially equal to the power of the RF input signal sampled and stored on capacitor C2.

[0022] In one implementation, the feedback logic circuit 115 can function similarly to the control in a successive approximation register (SAR) analog-to-digital converter. For example, suppose the signal generator 120 can adjust the amplitude of its output signal across a 3-bit dynamic range. Therefore, there will be eight possible attenuation values ​​applied relative to the amplitude of the reference voltage signal Vref. The feedback logic circuit 115 can then begin the detection process by selecting an intermediate level value of the output signal amplitude (such as 1 / 2Vref). The comparator 130 will then indicate whether this initial value is too large (the comparator output is binary 0) or too small (the comparator output is binary 1). Suppose the comparison indicates that the amplitude of 1 / 2Vref is too small. The feedback logic circuit 115 can then increase the amplitude of the replicated input signal 145 to a higher value, such as 3 / 4Vref. If the initial comparison indicates that 1 / 2Vref is too large, the same type of successive approximation will occur, but in this case, the feedback logic circuit 115 can continuously decrease the amplitude of the replicated input signal 145. It should be understood that, in alternative embodiments, the number of bits in the dynamic range of signal generator 120 may be greater than or less than 3 bits. For example, in some embodiments, digital control word 125 may be a binary signal. Therefore, in such an embodiment, the replicated signal power will have two possible values: a low value and a high value, with the high value being greater than the low value. The measurement phase may then begin when analog power sensor 105 senses the low power value of replicated input signal 145. If the comparison of comparator 130 indicates that the RF input signal power is less than the low power value of replicated input signal, the measurement phase is complete. However, if the comparison indicates that the RF input signal power is greater than the low value, the measurement phase continues, where digital control word 125 forces signal generator 120 to generate replicated input signal 145 with a higher power value. After analog power sensor 105 senses the high power value to generate a corresponding power signal, comparator 130 again compares the power signal with the stored power signal to determine whether the RF input signal power is greater than the higher value. Therefore, it should be understood that the resulting measurement phase has a 1.5-bit dynamic range because the RF input signal power is determined to be: 1) below a low value, 2) between a low and a high value, or 3) above a high value. Digital control of the attenuation of the signal generator 120 via feedback logic circuit 115 advantageously provides an inherent digitization of the output power measurement result. For example, digital control word 125 can also be used as a digital power output or measurement result 150 from the RF power detector 100 of the RF input signal power.

[0023] To balance the input impedance and loading of the RF input signal, the RF input signal can be coupled to the replicated analog power sensor 140 via switch S1. Switch S1 is configured to operate during the measurement clock phase. During the period of closure, and in the sampling clock phase The connection is interrupted during this period. The replicated analog power sensor 140 is configured to provide the same load (same input impedance) to the RF input signal as the analog power sensor 105. The analog power sensor 105 operates during the sampling clock phase. During this period, the RF input signal is loaded by closing switch S2, and then during the measurement clock phase. During this period, it is isolated from the RF input signal by opening switch S2. Then, during the measurement clock phase... During this period, the analog power sensor 140 applies the same load by closing switch S1 to subject the RF input signal to a constant load.

[0024] Referring again to the RF power detector 100, note that in an alternative embodiment, the storage and comparison circuitry 110 can instead be an analog-to-digital converter (ADC) 110. In this embodiment, the ADC 110 digitizes the analog power signal from the analog power sensor 105 to form a digital value. Therefore, no capacitor is needed to store this digital value. Alternatively, the ADC 110 may include a digital memory. In one ADC embodiment, the clock phase... This causes the ADC 110 to store the digitized value of the RF input signal power. During the clock phase... In this implementation, ADC 110 stores the digitized value of the replicated signal power. Therefore, feedback logic 115 can function as previously described to adjust digital control word 125 until the digitized value of the replicated signal power is substantially equal to the digitized value of the RF input signal power. In another ADC implementation, the clock signal is in the clock phase... and The oscillations between them are not used. For example, during the initialization phase when switch S3 is closed and switch S2 is open, feedback logic 115 can sweep through all possible values ​​of digital control word 125. Therefore, the duplicated input signal 145 will be similarly swept through all its possible amplitudes and converted into a corresponding reference (second) power signal by analog power sensor 105. ADC 110 digitizes all these reference power signals and stores the resulting digitized reference power signal. Subsequent measurement phases can continuously measure the RF input signal power by keeping switch S2 closed and switch S3 open. For each measurement during the measurement phase, the RF input signal passes through analog power sensor 105 to form an input power signal, which is digitized by ADC 110 into a digitized input power signal. Feedback logic 115 can then compare this digitized input power signal with the stored digitized reference power signal and form a digital power output 150 by setting the digital power output 150 to be equal to the digital control word 125, which produces the stored digitized reference power signal closest to the digitized input power signal.

[0025] As previously mentioned, another approach to RF signal power detection involves using an analog power sensor and an ADC. Since analog power sensors and ADCs are prone to PVT variations, they typically require careful characterization to compensate for these variations. In the RF power detector 100, the need for accuracy and robustness against PVT variations is instead placed on the signal generator 120. However, maintaining accurate signal generation of the replicated input signal 145 by the signal generator 120 can be more easily or cost-effectively implemented and designed compared to maintaining the accuracy of the analog signal generator and ADC combination. For example, attenuation within the signal generator 120 can be based on a resistor divider or a capacitor divider. In a resistor divider, attenuation is based on the ratio of the resistances of the corresponding resistors. Although these resistors will experience PVT variations, each resistor will typically exhibit the same PVT variation in the resulting resistance ratio of the resistor divider. Therefore, the voltage division of the resistors in a resistor divider essentially eliminates the PVT variation. Similarly, the individual capacitors in a capacitor divider exhibit similar PVT variations, thus essentially eliminating the PVT variation of the capacitor divider as well.

[0026] exist Figure 2AExample signal generator 200 is shown in more detail below. Attenuator 220 can be used for attenuation using resistor divider or capacitor divider. Reference voltage Vref is used as the supply voltage for inverter 210, which inverts the oscillation signal 215 to provide input signal 225 to attenuator 220. In an alternative embodiment, inverter 210 can be replaced by a buffer or another suitable circuit (such as an amplifier). Thus, inverter 210 is an example of circuitry that converts oscillation signal 215 into a converted oscillation signal that oscillates between ground and reference voltage Vref. Therefore, input signal 225 will oscillate between ground (or some suitable low voltage) and reference voltage Vref at the frequency of oscillation signal 215. Attenuator 220 attenuates input signal 225 in response to digital control word 125 to produce a replicated input signal 145. While signal generator 200 is advantageously robust to PVT variations, the oscillation of input signal 225 at the frequency of oscillation signal 215 means that parasitic effects within attenuator 220 may affect the accuracy of operation.

[0027] Figure 2B The alternative signal generator 205 shown uses attenuator 220 to attenuate the reference voltage Vref in response to digital control word 125 to form an attenuated DC voltage 230. Attenuator 220 then operates in DC, effectively eliminating parasitic effects. Oscillator signal 215 (e.g., a source clock signal) and an inverted version of oscillation signal 215 from inverter 210 control the switching of switches S6 and S5 to convert the attenuated voltage 230 into a replicated input signal 145. During the first phase of oscillation signal 215, switch S6 is closed and switch S5 is open, causing the attenuated voltage 230 to pass through switch S6 to form a high state for replicated input signal 145. During the second phase of oscillation signal 215, switch S6 is open and switch S5 is closed. Switch S5 is coupled between ground and the node used for replicated input signal 145. Therefore, replicated input signal 145 is grounded when switch S5 is closed. Since the oscillation signal 215 oscillates at its source clock signal frequency, the replicated input signal 145 oscillates between ground and the attenuation voltage 230 at the same source clock signal frequency. Therefore, the signal generator 205 is not only robust to PVT variations, but will also have accurate attenuation in the attenuator 220, because the attenuator 220 only attenuates the DC reference voltage Vref in the signal generator 205.

[0028] The following discussion will illustrate some resistor divider implementations used for attenuator 220. For example, attenuator 220 can be implemented as follows: Figure 3The implementation is as shown in the logarithmic resistive voltage divider ladder 300. The digital control word 125 controls the switch network 305 ranging from the initial switch S7 to the Nth switch SN, where N is a complex positive integer. Except for the initial switch S7, each switch is coupled to a corresponding rung of the resistive voltage divider ladder 300. For example, switch S8 is connected from the node for attenuating voltage 230 to the input node 310 for the corresponding resistor Rb (which is connected to ground). Another switch S9 is connected from the node for attenuating voltage 230 to the input node 311 for the corresponding resistor Rb, and so on for the remaining switches (except for input switch S7). Corresponding resistors Ra are connected between adjacent input nodes. The initial resistor Ra is connected between node 310 and the input node for the reference voltage Vref. Therefore, since the resistor divider ladder 300 divides the reference voltage Vref in response to the digital control word 125 to form the attenuated voltage 230, the resistor divider ladder 300 serves as the attenuator 220 in the signal generator 205. However, it should be understood that the resistor divider ladder 300 can alternatively be used to divide the input signal 225 to form a replicated input signal 145, as discussed with respect to the signal generator 200.

[0029] The load resistor Rload is connected in parallel with the resistor Rb for the step controlled by the Nth switch SN. If the resistance of resistor Ra is equal to the coefficient (1-α) multiplied by the resistance Rload of resistor Rload, and the resistance of resistor Rb is equal to the ratio α / (1-α) multiplied by the resistance Rload, where 0≤α≤1, then it can be shown that the attenuation voltage 230 is equal to αn multiplied by the reference voltage Vref, where n is the number of steps whose switches are closed starting from switch S7 (where n=0). The lower the position of the closed switch, the greater the attenuation. For the special case where α equals 1 / 2, the resistor divider step 300 becomes an R-2R step providing attenuation in 6dB steps. Resistor Rb is then equal to Rload, and resistor Ra is 1 / 2Rload. In this case, the attenuation voltage 230 in decibels (dB) is equal to the decibel level (Vref_dB) of the reference voltage Vref minus 6n. For example, if switch S8 is closed, the attenuation will be 6dB. If switch S9 is closed, the attenuation is 12 dB. As the position of the closed switch moves down the chain, the attenuation continues to increase in increments of 6 dB. However, if the initial switch S7 is closed, there is no attenuation, such that the attenuated voltage 230 equals the reference voltage Vref (corresponding to an attenuation of 6n, where n is 0).

[0030] When parameter α is changed, the dB increment of attenuation from the resistive voltage divider ladder 300 changes accordingly. (Return to reference) Figure 1Note that the RF power detector 100 may need to operate across a relatively wide dynamic range. To accommodate this wide dynamic range, the dB increments of attenuation can be relatively large, such as the 6 dB example discussed, to keep the number of steps manageable while still providing a large dynamic attenuation range. However, the accuracy of power determination may be limited by relatively coarse attenuation step sizes. For a given power level of the RF input signal, comparator 130 may simply indicate that, for the first value of digital control word 125 and the corresponding setting of attenuation in signal generator 120, the power level of the RF input signal is less than the power of the replicated input signal 145. At subsequent increments of attenuation controlled by the second value of digital control word 125, the power level of the RF input signal may become greater than the power of the replicated input signal 145. In this example, the power level of the RF input signal lies somewhere between the power indicated by the first value of digital control word 125 and the power indicated by the second value of digital control word 125. Therefore, the maximum uncertainty in power determination is equal to the attenuation increment (in dB). To increase the accuracy of power determination, the dB increments of attenuation can be made smaller.

[0031] To achieve a larger dynamic range and improved accuracy, methods such as... Figure 4 The cascaded resistor divider ladder 400 is shown. As the name "cascaded" implies, the resistor divider ladder 400 subdivides attenuation across multiple sub-ladders, each sub-ladder having a different magnitude for the attenuation increment. For example, the resistor divider ladder 400 has a first sub-ladder 415 that attenuates a reference voltage Vref to provide a first attenuated voltage at output node 405. The first attenuated voltage is used as the input voltage of a second sub-ladder 420, which can further attenuate the first attenuated voltage to a second attenuated voltage at output node 410. A third resistor sub-ladder 425 can attenuate the second attenuated voltage to form an attenuated voltage 230. Note that the attenuation increment of each successive sub-ladder is independent of the attenuation increment of the previous sub-ladder. Therefore, the order of the attenuation increment magnitudes across the sub-ladders does not need to be decreasing, but can be increasing or randomized in other implementations.

[0032] Each of the sub-ladders 415, 420, and 425 can be implemented as discussed for the resistor divider ladder 300. However, the resistors Ra and Rb in sub-ladders 415, 420, and 425 are adapted according to the desired cascading. For example, sub-ladder 415 can be configured to provide a relatively coarse increment of attenuation, such that sub-ladder 415 constructs its ladder stages with resistors Ra1 and Rb1, which have resistances that provide the desired relatively coarse attenuation step size. Similarly, sub-ladder 420 uses resistors Ra2 and Rb2, such that sub-ladder 420 can provide a finer attenuation step size. Finally, sub-ladder 425 uses resistors Ra3 and Rb3 to provide an even finer attenuation step size. For example, suppose the desired accuracy of the power measurement in the RF power detector 100 is within 1 dB. Sub-ladders providing relatively fine increments of attenuation (such as sub-ladder 425) can be configured accordingly to provide such 1 dB increments of attenuation. Sub-ladder 420 can also be configured to provide attenuation increments of 2 dB, while sub-ladder 415 can be configured to provide attenuation increments of 6 dB. It should be understood that, in alternative embodiments, the number of sub-ladders and their corresponding attenuation increments can vary.

[0033] The power detector disclosed herein can be incorporated into a transmitter, receiver, or transceiver. Figure 5 An example transmitter 500 for a cellular phone is shown. A modem 505 generates a digital baseband signal, which is converted into an analog baseband signal by a digital-to-analog converter (DAC) 510. A mixer 515 upconverts the analog baseband signal into an RF signal. It should be understood that multiple upconversion stages, such as those represented by mixer 515 in a heterodyne architecture, can be used. A power amplifier (PA) 520 amplifies the RF signal to form an amplified RF signal transmitted through an antenna (or an array of antennas). A power detector 525, as disclosed herein, samples the amplified RF signal, such as through a directional coupler (not shown), to generate a digital output signal representing a measured power of the amplified RF signal. The modem 505 adjusts the power amplification of the power amplifier 520 in response to the digital output signal so that the transmitted RF signal has a desired transmit power. In an alternative embodiment, the power detector 525 may alternatively (or additionally) detect the power of the intermediate frequency signal in the upconversion chain in the transmitter 500.

[0034] Now about Figure 6The flowchart discusses a method for power detection. The method includes action 600: passing an RF input signal through an analog power sensor to generate a first power signal. Passing the RF input signal through analog power sensor 105 to form a stored voltage in circuit 110 is an example of generating the first power signal in action 600. The method also includes action 605: generating a duplicate input signal in response to a digital control word. The operation of signal generator 120 forming a duplicate input signal 145 is an example of action 605. Furthermore, the method includes action 610: passing the duplicate input signal through an analog power sensor to generate a second power signal. This is achieved by analog power sensor 105 during the clock phase. The formation of a second power signal during this period is an example of action 610. Finally, the method includes action 615: adjusting the digital control word to measure the power of the RF input signal. Adjusting the digital control word 125 by the feedback logic circuit 115 is an example of action 615.

[0035] This disclosure will now be summarized through a series of points:

[0036] Clause 1. A power detector, comprising:

[0037] Analog power sensor;

[0038] A comparator is configured to compare a first power signal from the analog power sensor with a second power signal from the analog power sensor;

[0039] A signal generator is configured to: generate a replicated input signal with amplitude in response to a digital control word; and

[0040] The feedback logic circuit is configured to generate the digital control word in response to the output signal from the comparator.

[0041] Clause 2. The power detector according to Clause 1 further includes:

[0042] A capacitor is configured to store the first power signal as a voltage.

[0043] Clause 3. The power detector according to Clause 2 further includes:

[0044] A switch is coupled between the first terminal of the capacitor and the output of the comparator, wherein the second terminal of the capacitor is coupled to ground.

[0045] Clause 4. The power detector according to any one of Clauses 1-3, wherein the analog power sensor includes a square-law circuit element configured to square the input signal of the analog power sensor to provide a squared output signal.

[0046] Clause 5. The power detector according to Clause 4, wherein the analog power sensor further includes a filter configured to filter the squared output signal to form the first power signal.

[0047] Clause 6. The power detector according to Clause 5, wherein the filter is a low-pass filter.

[0048] Clause 7. The power detector according to any one of Clauses 1-6 further comprises:

[0049] A first switch is coupled between the node for inputting radio frequency (RF) signals and the input of the analog power sensor; and

[0050] A second switch is coupled between the output of the signal generator and the analog power sensor.

[0051] Clause 8. The power detector according to Clause 7, wherein the first switch is configured to close during a first phase of a clock signal and open for a second phase of the clock signal, and wherein the second switch is configured to close during the second phase of the clock signal and open during the first phase of the clock signal.

[0052] Clause 9. The power detector according to any one of Clauses 1-8, wherein the signal generator comprises:

[0053] A circuit, configured to convert an oscillating signal into a converted oscillating signal, said circuit being powered by a reference voltage; and

[0054] An attenuator is configured to attenuate the converted oscillating signal in response to the digital control word to form the replicated input signal.

[0055] Article 10. The power detector according to any one of Articles 1-9, wherein the signal generator comprises:

[0056] An attenuator is configured to attenuate a reference voltage in response to the digital control word to form an attenuated voltage at the signal node;

[0057] A first switch is coupled between the signal node and the output node of the signal generator; and

[0058] The second switch is coupled between the signal node and ground.

[0059] Clause 11. The power detector according to Clause 10, wherein the first switch is configured to close during a first phase of the oscillation signal and open during a second phase of the oscillation signal, and wherein the second switch is configured to close during the second phase of the oscillation signal and open during the first phase of the oscillation signal.

[0060] Clause 12. The power detector according to Clause 10, wherein the attenuator is a resistive voltage divider having multiple steps.

[0061] Clause 13. The power detector according to Clause 12, wherein the resistive voltage divider ladder includes a switch for each of the plurality of ladders.

[0062] Clause 14. The power detector according to Clause 12, wherein the resistive voltage divider ladder includes a plurality of sub-ladders configured to provide a series of attenuation increments for attenuating the reference voltage to form the attenuated voltage.

[0063] Clause 15. A power detector according to any one of Clauses 1-14, wherein the power detector is configured to measure the power of a radio frequency (RF) signal for a transmitter.

[0064] Clause 16. The power detector according to Clause 15, wherein the transmitter is a transmitter for a cellular phone.

[0065] Article 17. A method for power detection, comprising:

[0066] The radio frequency input signal is passed through an analog power sensor to generate a first power signal;

[0067] Responding to a digital control word to generate a copy input signal;

[0068] The copied input signal is transmitted through the analog power sensor to generate a second power signal; and

[0069] Adjust the digital control word to measure the power of the RF input signal.

[0070] Clause 18. The method according to Clause 17, wherein generating the copy input signal in response to the digital word comprises: attenuating a reference voltage signal to generate the copy input signal, and wherein adjusting the digital control word comprises: controlling the attenuation of the reference voltage signal by at least a coarse increment of attenuation and a fine increment of attenuation, the fine increment of attenuation being less than the coarse increment of attenuation.

[0071] Article 19. The method according to any one of Articles 17-18, wherein generating the copy input signal in response to the digital word comprises: attenuating a reference voltage signal to generate the copy input signal, and wherein attenuating the reference voltage signal in response to the digital control word to generate the copy input signal comprises:

[0072] In response to the digital control word, the reference voltage signal is attenuated to form an attenuated voltage; and

[0073] In response to the oscillation signal, the attenuated voltage is alternated between being transmitted and being transmitted to ground to generate the replicated input signal.

[0074] Clause 20. The method according to Clause 19, wherein the oscillating signal has a frequency lower than the frequency of the radio frequency input signal.

[0075] Article 21. A power detector, comprising:

[0076] Analog power sensor;

[0077] A switching network is configured to: pass an input signal to the analog power sensor during a first phase of the clock signal, and pass a copy signal to the analog power sensor during a second phase of the clock signal;

[0078] A signal generator is configured to form the replicated signal in response to a digital control word; and

[0079] Feedback logic circuitry is configured to generate the digital control word.

[0080] Clause 22. The power detector according to Clause 21 further includes:

[0081] The storage and comparison circuit is configured to: store a first power signal from the analog power sensor during the first phase of the clock signal, and is configured to: perform a comparison between the second power signal from the power sensor and the first power signal during the second phase of the clock signal.

[0082] Clause 23. The power detector according to Clause 22, wherein the feedback logic circuit is further configured to generate the digital control word in response to the comparison of the second power signal with the first power signal during the second phase of the clock signal.

[0083] Clause 24. The power detector according to Clause 21, wherein the switching network is further configured to: during the second phase of the clock signal, couple a replica analog power sensor to a node for the input signal.

[0084] Clause 25. The power detector according to Clause 22 further includes a clock source for generating the clock signal.

[0085] Clause 26. The power detector according to Clause 25, wherein the feedback circuit is further configured to: adjust the digital control word during the second phase of the clock signal until the power of the replicated input signal is substantially equal to the power of the input signal.

[0086] Article 27. A power detector, comprising:

[0087] Analog power sensor;

[0088] A signal generator is configured to generate a copy input signal in response to a digital control word;

[0089] A switching network is configured to: transmit an input signal to the analog power sensor during a first phase of operation, and transmit the replicated input signal to the analog power sensor during a second phase of operation.

[0090] An analog-to-digital converter is configured to digitize a reference power signal from the analog power sensor during the second phase of operation and to digitize an input power signal from the analog power sensor during the first phase of operation.

[0091] Clause 28. The power detector according to Clause 27 further includes:

[0092] The feedback logic circuit is configured to scan the digital control word through a series of possible values ​​during the second phase of operation.

[0093] Clause 29. The power detector according to Clause 27, wherein the input signal is an RF signal for a transmitter.

[0094] Clause 30. The power detector according to Clause 27, wherein the input signal is an intermediate frequency signal for the transceiver.

[0095] It should be understood that many modifications, substitutions, and variations can be made to the materials, apparatus, configurations, and methods of using the devices disclosed herein without departing from the scope of this disclosure. Therefore, since the specific embodiments shown and described herein are merely examples of this disclosure, the scope of this disclosure should not be limited to the specific embodiments shown and described, but should be fully equivalent to the scope of the appended claims and their functional equivalents.

Claims

1. A power detector, comprising: Analog power sensor; A comparator is configured to compare a first power signal from the analog power sensor with a second power signal from the analog power sensor; A signal generator is configured to generate a copy input signal with amplitude in response to a digital control word, wherein the second power signal is generated based on the copy input signal; as well as The feedback logic circuit is configured to generate the digital control word in response to the output signal from the comparator.

2. The power detector according to claim 1, further comprising: A capacitor is configured to store the first power signal as a voltage.

3. The power detector according to claim 2, further comprising: A switch is coupled between the first terminal of the capacitor and the output of the comparator, wherein the second terminal of the capacitor is coupled to ground.

4. The power detector of claim 1, wherein the analog power sensor includes a square-law circuit element configured to square the input signal of the analog power sensor to provide a squared output signal.

5. The power detector of claim 4, wherein the analog power sensor further comprises a filter configured to filter the squared output signal to form the first power signal.

6. The power detector according to claim 5, wherein the filter is a low-pass filter.

7. The power detector according to claim 1, further comprising: A first switch is coupled between the node for inputting radio frequency (RF) signals and the input of the analog power sensor; as well as A second switch is coupled between the output of the signal generator and the analog power sensor.

8. The power detector of claim 7, wherein the first switch is configured to close during a first phase of the clock signal and open for a second phase of the clock signal, and wherein the second switch is configured to close during the second phase of the clock signal and open during the first phase of the clock signal.

9. The power detector of claim 1, wherein the signal generator comprises: A circuit is configured to convert an oscillating signal into a converted oscillating signal, the circuit being powered by a reference voltage; as well as An attenuator is configured to attenuate the converted oscillating signal in response to the digital control word to form the replicated input signal.

10. The power detector of claim 1, wherein the signal generator comprises: An attenuator is configured to attenuate a reference voltage in response to the digital control word to form an attenuated voltage at the signal node; A first switch is coupled between the signal node and the output node of the signal generator; as well as The second switch is coupled between the signal node and ground.

11. The power detector of claim 10, wherein the first switch is configured to close during a first phase of the oscillation signal and open during a second phase of the oscillation signal, and wherein the second switch is configured to close during the second phase of the oscillation signal and open during the first phase of the oscillation signal.

12. The power detector of claim 10, wherein the attenuator is a resistive voltage divider having multiple steps.

13. The power detector of claim 12, wherein the resistive voltage divider ladder includes a switch for each of the plurality of ladder stages.

14. The power detector of claim 12, wherein the resistive voltage divider ladder comprises a plurality of sub-ladders configured to provide a series of attenuation increments for attenuating the reference voltage to form the attenuated voltage.

15. The power detector of claim 1, wherein the power detector is configured to measure the power of a radio frequency (RF) signal for a transmitter.

16. The power detector of claim 15, wherein the transmitter is a transmitter for a cellular phone.

17. A method for power detection, comprising: The radio frequency input signal is passed through an analog power sensor to generate a first power signal; Responding to a digital control word to generate a copy input signal; The copied input signal is transmitted through the analog power sensor to generate a second power signal; as well as The digital control word is adjusted based on a comparison of the first power signal and the second power signal to measure the power of the radio frequency input signal.

18. The method of claim 17, wherein generating the copy input signal in response to the digital control word comprises: The reference voltage signal is attenuated to generate the replicated input signal, and the adjustment of the digital control word includes controlling the attenuation of the reference voltage signal by at least a coarse increment of attenuation and a fine increment of attenuation, wherein the fine increment of attenuation is smaller than the coarse increment of attenuation.

19. The method of claim 17, wherein generating the copy input signal in response to the digital control word comprises: Attenuating the reference voltage signal to generate the replicated input signal, wherein attenuating the reference voltage signal in response to the digital control word to generate the replicated input signal includes: In response to the digital control word, the reference voltage signal is attenuated to form an attenuated voltage; and In response to the oscillation signal, the attenuated voltage is alternated between being transmitted and being transmitted to ground to generate the replicated input signal.

20. The method of claim 19, wherein the oscillation signal has a frequency lower than the frequency of the radio frequency input signal.

21. A power detector, comprising: Analog power sensor; A switching network is configured to: pass an input signal to the analog power sensor during a first phase of the clock signal, and pass a duplicated input signal to the analog power sensor during a second phase of the clock signal; A signal generator is configured to form the copy input signal in response to a digital control word; as well as Feedback logic circuitry is configured to generate the digital control word.

22. The power detector according to claim 21, further comprising: The storage and comparison circuit is configured to: store a first power signal from the analog power sensor during the first phase of the clock signal, and is configured to: perform a comparison between the second power signal from the power sensor and the first power signal during the second phase of the clock signal.

23. The power detector of claim 22, wherein the feedback logic circuit is further configured to generate the digital control word in response to the comparison of the second power signal with the first power signal during the second phase of the clock signal.

24. The power detector of claim 21, wherein the switching network is further configured to: couple a replica analog power sensor to a node for the input signal during the second phase of the clock signal.

25. The power detector of claim 22, further comprising a clock source for generating the clock signal.

26. The power detector of claim 25, wherein the feedback logic circuit is further configured to: adjust the digital control word during the second phase of the clock signal until the power of the replicated input signal is substantially equal to the power of the input signal.

27. A power detector, comprising: Analog power sensor; A signal generator is configured to generate a copy input signal in response to a digital control word; A switching network is configured to: transmit an input signal to the analog power sensor during a first phase of operation, and transmit the replicated input signal to the analog power sensor during a second phase of operation. An analog-to-digital converter is configured to digitize a reference power signal from the analog power sensor during the second phase of operation, and to digitize a first power signal from the analog power sensor during the first phase of operation.

28. The power detector according to claim 27, further comprising: The feedback logic circuit is configured to scan the digital control word through a series of possible values ​​during the second phase of operation.

29. The power detector of claim 27, wherein the input signal is an RF signal for a transmitter.

30. The power detector of claim 27, wherein the input signal is an intermediate frequency signal for a transceiver.

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