Method, device and equipment for generating memory description information and storage medium

Abstract

The application provides a memory description information generation method, device, equipment and storage medium. The equipment comprises a memory and a processor. The memory is used for storing processor executable instructions. The processor is used for calling the program instructions in the memory to execute the memory description information generation method. The memory description information generation method, device and equipment provided by the application can generate accurate memory description information, thereby accurately optimizing the memory access in parallel, and effectively improving the program running speed.

Description

Technical Field

[0001] This application relates to the field of computer compilation technology, and in particular to a method, apparatus, device and storage medium for generating memory description information. Background Technology

[0002] Computer compilation refers to translating programs written in high-level languages ​​into executable object code. During compilation, memory access needs to be optimized in parallel to improve program speed. Before performing parallel optimization, alias analysis of each memory node is first performed to generate memory description information for the address space pointed to by each memory node.

[0003] Currently, a common method for generating memory description information is to determine whether the dimension of the target address space is one-dimensional. If the dimension of the target address space is not one-dimensional, then default memory description information is generated. For example, the address space size of the generated default memory description information can be the size of the base address space where the target address space is located.

[0004] However, this default memory description information cannot accurately describe the true attributes of the target address space, thus failing to perform accurate parallel optimization of memory access and effectively improve the program's running speed. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for generating memory description information, which can generate accurate memory description information, thereby enabling accurate parallel optimization of memory access.

[0006] In a first aspect, embodiments of this application provide a method for generating memory description information, including:

[0007] Obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions;

[0008] For target address spaces with different numbers of dimensions, memory description information of the target address space is generated based on the tensor information of the target address space in different dimensions.

[0009] Secondly, embodiments of this application provide a memory access method, including:

[0010] Based on the memory description information of the generated target address space, parallel optimization of memory access is performed on multiple sub-address spaces created with the target address space as the source address space, wherein the memory description information of the target address space is generated using the method described in the first aspect.

[0011] Thirdly, embodiments of this application provide a memory description information generation apparatus, comprising:

[0012] The judgment module is used to obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and to determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions.

[0013] The generation module is used to generate memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions.

[0014] Fourthly, embodiments of this application provide a memory access device, including:

[0015] An optimization module is used to perform parallel optimization of memory access for multiple sub-address spaces created with the target address space as the source address space, based on the generated memory description information of the target address space, wherein the memory description information of the target address space is generated using the apparatus described in the third aspect.

[0016] Fifthly, embodiments of this application provide a processor and a memory communicatively connected to the processor;

[0017] The memory stores computer-executed instructions;

[0018] The processor executes computer execution instructions stored in the memory to implement the method as described in the first or second aspect.

[0019] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described in the first or second aspect.

[0020] In a seventh aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first or second aspect.

[0021] This application provides a method, apparatus, device, and storage medium for generating memory description information. It obtains tensor information of a target address space pointed to by a target memory node in multiple dimensions, and generates memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions. In other words, this application determines the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions, and generates memory description information of the target address space based on the tensor information of the target address space in different dimensions according to the different numbers of dimensions. This allows the generated memory description information to accurately describe the true attributes of the target address space, thereby enabling accurate parallel optimization of memory access and effectively improving program execution speed. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0023] Figure 1 A schematic diagram of a system architecture provided for an embodiment of this application;

[0024] Figure 2 A flowchart illustrating a method for generating memory description information provided in an embodiment of this application;

[0025] Figure 3 A flowchart illustrating yet another method for generating memory description information provided in this application embodiment;

[0026] Figure 4 A flowchart illustrating another method for generating memory description information provided in this application embodiment;

[0027] Figure 5 A flowchart illustrating another method for generating memory description information provided in this application embodiment;

[0028] Figure 6 A schematic diagram illustrating the structure of a first address space and a second address space created using a target address space as the source address space, provided in an embodiment of this application.

[0029] Figure 7 This diagram illustrates, as an example, the parallel optimization of memory access using memory description information generated by a method for generating memory description information based on existing technologies.

[0030] Figure 8 This is a schematic diagram illustrating the parallel optimization of memory access based on the memory description information generated by the method for generating memory description information according to the embodiments of this application;

[0031] Figure 9This is a schematic diagram of the structure of the memory description information generation device provided in the embodiments of this application;

[0032] Figure 10 This is a schematic diagram of the structure of a memory access device provided in an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0034] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0036] When compiling computer programs, memory access needs to be optimized in parallel to improve program execution speed. Before performing parallel optimization, alias analysis (AA) is first performed on each memory node to generate memory description information that describes the attributes of the address space pointed to by each memory node. This allows the compiler to determine whether there is overlap between multiple new address spaces created from the address spaces pointed to by each memory node, and thus whether serial instructions need to be added between the multiple new address spaces during parallel optimization.

[0037] Currently, a common method for generating memory description information is to determine whether the target address space has one dimension. If it does, the memory description information of the target address space is generated based on the tensor information of the first dimension. If not, a default memory description information is generated. For example, the address space size of the generated default memory description information can be the size of the base address space where the target address space is located.

[0038] However, in the above methods for generating memory description information, when the dimension of the target address space is not one-dimensional, the generated default memory description information cannot accurately describe the true attributes of the target address space, thus failing to perform accurate parallel optimization of memory access and consequently failing to effectively improve the program's running speed.

[0039] The method, apparatus, device, and storage medium for generating memory description information provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0040] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram of a system architecture provided in an embodiment of this application, such as... Figure 1 As shown, the Figure 1 The system architecture shown may specifically include target address space 1 and server 2, wherein server 2 is equipped with a memory description information generation device.

[0042] Among them, target address space 1 can be the address space pointed to by the target memory node. The target address space has pre-created tensor information of multiple dimensions. The tensor information of multiple dimensions is used to characterize the data storage structure of the target address space. For example, it can be used to characterize whether the data is stored on "a line", "a plane", "a cube", or even "a multi-dimensional space", as well as the size of the "line", "plane", "cube" or "multi-dimensional space".

[0043] It should be noted that target address space 1 is actually a one-dimensional continuous address space. The multiple dimensions in this application can be understood as abstracting the continuous one-dimensional address space into two-dimensional surfaces, three-dimensional volumes, or even multi-dimensional spaces based on offsets and spans.

[0044] The memory description information generation device can be mounted on server 2. It is used to acquire tensor information of target address space 1 in multiple dimensions and execute the memory description information generation method provided in this application embodiment. Specifically, it determines the number of dimensions of the target address space and generates memory description information of the target address space based on the tensor information of the target address space in different dimensions, according to the different numbers of dimensions. This memory description information is used to describe the attributes of the target address space during the compilation process; that is, it can be memory description information suitable for compilation generated based on tensor information.

[0045] Figure 2 A flowchart illustrating a method for generating memory description information provided in this application embodiment is shown below. Figure 2 As shown, the method for generating memory description information provided in this embodiment includes the following steps:

[0046] Step 201: Obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions.

[0047] Step 202: For target address spaces with different numbers of dimensions, generate memory description information of the target address space based on the tensor information of the target address space in different dimensions.

[0048] It should be noted that the execution entity of the memory description information generation method provided in this embodiment can be a memory description information generation device. In practical applications, this memory description information generation device can be implemented by a computer program, such as application software, or by a medium storing the relevant computer program, such as a USB flash drive or optical disc, or by a physical device integrating or installing the relevant computer program, such as a chip or circuit board.

[0049] In this embodiment, in order to generate accurate memory description information, the memory description information generation device can first obtain the tensor information of the target address space pointed to by the target memory node in multiple dimensions.

[0050] The target memory node can be a memory node with a pre-specified node identifier. Since the central processing unit cannot directly access the address space, access to the address space can be achieved through memory nodes. Each memory node can point to a corresponding address space. The node identifier can include the identifier of the node that can directly access the pointed address space, such as IR_PR, IR_ST, or IR_LD, and the identifier of the node that can indirectly access the pointed address space, such as IR_IST or IR_ILD. Indirect access to the pointed address space can include accessing the address space pointed to by the target memory node after performing one or more operations.

[0051] Accordingly, the pre-specified node identifier can be one or more of the identifiers of nodes that can directly access the pointed address space and / or the identifiers of nodes that can indirectly access the pointed address space. This embodiment does not limit this.

[0052] Furthermore, tensor information may include, but is not limited to, offset, size, and stride. The offset can be an offset relative to the starting address of the base address. The base address can be a pre-declared address range, for example, an address range starting at address 0 and with a length of 1024 bytes; in this case, the offset is the offset relative to that starting address 0. Correspondingly, the tensor information of the target address space in multiple dimensions can include the offset, size, and stride of the target address space in multiple dimensions.

[0053] After obtaining tensor information of the target address space in multiple dimensions, the memory description information generation device can determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions. Optionally, the number of dimensions of the target address space can be determined by: whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one.

[0054] It is understood that there are other ways to determine the dimension of the target address space, and this embodiment does not limit this.

[0055] After determining the number of dimensions of the target address space, the memory description information generation device can generate memory description information for the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions. The memory description information may include, but is not limited to, the base address of the address space, the size of the address space, the type of the address space, and the offset of the address space; the specific generation method is not limited in this embodiment.

[0056] The memory description information generation method provided in this embodiment obtains tensor information of the target address space pointed to by the target memory node in multiple dimensions, determines the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions, and generates memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions. In other words, in this embodiment, the number of dimensions of the target address space is determined based on the tensor information of the target address space in multiple dimensions, and memory description information of the target address space is generated based on the tensor information of the target address space in different dimensions according to the different numbers of dimensions. This allows the generated memory description information to accurately describe the true attributes of the target address space, thereby enabling accurate parallel optimization of memory access and effectively improving program execution speed.

[0057] Based on the above embodiments, in an optional implementation, the tensor information includes size and span. In step 201, determining the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions includes: determining the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one.

[0058] In this embodiment, tensor information may include size and span. Accordingly, the tensor information of the target address space in each dimension may include the size and span of the target address space in each dimension. Then, the memory description information generation device can determine the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant and whether the size value of the target address space in each dimension is one.

[0059] In one example, if the size and span of the target address space in the first to Nth dimensions are constant and the value is not one, it means that the size and span of the target address space in the Nth dimension are fixed values ​​and are greater than one byte. Then the memory description information generation device can determine that the data in the target address space is stored in "N dimensions", that is, the number of dimensions of the target address space is N.

[0060] In another example, if the size and span of the target address space in the first to N-1 dimensions are constant and the value is not one, and the size and span in the Nth dimension are constant and the value is one, it indicates that the size and span of the target address space in the N-1 dimensions are fixed values ​​and are greater than one byte, and the size and span in the Nth dimension are fixed values ​​but only one byte. Then the memory description information generation device can determine that the data in the target address space is stored in "N-1 dimensions", that is, the number of dimensions of the target address space is N-1.

[0061] The memory description information generation method provided in this embodiment accurately determines the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant and whether the size value of the target address space in each dimension is one. This lays the foundation for generating memory description information of the target address space based on the tensor information of the target address space in different dimensions according to the different number of dimensions of the target address space.

[0062] Based on the above implementation method, in an optional implementation method, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first dimension, the second dimension, and the third dimension.

[0063] Accordingly, determining the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one, includes: if the size of the target address space in the second dimension and the third dimension are both constant and the value is one, and the size in the first dimension is constant, then the number of dimensions of the target address space is determined to be one-dimensional; if the size of the target address space in the second dimension is constant and the value is not one, the size in the third dimension is constant and the value is one, and the span in the first dimension is constant, then the number of dimensions of the target address space is determined to be two-dimensional; if the size of the target address space in the second dimension and the third dimension are both constant and the value is not one, and the span in the second dimension is constant, then the number of dimensions of the target address space is determined to be three-dimensional.

[0064] In this embodiment, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first dimension, the second dimension, and the third dimension. Specifically, it may include the size and span of the target address space in the first dimension, the second dimension, and the third dimension.

[0065] In one possible scenario, if the dimensions of the target address space in the second and third dimensions are both constant and have a value of one, and the dimension in the first dimension is constant, it indicates that the size of the target address space in the second and third dimensions is fixed and consists of only one byte. In this case, the memory description information generation device can determine that the data in the target address space is stored on "a line," meaning that the dimension of the target address space is one.

[0066] In another possible scenario, if the target address space has a constant size in the second dimension and a value that is not one, a constant size in the third dimension and a value that is one, and a constant span in the first dimension, then it indicates that the target address space has a fixed size in the third dimension and contains only one byte, a fixed size in the second dimension and contains more than one byte, and a fixed span in the first dimension. In this case, the memory description information generation device can determine that the data in the target address space is stored on "a plane," that is, the target address space has two dimensions.

[0067] In another possible scenario, if the dimensions of the target address space in the second and third dimensions are both constant and their values ​​are not one, and the span in the second dimension is constant, it indicates that the dimensions of the target address space in the second and third dimensions are both fixed values ​​and both are greater than one byte, and the span in the second dimension is a fixed value. In this case, the memory description information generation device can determine that the data in the target address space is stored on "a cube", that is, the target address space has three dimensions.

[0068] The memory description information generation method provided in this embodiment accurately determines the number of dimensions of the target address space when the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions. This is done by determining whether the size or span of the target address space in the three dimensions is constant and whether the size value of the target address space in the three dimensions is one. This lays the foundation for generating memory description information of the target address space based on the tensor information of the target address space in different dimensions according to the different number of dimensions of the target address space.

[0069] Based on the above implementation, in an optional implementation, the memory description information includes the address space size. Accordingly, step 202 specifically includes: if the dimension of the target address space is determined to be one-dimensional, then the size of the target address space in that dimension is determined as the address space size; if the dimension of the target address space is determined to be N-dimensional, then the product of the size of the target address space in the Nth dimension and the span of the target address space in the (N-1)th dimension is determined as the address space size, where N is a positive integer greater than 1; based on the determined address space size, memory description information of the target address space is generated.

[0070] In this embodiment, the memory description information may include the address space size. Specifically, in one possible case, if the memory description information generating device determines that the dimension of the target address space is one-dimensional, it indicates that the size of the target address space in the first dimension is a fixed value and the address space of the target address space is continuous. In this case, the memory description information generating device can determine the size of the target address space in that dimension as the address space size in the memory description information of the target address space.

[0071] In another possible scenario, if the memory description information generating device determines that the target address space has N dimensions, it indicates that the size and span of the target address space in the N dimensions are fixed values ​​and greater than one byte. In this case, the memory description information generating device can determine the address space size in the memory description information of the target address space by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension. Here, N is a positive integer greater than 1.

[0072] After determining the size of the target address space, the memory description information generation device can generate memory description information for the target address space based on the determined address space size. This allows the generated memory description information to accurately describe the true size of the target address space, laying the foundation for accurate parallel optimization of subsequent memory access.

[0073] Based on the above implementation, in an optional implementation, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first, second, and third dimensions. Correspondingly, if the number of dimensions of the target address space is determined to be N, the product of the size of the target address space in the Nth dimension and the span of the target address space in the (N-1)th dimension is used to determine the size of the address space, including:

[0074] If the target address space is determined to have two dimensions, then the product of the size of the target address space in the second dimension and the span of the target address space in the first dimension is determined as the address space size in the memory description information of the target address space.

[0075] If the target address space is determined to have three dimensions, then the product of the size of the target address space in the third dimension and the span of the target address space in the second dimension is determined as the address space size in the memory description information of the target address space.

[0076] In this embodiment, in one possible case, if the memory description information generating device determines that the dimension of the target address space is two-dimensional, it indicates that the size of the target address space in the second dimension is a fixed value and is greater than one byte, and the span in the first dimension is a fixed value. Then, the memory description information generating device can determine the address space size in the memory description information of the target address space by multiplying the size of the target address space in the second dimension by the span of the target address space in the first dimension.

[0077] For example, if the target address space has a size of 8 bytes in the second dimension and a span of 64 bytes in the first dimension, the memory description information generation device can determine the address space size in the memory description information of the target address space by multiplying the 8 bytes and 64 bytes, which is 512 bytes.

[0078] In another possible scenario, if the memory description information generating device determines that the target address space has three dimensions, it means that the size of the target address space in the second and third dimensions are both fixed values ​​and both are greater than one byte, and the span in the second dimension is a fixed value. In this case, the memory description information generating device can determine the address space size in the memory description information of the target address space by multiplying the size of the target address space in the third dimension by the span of the target address space in the second dimension.

[0079] For example, if the size of the target address space in the third dimension is 2 bytes and the span of the second dimension is 512 bytes, the memory description information generation device can determine the address space size in the memory description information of the target address space by multiplying the 2 bytes and 512 bytes, which is 1024 bytes.

[0080] The memory description information generation method provided in this embodiment can determine the address space size of a two-dimensional target address space based on the size of the target address space in the second dimension and the span of the target address space in the first dimension, and determine the address space size of a three-dimensional target address space based on the size of the target address space in the third dimension and the span of the target address space in the second dimension, thereby achieving an accurate description of the target address space.

[0081] Figure 3 A flowchart illustrating another method for generating memory description information provided in this application embodiment is shown below. Figure 3 As shown, based on the above implementation method, the memory description information generation method provided in this embodiment further includes an address space type. Accordingly, step 202 specifically includes the following steps:

[0082] Step 301: If the dimension of the target address space is one dimension, then the address space type is determined to be a fully known type.

[0083] Step 302: If the target address space has N dimensions, determine the address space type by multiplying the span of the (N-1)th dimension by the size of the Nth dimension and the span size of the Nth dimension.

[0084] Step 303: If the span of the (N-1)th dimension multiplied by the size of the Nth dimension is equal to the span of the Nth dimension, then the address space type is determined to be a fully known type.

[0085] Step 304: Otherwise, determine that the address space type is not a fully known type.

[0086] In this embodiment, the memory description information may include the address space type. The address space type may include a fully known type or a non-fully known type. A fully known type refers to an address space size that is known and the address space is contiguous, meaning that the specific access location is known. A non-fully known type refers to an address space size that is known, but the address space is not contiguous, meaning that the specific access location is unknown.

[0087] Specifically, in one example, if the dimension of the target address space is one-dimensional, it means that the size of the target address space in that dimension is a fixed value, and the address space of the target address space is continuous. That is, the size of the target address space is known, and the specific access location is also known. Then the memory description information generation device can determine that the address space type is a fully known type.

[0088] In another example, if the target address space has N dimensions, the memory description information generation device can determine whether the target address space is continuous based on the relationship between the span of the target address space in the (N-1)th dimension multiplied by the size of the Nth dimension and the span of the target address space in the Nth dimension, and thus determine the address space type.

[0089] In one possible scenario, if the span of the target address space in the (N-1)th dimension multiplied by the size of the Nth dimension is equal to the span of the target address space in the Nth dimension, it indicates that the target address space is continuous and the specific access location is known. In this case, the memory description information generation device can determine that the address space type is a fully known type.

[0090] In another possible scenario, if the span of the target address space in the (N-1)th dimension multiplied by the size of the Nth dimension is not equal to the span of the target address space in the Nth dimension, it indicates that the address space of the target address space is not contiguous and the specific access location is unknown. In this case, the memory description information generation device can determine that the address space type is not a fully known type.

[0091] The memory description information generation method provided in this embodiment determines whether the address space of the target address space is continuous based on the relationship between the span of the target address space in the (N-1)th dimension multiplied by the size of the Nth dimension and the span of the target address space in the Nth dimension. This allows for accurate determination of the address space type of the target address space, laying the foundation for accurate parallel optimization of subsequent memory access.

[0092] Based on the above implementation, in an optional implementation, the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions. Accordingly, step 202 specifically includes: if it is determined that the number of dimensions of the target address space is one dimension, then the address space type in the memory description information of the target address space is determined to be a fully known type; based on the determined address space type, the memory description information of the target address space is generated.

[0093] In this embodiment, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first dimension, the second dimension, and the third dimension. Specifically, it may include the size and span of the target address space in the first dimension, the second dimension, and the third dimension.

[0094] Specifically, if the memory description information generation device determines that the dimension of the target address space is one-dimensional, it means that the size of the target address space in the first dimension is a fixed value, and the address space of the target address space is continuous. That is, the size of the target address space is known, and the specific access location is also known. Then the memory description information generation device can determine that the address space type in the memory description information of the target address space is a fully known type.

[0095] After determining the address space type of the target address space, the memory description information generation device can generate memory description information for the target address space based on the determined address space type.

[0096] The memory description information generation method provided in this embodiment, when the target address space has tensor information in multiple dimensions including tensor information in the first, second, and third dimensions, if it is determined that the number of dimensions of the target address space is one-dimensional, then the address space type in the memory description information of the target address space is determined to be a fully known type. Based on the determined address space type, the memory description information of the target address space is generated, so that the generated memory description information can accurately describe the true attributes of the target address space with a one-dimensional dimension, laying the foundation for accurate parallel optimization of memory access in the future.

[0097] Figure 4 A flowchart of another method for generating memory description information provided in the embodiments of this application is shown below. Figure 4 As shown, based on the above implementation method, the method for generating memory description information provided in this embodiment, step 202, further includes the following steps:

[0098] Step 401: If the dimension of the target address space is determined to be two-dimensional, then determine whether the size and span of the target address space in the first dimension are both constants and equal in value.

[0099] Step 402: If yes, then determine that the address space type in the memory description information of the target address space is a fully known type.

[0100] Step 403: If not, then determine that the address space type in the memory description information of the target address space is not a fully known type.

[0101] Step 404: Based on the determined address space type, generate memory description information for the target address space.

[0102] In this embodiment, if the memory description information generation device determines that the dimension of the target address space is two-dimensional, the memory description information generation device can determine whether the address space of the target address space is continuous by judging whether the size and span of the first dimension of the target address space are constant and equal in value, and thus determine the address space type of the target address space.

[0103] In one possible scenario, if the size and span of the target address space in the first dimension are both constant and equal in value, it indicates that the address space of the target address space is continuous, meaning that the specific access location is known. In this case, the memory description information generation device can determine that the address space type in the memory description information of the target address space is a fully known type.

[0104] In another possible scenario, if the size and span of the target address space in the first dimension are constant but the values ​​are not equal, it indicates that the address space of the target address space is not contiguous, that is, the specific access location is unknown. In this case, the memory description information generation device can determine that the address space type in the memory description information of the target address space is not a fully known type.

[0105] After determining the address space type of the target address space, the memory description information generation device can generate memory description information for the target address space based on the determined address space type.

[0106] The memory description information generation method provided in this embodiment, when the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first dimension, the second dimension, and the third dimension, determines the address space type in the memory description information of the target address space based on whether the size and span of the target address space in the first dimension are constant and equal in value. Based on the determined address space type, the memory description information of the target address space is generated, so that the generated memory description information can accurately describe the true attributes of the two-dimensional target address space, laying the foundation for accurate parallel optimization of memory access in the future.

[0107] Figure 5A flowchart of another method for generating memory description information provided in the embodiments of this application is shown below. Figure 5 As shown, based on the above implementation method, the method for generating memory description information provided in this embodiment, step 202, further includes the following steps:

[0108] Step 501: If the target address space is determined to have three dimensions, then determine whether the span of the target address space in the second dimension multiplied by the size of the third dimension is equal to the span in the third dimension.

[0109] Step 502: If yes, then determine that the address space type in the memory description information of the target address space is a fully known type.

[0110] Step 503: If not, then determine that the address space type in the memory description information of the target address space is not a fully known type.

[0111] Step 504: Based on the determined address space type, generate memory description information for the target address space.

[0112] In this embodiment, if the memory description information generation device determines that the target address space has three dimensions, the memory description information generation device can determine whether the address space of the target address space is continuous by judging whether the span of the second dimension multiplied by the size of the third dimension is equal to the span of the third dimension, and thus determine the address space type of the target address space.

[0113] In one possible scenario, if the span of the target address space in the second dimension multiplied by the size of the third dimension equals the span in the third dimension, it indicates that the address space of the target address space is continuous, meaning that the specific access location is known. In this case, the memory description information generation device can determine that the address space type in the memory description information of the target address space is a fully known type.

[0114] In another possible scenario, if the span of the target address space in the second dimension multiplied by the size of the third dimension is not equal to the span in the third dimension, it indicates that the address space of the target address space is discontinuous, that is, the specific access location is unknown. In this case, the memory description information generation device can determine that the address space type in the memory description information of the target address space is not a fully known type.

[0115] After determining the address space type of the target address space, the memory description information generation device can generate memory description information for the target address space based on the determined address space type.

[0116] The memory description information generation method provided in this embodiment, when the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions, determines whether the span of the target address space in the second dimension multiplied by the size of the third dimension equals the span in the third dimension, determines whether the address space of the target address space is continuous, and then determines the address space type of the target address space. Based on the determined address space type, memory description information of the target address space is generated, so that the generated memory description information can accurately describe the true attributes of the three-dimensional target address space, laying the foundation for accurate parallel optimization of memory access in the future.

[0117] After generating the memory description information of the target address space, this application embodiment also provides a memory access method, including:

[0118] Based on the generated memory description information of the target address space, parallel optimization of memory access is performed on multiple sub-address spaces created with the target address space as the source address space, wherein the memory description information of the target address space is generated using the memory description information generation method described in any of the above embodiments of this application.

[0119] It should be noted that the execution subject of the memory access method provided in this embodiment can be a memory access device. In practical applications, this memory access device can be implemented by a computer program, such as application software, or by a medium storing the relevant computer program, such as a USB flash drive or optical disc, or by a physical device that integrates or installs the relevant computer program, such as a chip or circuit board.

[0120] Based on the above embodiments, in an optional implementation, the parallel optimization of memory access for multiple sub-address spaces created with the target address space as the source address space based on the generated memory description information of the target address space includes: determining whether there is overlap between the multiple sub-address spaces created with the target address space as the source address space based on the generated memory description information of the target address space; if so, inserting serial access instructions for the multiple sub-address spaces; if not, not inserting serial access instructions for the multiple sub-address spaces.

[0121] In this embodiment, after the memory description information generation device generates the memory description information of the target address space, the memory access device can perform parallel optimization of memory access on multiple sub-address spaces created with the target address space as the source address space based on the generated memory description information of the target address space.

[0122] Figure 6This application provides a schematic diagram illustrating the structure of a first address space and a second address space created using the target address space as the source address space, as shown in the embodiments of this application. Figure 6 As shown, the target address space is the address space at the base address, which is a 32-bit (4-byte) numeric type with a length of 1024 bytes. The target address space has an offset of 0, a size of 64 bytes, and a span of 64 bytes in the first dimension; an offset of 0, a size of 8 bytes, and a span of 512 bytes in the second dimension; and an offset of 0 and a size of 2 bytes in the third dimension.

[0123] The first address space and the second address space are two sub-address spaces created using the target address space as the source address space. The first address space has an offset of 8 bytes and a size of 64 bytes in the first dimension, an offset of 0 bytes and a size of 3 bytes in the second dimension, and an offset of 0 bytes and a size of 2 bytes in the third dimension. The second address space has an offset of 512 bytes and a size of 64 bytes in the first dimension, an offset of 0 bytes and a size of 3 bytes in the second dimension, and an offset of 0 bytes and a size of 2 bytes in the third dimension.

[0124] For example, if the memory description information of the target address space is generated using the memory description information generation method provided by the prior art, the memory description information generation device determines whether the dimension of the target address space is one-dimensional. Specifically, since the dimensions of the target address space in the second and third dimensions are constants but not 1, the memory description information generation device can determine that the dimension of the target address space is not one-dimensional, and then generate default memory description information. The default memory description information can be determined with the space size of the base address 1024×4, that is, 4096 bytes, as the address space size of the target address space, and the address space type in the memory description information of the target address space is determined to be a non-fully known type. Since a non-fully known type represents that the specific access location is unknown, the space size of the base address 4096 bytes will be determined as the address space size of the first address space and the second address space, respectively.

[0125] However, the actual size of the first address space should be the product of its dimension in the first dimension, its offset in the second dimension, and its offset in the third dimension, which is 64 × 3 × 2 = 384 bytes. Similarly, the size of the second address space should also be the product of its dimension in the first dimension, its offset in the second dimension, and its offset in the third dimension, which is also 64 × 3 × 2 = 384 bytes.

[0126] Figure 7 A schematic diagram illustrating parallel optimization of memory access based on memory description information generated by methods for generating memory description information provided by existing technologies is shown below. Figure 7 As shown, since the memory description information generated by the method of generating memory description information based on the existing technology is inaccurate and is larger than the actual address space size, when performing parallel optimization of memory access, the memory access device will determine that there is an overlap between the first address space and the second address space, and thus insert a serial access instruction for the first address space and the second address space. For example, the serial access instruction can be a sync instruction, that is, the first address space and the second address space are accessed sequentially when accessing, which affects the running speed of the program.

[0127] For example, if the memory description information of the target address space is generated using the existing memory description information generation method provided in the embodiments of this application, then since the dimensions of the target address space in the second and third dimensions are both constants, namely 64 bytes and 3 bytes respectively, and neither value is one, and the span in the second dimension is constant, the memory description information generation device can determine that the target address space has three dimensions. Accordingly, the memory description information generation device can determine the address space size of the target address space as the product of the size of the target address space in the third dimension and the span of the target address space in the second dimension, which is 2 × 512 = 1024 bytes.

[0128] Furthermore, since the size and span of the target address space in the first dimension are both constant (64 bytes), and the size and span of the target address space in the second dimension are also constant, and the product of the size of the target address space in the second dimension and the span in the first dimension is 8 × 64 bytes, which equals the span of the target address space in the second dimension (512 bytes), the memory description information generation device can determine that the address space type in the memory description information of the target address space is a fully known type. Since a fully known type means that the specific access location is known, the 384 bytes calculated using the above method will be determined as the address space size of the first address space and the second address space, respectively.

[0129] Figure 8 To exemplify the parallel optimization of memory access based on the memory description information generated by the method for generating memory description information according to the embodiments of this application, as shown in the diagram. Figure 8As shown, since the memory description information generated by the method for generating memory description information provided in this application embodiment is accurate, that is, the product of the size of the target address space in the third dimension and the span of the target address space in the second dimension, which is 1024 bytes, is determined as the address space size of the target address space, and the address space type in the memory description information of the target address space is determined to be all known types, the address space size of the first address space and the second address space can be accurately determined to be 384 bytes. Since the offset of the first address space in the first dimension is 8 bytes and the offsets in the second and third dimensions are 0, and the offset of the second address space in the first dimension is 512 bytes and the offsets in the second and third dimensions are 0, the memory access device can determine that there is no overlap between the first address space and the second address space. Therefore, there is no need to insert serial access instructions for the first address space and the second address space, that is, the first address space and the second address space can be accessed in parallel, which effectively improves the running speed of the program.

[0130] Figure 9 This is a schematic diagram of the structure of the memory description information generation device provided in the embodiments of this application, such as... Figure 9 As shown, the memory description information generation device provided in this embodiment includes a judgment module 91 and a generation module 92. The judgment module 91 is used to obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and to determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions. The generation module 92 is used to generate memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions.

[0131] In an optional implementation, the tensor information includes size and span. The judgment module 91 is specifically used to determine the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one.

[0132] In an optional implementation, the memory description information includes the address space size. The generation module 92 is specifically configured to: if the dimension of the target address space is determined to be one dimension, then determine the size of the target address space in that dimension as the address space size; if the dimension of the target address space is determined to be N dimensions, then determine the address space size by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, where N is a positive integer greater than 1; and generate the memory description information of the target address space based on the determined address space size.

[0133] In an optional implementation, the memory description information further includes an address space type. The generation module 92 is further specifically configured to: if the target address space has one dimension, determine that the address space type is a fully known type; if the target address space has N dimensions, determine the address space type based on the span of the (N-1)th dimension multiplied by the size of the Nth dimension and the span size of the Nth dimension; if the span of the (N-1)th dimension multiplied by the size of the Nth dimension is equal to the span size of the Nth dimension, determine that the address space type is a fully known type; otherwise, determine that the address space type is a partially known type.

[0134] In an optional implementation, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first dimension, the second dimension, and the third dimension. The judgment module 91 is specifically configured to determine that the target address space has one dimension if the dimensions of the target address space in the second dimension and the third dimension are both constant and their values ​​are both one, and the dimension in the first dimension is constant; if the dimensions of the target address space in the second dimension are constant and their values ​​are not one, the dimensions in the third dimension are constant and their values ​​are one, and the span in the first dimension is constant; and if the dimensions of the target address space in the second dimension and the third dimension are both constant and their values ​​are not one, and the span in the second dimension is constant, then the target address space has three dimensions.

[0135] In an optional implementation, the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions. The generation module 92 is further specifically configured to, if the number of dimensions of the target address space is determined to be two-dimensional, multiply the size of the target address space in the second dimension by the span of the target address space in the first dimension, and determine the address space size in the memory description information of the target address space; if the number of dimensions of the target address space is determined to be three-dimensional, multiply the size of the target address space in the third dimension by the span of the target address space in the second dimension, and determine the address space size in the memory description information of the target address space.

[0136] In an optional implementation, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first, second, and third dimensions. The generation module 92 is further specifically configured to, if the number of dimensions of the target address space is determined to be one dimension, determine that the address space type in the memory description information of the target address space is a fully known type; and generate the memory description information of the target address space based on the determined address space type.

[0137] In an optional implementation, the generation module 92 is further configured to: if the dimension of the target address space is determined to be two-dimensional, determine whether the size and span of the target address space in the first dimension are both constants and equal in value; if yes, determine that the address space type in the memory description information of the target address space is a fully known type; if no, determine that the address space type in the memory description information of the target address space is a non-fully known type; and generate the memory description information of the target address space based on the determined address space type.

[0138] In an optional implementation, the generation module 92 is further configured to: if the dimension of the target address space is determined to be three-dimensional, determine whether the span of the target address space in the second dimension multiplied by the size of the third dimension is equal to the span in the third dimension; if yes, determine that the address space type in the memory description information of the target address space is a fully known type; if no, determine that the address space type in the memory description information of the target address space is a non-fully known type; and generate the memory description information of the target address space based on the determined address space type.

[0139] It should be noted that the technical solution and effects of the memory description information generation device provided in this embodiment can be found in the relevant content of the foregoing method embodiments, and will not be repeated here.

[0140] Figure 10 This is a schematic diagram of the structure of the memory access device provided in the embodiments of this application, such as... Figure 10 As shown, the memory access device provided in this embodiment includes: an optimization module 101, used to perform parallel optimization of memory access on multiple sub-address spaces created with the target address space as the source address space based on the generated memory description information of the target address space, wherein the memory description information of the target address space is generated using the memory description information generation device as described in the above embodiments of this application.

[0141] In an optional implementation, the optimization module 101 is specifically used to determine, based on the memory description information of the generated target address space, whether there is overlap between multiple sub-address spaces created with the target address space as the source address space; if so, then insert serial access instructions for the multiple sub-address spaces; if not, then do not insert serial access instructions for the multiple sub-address spaces.

[0142] It should be noted that the technical solutions and effects of the memory access device provided in this embodiment can be found in the relevant content of the foregoing method embodiments, and will not be repeated here.

[0143] Figure 11This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application, such as... Figure 11 As shown, this application also provides an electronic device 1100, including: a memory 1101 and a processor 1102.

[0144] Memory 1101 is used to store programs. Specifically, the program may include program code, which includes computer-executable instructions. Memory 1101 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0145] Processor 1102 is used to execute the program stored in memory 1101.

[0146] The computer program is stored in memory 1101 and configured to be executed by processor 1102 to implement the method for generating memory description information or the memory access method provided in any embodiment of this application. Related descriptions can be understood by referring to the relevant descriptions and effects corresponding to the steps in the accompanying drawings, and will not be elaborated upon here.

[0147] In this embodiment, the memory 1101 and the processor 1102 are connected via a bus. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 11 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0148] This application also provides a computer-readable storage medium storing a computer program thereon, which is executed by a processor to implement the method for generating memory description information or the memory access method provided in any embodiment of this application.

[0149] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the method for generating memory description information or the memory access method provided in any embodiment of this application.

[0150] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0151] The modules described as separate components may or may not be physically separate. Similarly, the components shown as modules may or may not be physical modules; they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0152] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in a combination of hardware and software functional modules.

[0153] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other method for generating or accessing programmable memory description information, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0154] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0155] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0156] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0157] The foregoing can be better understood in accordance with the following terms:

[0158] Clause A1. A method for generating memory description information, comprising:

[0159] Obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions;

[0160] For target address spaces with different numbers of dimensions, memory description information of the target address space is generated based on the tensor information of the target address space in different dimensions.

[0161] Clause A2. According to the method described in Clause A1, the tensor information includes size and span; determining the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions includes:

[0162] The number of dimensions of the target address space is determined based on whether the size or span of the target address space in each dimension is constant and whether the size value of the target address space in each dimension is one.

[0163] Clause A3. According to the method described in Clause A1, the memory description information includes the address space size; generating memory description information for a target address space based on tensor information of the target address space in different dimensions for target address spaces of different numbers of dimensions includes:

[0164] If the dimension of the target address space is determined to be one dimension, then the size of the target address space in that dimension is determined as the size of the address space.

[0165] If the dimension of the target address space is determined to be N, then the size of the address space is determined by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, where N is a positive integer greater than 1.

[0166] Based on the determined address space size, memory description information for the target address space is generated.

[0167] Clause A4. According to the method described in Clause A3, the memory description information further includes an address space type; the step of generating memory description information for a target address space based on tensor information of the target address space in different dimensions, for target address spaces of different dimensions, further includes:

[0168] If the dimension of the target address space is one dimension, then the address space type is determined to be a fully known type.

[0169] If the target address space has N dimensions, the address space type is determined by multiplying the span of the (N-1)th dimension by the size of the Nth dimension and the span size of the Nth dimension.

[0170] If the span of the (N-1)th dimension multiplied by the size of the Nth dimension is equal to the span of the Nth dimension, then the address space type is determined to be a fully known type.

[0171] Otherwise, the address space type is determined to be a type that is not fully known.

[0172] Clause A5. According to the method described in Clause A2, the tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions; the step of determining the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one, includes:

[0173] If the dimensions of the target address space in the second dimension and the third dimension are both constant and the value is one, and the dimension in the first dimension is constant, then the number of dimensions of the target address space is determined to be one.

[0174] If the size of the target address space in the second dimension is constant and its value is not one, the size in the third dimension is constant and its value is one, and the span in the first dimension is constant, then the number of dimensions of the target address space is determined to be two-dimensional.

[0175] If the dimensions of the target address space in the second dimension and the third dimension are both constant and their values ​​are not one, and the span in the second dimension is constant, then the target address space is determined to have three dimensions.

[0176] Clause A6. According to the method described in Clause A3, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first, second, and third dimensions. If the number of dimensions of the target address space is determined to be N, then the size of the address space is determined by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, including:

[0177] If the dimension of the target address space is determined to be two-dimensional, then the product of the size of the target address space in the second dimension and the span of the target address space in the first dimension is determined as the address space size in the memory description information of the target address space.

[0178] If the target address space is determined to have three dimensions, then the product of the size of the target address space in the third dimension and the span of the target address space in the second dimension is determined as the address space size in the memory description information of the target address space.

[0179] Clause A7. According to the method described in Clause A4, the tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first dimension, the second dimension, and the third dimension. The step of generating memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions further includes: if it is determined that the number of dimensions of the target address space is one dimension, then the address space type in the memory description information of the target address space is determined to be a fully known type.

[0180] Based on the determined address space type, memory description information for the target address space is generated.

[0181] Clause A8. According to the method described in Clause A7, the step of generating memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different number of dimensions further includes: if it is determined that the number of dimensions of the target address space is two-dimensional, then it is determined whether the size and span of the target address space in the first dimension are both constants and have equal values;

[0182] If so, then the address space type in the memory description information of the target address space is determined to be a fully known type;

[0183] If not, then the address space type in the memory description information of the target address space is determined to be a type that is not fully known.

[0184] Based on the determined address space type, memory description information for the target address space is generated.

[0185] Clause A9. The method described in Clause A7, wherein generating memory description information of the target address space based on tensor information of the target address space in different dimensions for target address spaces of different dimensions, further includes: if it is determined that the number of dimensions of the target address space is three-dimensional, then determining whether the span of the target address space in the second dimension multiplied by the size of the third dimension is equal to the span in the third dimension;

[0186] If so, then the address space type in the memory description information of the target address space is determined to be a fully known type;

[0187] If not, then the address space type in the memory description information of the target address space is determined to be a type that is not fully known.

[0188] Based on the determined address space type, memory description information for the target address space is generated.

[0189] Clause A10. A memory access method, comprising:

[0190] Based on the generated memory description information of the target address space, parallel optimization of memory access is performed on multiple sub-address spaces created with the target address space as the source address space, wherein the memory description information of the target address space is generated using the memory description information generation method described in any one of clauses A1-A9.

[0191] Clause A11. The method according to Clause A10, wherein the parallel optimization of memory access to multiple sub-address spaces created using the target address space as the source address space, based on the generated memory description information of the target address space, includes:

[0192] Based on the memory description information of the generated target address space, it is determined whether there is any overlap between multiple sub-address spaces created using the target address space as the source address space;

[0193] If so, then insert serial access instructions into the plurality of sub-address spaces;

[0194] If not, then serial access instructions will not be inserted for the plurality of sub-address spaces.

[0195] Clause A12. A memory description information generation apparatus, comprising:

[0196] The judgment module is used to obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and to determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions.

[0197] The generation module is used to generate memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions.

[0198] Clause A13. A memory access device, comprising:

[0199] An optimization module is used to perform parallel optimization of memory access for multiple sub-address spaces created with the target address space as the source address space, based on the generated memory description information of the target address space, wherein the memory description information of the target address space is generated using the memory description information generation device as described in Clause A12.

[0200] Clause A14. An electronic device comprising: a processor, and a memory communicatively connected to said processor;

[0201] The memory stores computer-executed instructions;

[0202] The processor executes computer execution instructions stored in the memory to implement the method as described in any one of clauses A1-A11.

[0203] Clause A15. A computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method as described in any one of Clauses A1-A11.

[0204] Clause A16. A computer program product comprising a computer program that, when executed by a processor, implements the method as described in any one of Clauses A1-A11.

[0205] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for generating memory description information, characterized in that, Applied to the compilation process, including: Obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions; For target address spaces with different numbers of dimensions, memory description information of the target address space is generated based on tensor information of the target address space in different dimensions, so as to perform parallel optimization of memory access based on the generated memory description information of the target address space. The memory description information includes the address space size; the generation of memory description information for target address spaces with different numbers of dimensions, based on tensor information of the target address space in different dimensions, includes: If the dimension of the target address space is determined to be one dimension, then the size of the target address space in that dimension is determined as the size of the address space. If the dimension of the target address space is determined to be N, then the size of the address space is determined by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, where N is a positive integer greater than 1. Based on the determined address space size, memory description information for the target address space is generated.

2. The method according to claim 1, characterized in that, The tensor information includes size and span; determining the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions includes: The number of dimensions of the target address space is determined based on whether the size or span of the target address space in each dimension is constant and whether the size value of the target address space in each dimension is one.

3. The method according to claim 1, characterized in that, The memory description information also includes the address space type; the step of generating memory description information for target address spaces of different dimensions based on tensor information of the target address space in different dimensions further includes: If the dimension of the target address space is one dimension, then the address space type is determined to be a fully known type. If the target address space has N dimensions, the address space type is determined by multiplying the span of the (N-1)th dimension by the size of the Nth dimension and the span size of the Nth dimension. If the span of the (N-1)th dimension multiplied by the size of the Nth dimension is equal to the span of the Nth dimension, then the address space type is determined to be a fully known type. Otherwise, the address space type is determined to be a type that is not fully known.

4. The method according to claim 1, characterized in that, The tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first, second, and third dimensions; the determination of the number of dimensions of the target address space based on whether the size or span of the target address space in each dimension is constant, and whether the size value of the target address space in each dimension is one, includes: If the dimensions of the target address space in the second dimension and the third dimension are both constant and the value is one, and the dimension in the first dimension is constant, then the number of dimensions of the target address space is determined to be one. If the size of the target address space in the second dimension is constant and its value is not one, the size in the third dimension is constant and its value is one, and the span in the first dimension is constant, then the number of dimensions of the target address space is determined to be two-dimensional. If the dimensions of the target address space in the second dimension and the third dimension are both constant and their values ​​are not one, and the span in the second dimension is constant, then the target address space is determined to have three dimensions.

5. The method according to claim 1, characterized in that, The tensor information of the target address space in multiple dimensions includes the tensor information of the target address space in the first, second, and third dimensions. If the number of dimensions of the target address space is determined to be N, then the size of the address space is determined by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, including: If the dimension of the target address space is determined to be two-dimensional, then the product of the size of the target address space in the second dimension and the span of the target address space in the first dimension is determined as the address space size in the memory description information of the target address space. If the target address space is determined to have three dimensions, then the product of the size of the target address space in the third dimension and the span of the target address space in the second dimension is determined as the address space size in the memory description information of the target address space.

6. The method according to claim 3, characterized in that, The tensor information of the target address space in multiple dimensions includes tensor information of the target address space in the first, second, and third dimensions. The step of generating memory description information of the target address space based on the tensor information of the target address space in different dimensions, for target address spaces with different numbers of dimensions, further includes: If the dimension of the target address space is determined to be one dimension, then the address space type in the memory description information of the target address space is determined to be a fully known type. Based on the determined address space type, memory description information for the target address space is generated.

7. The method according to claim 6, characterized in that, The method of generating memory description information for target address spaces of different dimensions based on tensor information of the target address space in different dimensions further includes: If the dimension of the target address space is determined to be two-dimensional, then it is determined whether the size and span of the target address space in the first dimension are both constants and have equal values. If so, then the address space type in the memory description information of the target address space is determined to be a fully known type; If not, then the address space type in the memory description information of the target address space is determined to be a type that is not fully known. Based on the determined address space type, memory description information for the target address space is generated.

8. The method according to claim 6, characterized in that, The method of generating memory description information for target address spaces of different dimensions based on tensor information of the target address space in different dimensions further includes: If the target address space is determined to have three dimensions, then it is determined whether the span of the target address space in the second dimension multiplied by the size of the third dimension is equal to the span in the third dimension. If so, then the address space type in the memory description information of the target address space is determined to be a fully known type; If not, then the address space type in the memory description information of the target address space is determined to be a type that is not fully known. Based on the determined address space type, memory description information for the target address space is generated.

9. A memory access method, characterized in that, include: Based on the generated memory description information of the target address space, parallel optimization of memory access is performed on multiple sub-address spaces created with the target address space as the source address space, wherein the memory description information of the target address space is generated using the memory description information generation method as described in any one of claims 1-8.

10. The method according to claim 9, characterized in that, The parallel optimization of memory access for multiple sub-address spaces created using the target address space as the source address space, based on the generated memory description information of the target address space, includes: Based on the memory description information of the generated target address space, it is determined whether there is any overlap between multiple sub-address spaces created using the target address space as the source address space; If so, then insert serial access instructions into the plurality of sub-address spaces; If not, then serial access instructions will not be inserted for the plurality of sub-address spaces.

11. A memory description information generation device, characterized in that, Applied to the compilation process, including: The judgment module is used to obtain tensor information of the target address space pointed to by the target memory node in multiple dimensions, and to determine the number of dimensions of the target address space based on the tensor information of the target address space in multiple dimensions. The generation module is used to generate memory description information of the target address space based on the tensor information of the target address space in different dimensions for target address spaces with different numbers of dimensions, so as to perform parallel optimization of memory access based on the generated memory description information of the target address space. The memory description information includes the address space size; the generation module is specifically used for: If the dimension of the target address space is determined to be one dimension, then the size of the target address space in that dimension is determined as the size of the address space. If the dimension of the target address space is determined to be N, then the size of the address space is determined by multiplying the size of the target address space in the Nth dimension by the span of the target address space in the (N-1)th dimension, where N is a positive integer greater than 1. Based on the determined address space size, memory description information for the target address space is generated.

12. A memory access device, characterized in that, include: An optimization module is used to perform parallel optimization of memory access on multiple sub-address spaces created with the target address space as the source address space, based on the generated memory description information of the target address space, wherein the memory description information of the target address space is generated using the memory description information generation device as described in claim 11.

13. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-10.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-10.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-10.

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