Flow test circuit, method, device, intellectual property core and computer equipment

Abstract

The application relates to a flow test circuit, a method, an apparatus, intellectual property rights, and a computer device. The flow test circuit comprises a test signal analysis module and an access flow control module connected to each other. The test signal analysis module is used for receiving a flow test signal issued by a flow test program for a test object, analyzing a test command in the flow test signal, determining a command identifier carried by the test command, and converting the flow test signal into a target test signal adapted to the test object according to a data flow test mode indicated by the command identifier. The access flow control module is used for sending the target test signal to a test port according to a test signal transmission protocol adopted by the test port, so as to realize that the flow test program applies access flow for testing to each component in the test object. The method can improve the chip test efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a flow test circuit, method, apparatus, intellectual property core, computer equipment, storage medium, and computer program product. Background Technology

[0002] With the increasing performance and complexity of digital circuits, as well as the growing diversity of application scenarios, testing digital circuits is facing more and more challenges. Among them, flow stress testing is a key test point. It can apply flow stress to various components of the chip according to the flow requirements of the actual working scenario, thereby verifying the chip's performance and reliability.

[0003] Traditional techniques often involve verification personnel building models to replace the original main components in the circuit and injecting simple stimulus vectors into various test ports to verify the designed circuit. Because this test stimulus scenario is singular and occurs after chip fabrication, it's impossible to control the access traffic to each component on the chip, resulting in poor performance in stress testing the chip's flow. Summary of the Invention

[0004] Therefore, it is necessary to provide a flow test circuit, method, apparatus, intellectual property core, computer equipment, computer-readable storage medium, and computer program product that can improve chip testing efficiency in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a flow testing circuit, including: a test signal parsing module and an access flow control module connected together.

[0006] The test signal parsing module is used to receive the traffic test signal issued by the traffic test program for the test object, parse the test command in the traffic test signal, determine the command identifier carried by the test command, and convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test method indicated by the command identifier.

[0007] The access traffic control module is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access traffic for testing to each component in the test object.

[0008] In one embodiment, the target test signal includes a target access command and target test data;

[0009] The test signal parsing module is used to determine the target access command in the test command of the flow test signal according to the bus requirements of the test port; and is also used to determine the target test data in the test data of the flow test signal according to the data reading requirements indicated by the command identifier.

[0010] The access flow control module is used to cache the target access command and the target test data according to the caching method indicated by the command identifier, and send the target access command and the target test data as the target test signal to the test port according to the test signal transmission protocol.

[0011] In one embodiment, the access flow control module includes a command buffer and a data buffer;

[0012] The access flow control module is used to store the target access command into the command buffer and the target test data into the data buffer according to the caching method indicated by the command identifier.

[0013] The access flow control module is used to read the command buffer and data buffer according to the test signal transmission protocol, and send the target access command and the target test data as the target test signal to the test port.

[0014] In one embodiment, the traffic testing circuit further includes a monitoring module connected to the access traffic control module:

[0015] The monitoring module is used to receive the target access command and the target test data sent by the access traffic control module, and send the test access traffic to each component in the test object through the read and write channel provided by the test port;

[0016] The monitoring module is also used to monitor the data traffic of the read / write channel and send the monitored traffic information to the access traffic control module so as to control the access traffic applied to the test object using the traffic monitoring information.

[0017] In one embodiment, the flow test circuit further includes an address decoding module, and the test signal parsing module includes: command memory, data memory, and control unit;

[0018] The address decoding module is also used to allow the traffic test program to cache the test data in the traffic test signal in the data memory, and to cache the test command in the traffic test signal in the command memory;

[0019] The control unit is configured to package the test commands in the command memory according to the bus requirements to obtain the target access command; and is also configured to read the target test data from the data memory according to the data reading requirements indicated by the command identifier.

[0020] In one embodiment, the flow test circuit further includes a register, and the address decoding module, the test signal parsing module, and the access flow control module are all connected to the register;

[0021] The address decoding module is used to allow the flow test program to send control signals to the flow test circuit to the register, and the register temporarily stores the control signals.

[0022] The register is used to send a first control instruction from the control signal to the test signal parsing module; the first control instruction is used to instruct the test signal parsing module to perform an operation corresponding to the first control instruction;

[0023] The register is also used to send a second control instruction from the control signal to the access flow control module; the second control instruction is used to instruct the access flow control module to perform an operation corresponding to the second control instruction.

[0024] Secondly, this application also provides a traffic testing method, the method comprising:

[0025] Receive traffic test signals sent by the traffic test program to the test object;

[0026] The test commands in the flow test signal are parsed to determine the command identifier carried by the test commands;

[0027] According to the data traffic testing method indicated by the command identifier, the traffic test signal is converted into a target test signal that is compatible with the test object;

[0028] According to the test signal transmission protocol adopted by the test port of the test object, the target test signal is sent to the test port so that the traffic test program can apply access traffic for testing to each component in the test object.

[0029] In one embodiment, sending the target test signal to the test port includes:

[0030] Monitor the access traffic and determine the current traffic value of the access traffic;

[0031] If the current traffic value is less than or equal to the preset target traffic value, the target test signal is sent to the test port at full speed.

[0032] If the current traffic value is greater than the preset target traffic value, the transmission frequency of the target test signal is adjusted to the pre-configured target transmission frequency.

[0033] In one embodiment, the step of converting the traffic test signal into a target test signal adapted to the test object according to the data traffic test method indicated by the command identifier includes:

[0034] According to the bus requirements of the test port, the test commands in the command memory are packaged to obtain the target access command;

[0035] According to the data reading requirements indicated by the command identifier, the target test data is determined from the test data of the flow test signal;

[0036] The target access command and the target test data are used as the target test signal.

[0037] In one embodiment, sending the target test signal to the test port according to the test signal transmission protocol used by the test port of the test object includes:

[0038] According to the caching method indicated by the command identifier, the target access command is stored in the command buffer, and the target test data is stored in the data buffer.

[0039] According to the test signal transmission protocol, the command buffer and the data buffer are read, and the read target access command and the target test data are sent to the test port.

[0040] Thirdly, this application also provides a flow rate testing device, the device comprising:

[0041] The receiving module is used to receive traffic test signals sent by the traffic test program to the test object;

[0042] The parsing module is used to parse the test commands in the traffic test signal and determine the command identifier carried by the test command;

[0043] The conversion module is used to convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test method indicated by the command identifier;

[0044] The sending module is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access traffic for testing to each component in the test object.

[0045] In one embodiment, the sending module is specifically used to monitor the access traffic and determine the current traffic value of the access traffic; if the current traffic value is less than or equal to a preset target traffic value, send the target test signal to the test port at full speed; if the current traffic value is greater than the preset target traffic value, adjust the sending frequency of the target test signal to a pre-configured target sending frequency.

[0046] In one embodiment, the conversion module is specifically configured to package the test commands in the command memory according to the bus requirements of the test port to obtain the target access command; determine the target test data in the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; and use the target access command and the target test data as the target test signal.

[0047] In one embodiment, the sending module is specifically configured to store the target access command into a command buffer and the target test data into a data buffer according to the caching method indicated by the command identifier; read the command buffer and the data buffer according to the test signal transmission protocol, and send the read target access command and the target test data to the test port.

[0048] Fourthly, this application also provides an intellectual property core, including: the flow test circuit as described above.

[0049] Fifthly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.

[0050] Sixthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0051] In a seventh aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0052] The aforementioned traffic testing circuit, method, apparatus, intellectual property core, computer equipment, storage medium, and computer program product include a test signal parsing module and an access traffic control module connected together. The test signal parsing module receives traffic test signals issued by the traffic testing program for the test object, parses the test commands in the traffic test signals, determines the command identifier carried in the test commands, and converts the traffic test signals into target test signals suitable for the test object according to the data traffic testing method indicated by the command identifier. The access traffic control module then sends the target test signals to the test port according to the test signal transmission protocol used by the test port of the test object. Thus, the traffic testing circuit can adaptively convert the traffic test signals (i.e., software-defined commands) issued by the traffic testing program into a traffic test model that meets the current test task, thereby applying access traffic for testing to each component in the test object and performing personalized control of the access traffic of each component. This effectively facilitates users in constructing rich traffic test scenarios for the test object.

[0053] In addition, since the flow test circuit can be set inside the test object, the access flow of each component on the chip can still be controlled after the test object is fabricated. This allows the test object to be tested to see if it can meet the actual performance requirements before it is put into production, effectively improving the test results of the test object. Attached Figure Description

[0054] Figure 1 This is a diagram illustrating the application environment of a traffic testing method in one embodiment.

[0055] Figure 2 This is a structural block diagram of a flow test circuit in one embodiment;

[0056] Figure 3 This is a structural block diagram of an access flow control module in one embodiment;

[0057] Figure 4 This is a block diagram of another flow test circuit in one embodiment;

[0058] Figure 5 This is a structural block diagram of a test signal parsing module in one embodiment;

[0059] Figure 6 This is a block diagram of a flow test circuit in one embodiment;

[0060] Figure 7 This is a flowchart illustrating a traffic testing method in one embodiment;

[0061] Figure 8This is a control flowchart of a flow testing method in one embodiment;

[0062] Figure 9 This is a structural block diagram of a flow testing device in one embodiment;

[0063] Figure 10 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0065] The flow rate testing circuit provided in this application embodiment can be applied to, for example... Figure 1 In the application environment shown, the flow test circuit 100 can be electrically connected to the electronic device 200 and the test object 300 respectively. In practical applications, the electronic device 200 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. The electronic device 200 runs a flow test program for performing flow test tasks on the test object. The test object 300 can refer to the object that needs to be tested for flow. In practical applications, the test object can refer to an integrated circuit that needs to be subjected to flow stress testing. For example, a chip. The chip can be a system-on-chip (SoC). The test object 300 can include multiple components 310 (slave components). In practical applications, the test object also includes a connection module 320 (e.g., interconnect), through which the flow test circuit 100 can access the various components 320 connected to the connection module 320 via the test master port (TMP) on the connection module 320.

[0066] In one embodiment, such as Figure 2 As shown, a flow test circuit 100 is provided, including: a test signal parsing module 110 and an access flow control module 120 connected together;

[0067] The test signal parsing module 110 is used to receive the traffic test signal issued by the traffic test program for the test object, parse the test command in the traffic test signal, determine the command identifier carried by the test command, and convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test method indicated by the command identifier.

[0068] The command identifier can refer to the command field carried in the test command. This allows for software-defined traffic test signals through the traffic testing program. The field values ​​corresponding to different command fields collectively represent the current data traffic testing method for that test object.

[0069] To facilitate understanding of the command fields by those skilled in the art, the following detailed explanation is provided:

[0070] For each data transmission characteristic, the command field can support the definition of information such as data length, data width, data type, number of loop transmissions, read / write flags, and bus characteristics. The meaning of each command field is shown in Table 1.

[0071] Table 1

[0072]

[0073]

[0074] Table 2 is as follows:

[0075] Table 2

[0076]

[0077] In practice, when a user needs to perform a traffic test on the test object, the user can send a traffic test signal for the test object to the traffic test circuit according to the traffic test program on the electronic device. Specifically, the electronic device responds to the traffic test operation input by the user through the traffic test program for the test object, and generates a software-defined test command for the test object. Then, the electronic device sends the software-defined test command as a traffic test signal to the test signal parsing module in the traffic test circuit.

[0078] The test signal parsing module receives the flow test signal sent by the electronic device. The test signal parsing module can then parse the test command in the flow test signal, determine the command identifier carried by the test command, and convert the flow test signal into a target test signal that is compatible with the test object according to the data flow test method indicated by the command identifier.

[0079] Then, the test signal parsing module sends the target test signal to the access flow control module.

[0080] Specifically, the traffic test signal includes a test command (CMD) and test data (DATA). The test signal parsing module can read and parse the test command (CMD) and, according to the command identifier requirements in the test command, read the test data from the traffic test signal. Simultaneously, the test signal parsing module can package the command according to the TMP interface bus requirements. Finally, the test signal parsing module uses the packaged test command and the read test data as the target test signal adapted to the test object. This allows for the adaptive construction of a test traffic model for traffic testing of the test object within the traffic test circuit, utilizing the traffic test signals issued by the traffic test program.

[0081] The access flow control module 120 is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the flow test program to apply access flow for testing to each component in the test object.

[0082] In practical applications, the access flow control module can be named TMP_CTRL.

[0083] Among them, the test signal transmission protocol can refer to the bus protocol used for the test signal. In practical applications, the test signal transmission protocol can also be named the TMP bus protocol.

[0084] In the specific implementation, the access flow control module can receive and cache the target test signal (i.e., the packaged test command and the read test data) sent by the test signal parsing module. The access flow control module can then read the cached target command and target data according to the TMP bus protocol and send the target command and target data to the test port on the connection module. This enables the application of access flow for testing to each component in the test object, so that the flow test program can perform flow stress testing on the test object.

[0085] The aforementioned traffic testing circuit includes a connected test signal parsing module and an access traffic control module. The test signal parsing module receives traffic test signals issued by the traffic testing program for the test object, parses the test commands in the traffic test signals, determines the command identifier carried by the test commands, and converts the traffic test signals into target test signals suitable for the test object according to the data traffic testing method indicated by the command identifier. The access traffic control module then sends the target test signals to the test ports according to the test signal transmission protocol used by the test ports of the test object. Thus, the traffic testing circuit can adaptively convert the traffic test signals issued by the traffic testing program, i.e., the software-defined commands, into a traffic test model that meets the current test task. This allows for the application of access traffic for testing to each component in the test object and personalized control of the access traffic of each component. This effectively facilitates users in constructing rich traffic test scenarios for the test object.

[0086] In addition, since the flow test circuit can be set inside the test object, the access flow of each component on the chip can still be controlled after the test object is fabricated. This allows the test object to be tested to see if it can meet the actual performance requirements before it is put into production, effectively improving the test results of the test object.

[0087] In another embodiment, the test signal parsing module is used to determine the target access command in the test command of the traffic test signal according to the bus requirements of the test port; and is also used to determine the target test data in the test data of the traffic test signal according to the data reading requirements indicated by the command identifier.

[0088] In its implementation, after receiving the traffic test signal issued by the traffic test program for the test object, the test signal parsing module packages the test commands in the traffic test signal according to the bus requirements of the TMP interface, obtaining the target access command. This target access command is then sent to the access traffic control module. Simultaneously, the test signal parsing module can also determine the target test data from the test data of the traffic test signal according to the data reading requirements indicated by the command identifier. This target test data is then sent to the access traffic control module.

[0089] The access flow control module is used to cache the target access command and target test data according to the caching method indicated by the command identifier, and send the target access command and target test data as target test signals to the test port according to the test signal transmission protocol.

[0090] In its implementation, after receiving the target access command and target test data from the test signal parsing module, the access flow control module can cache the target access command and target test data based on the received command word indication, i.e., according to the caching method indicated by the command identifier. Specifically, the target access command includes at least one of a write command and a read command. Based on the received command word indication, the access flow control module can cache the write command in the target access command to a first buffer specifically for caching write commands, cache the read command in the target access command to a second buffer specifically for caching read commands, and cache the target test data to a third buffer specifically for caching data.

[0091] Then, the access flow control module can read the first buffer, the second buffer, and the third buffer according to the TMP bus protocol, and send the read target access command and target test data as target test signals to the test port TMP.

[0092] The technical solution of this embodiment, through the test signal parsing module, determines the target access command from the test command of the traffic test signal according to the bus requirements of the test port, and determines the target test data from the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; then, through the access traffic control module, the target access command and target test data are cached according to the caching method indicated by the command identifier, and the target access command and target test data are sent to the test port as target test signals according to the test signal transmission protocol. Thus, the above-mentioned traffic test circuit can adaptively convert the traffic test signal issued by the traffic test program, i.e., the software-defined command, into a traffic test model that meets the current test task, thereby using the traffic test circuit to apply access traffic that meets the current test task to each component in the test object.

[0093] In another embodiment, the access flow control module includes a command buffer and a data buffer; the access flow control module is used to store the target access command in the command buffer and the target test data in the data buffer according to the caching method indicated by the command identifier; the access flow control module is used to read the command buffer and the data buffer according to the test signal transmission protocol, and send the target access command and the target test data as a target test signal to the test port.

[0094] For specific implementation details, please refer to [link / reference]. Figure 3 The access flow control module 120 includes a write command buffer 121, a read command buffer 122, and a data buffer 123. In practical applications, the write command buffer can be named WR_CMD_BUFFR, the read command buffer can be named RD_CMD_BUFFR, and the data buffer can be named WR_DATA_BUFFR.

[0095] The target access command includes a write command and a read command. After receiving the read command, write command and target test data sent by the test signal parsing module, the access flow control module caches the write command to the write command buffer, the read command to the read command buffer, and the target test data to the data buffer based on the received command word indication.

[0096] Then, the access flow control module can read the write command buffer, read command buffer, and data buffer according to the TMP bus protocol, and send the read read commands, write commands, and target test data as target test signals to the test port TMP.

[0097] The technical solution of this embodiment enables the above-mentioned traffic test circuit to adaptively convert the traffic test signal, i.e., the software-defined command, issued by the traffic test program into a traffic test model that meets the current test task, thereby applying access traffic that meets the current test task to each component in the test object using the traffic test circuit.

[0098] In another embodiment, the traffic test circuit further includes a monitoring module connected to the access traffic control module: the monitoring module is used to receive the target access command and target test data sent by the access traffic control module, and send the test access traffic to each component in the test object through the read and write channel provided by the test port; the monitoring module is also used to monitor the data traffic of the read and write channel, and send the monitored traffic monitoring information to the access traffic control module, so as to control the access traffic applied to the test object using the traffic monitoring information.

[0099] For specific implementation details, please refer to [link / reference]. Figure 4 The flow test circuit 100 also includes a monitoring module 130 connected to the access flow control module 120; the monitoring module 130 is used to establish a data connection with the test port on the connection module 320. In practical applications, this monitoring module can also be named MONITOR.

[0100] During the process of sending the target access command and target test data to the test port, the access traffic control module can also send the target access command and target test data to the monitoring module. The monitoring module receives the target access command and target test data sent by the access traffic control module and sends the test access traffic to each component in the test object through the read and write channel provided by the test port.

[0101] The monitoring module can also monitor the data traffic of the read and write channels and send the traffic monitoring information to the access traffic control module to dynamically or statically control the access traffic applied to the test object using the traffic monitoring information.

[0102] The dynamic control method is as follows:

[0103] A. If the traffic value received from traffic monitoring is less than or equal to the traffic target value, continue sending data packets to the test object at full speed.

[0104] B. If the traffic value received from traffic monitoring feedback is greater than the target traffic value, the frequency of sending target access commands and target test data will be reduced to the target frequency by controlling the frequency; this target frequency value can be pre-configured.

[0105] The static control method is as follows:

[0106] The traffic testing circuit will report the collected traffic monitoring information to the traffic testing program. Based on the traffic monitoring information, the traffic testing program will configure the access traffic control module to apply the amount of access traffic to the test object.

[0107] The technical solution of this embodiment, by setting a monitoring module connected to the access traffic control module in the traffic test circuit, can monitor the data traffic of the data read and write channel between the traffic test circuit and the test object through the monitoring module, and can effectively dynamically or statically control the access traffic applied to the test object by using the monitored traffic monitoring information.

[0108] In another embodiment, the flow test circuit further includes an address decoding module, and the test signal parsing module includes: a command memory, a data memory, and a control unit; the address decoding module is also used to allow the flow test program to cache the test data in the flow test signal in the data memory, and to cache the test command in the flow test signal in the command memory; the control unit is used to package the test commands in the command memory according to the bus requirements to obtain the target access command; and is also used to read the target test data from the data memory according to the data reading requirements indicated by the command identifier.

[0109] For specific implementation details, please refer to [link / reference]. Figure 4 The flow test circuit 100 also includes an address decoding module 140. In practical applications, the address decoding module BUS_DEC can refer to the interaction channel decoding module between the flow test software and the flow test circuit. The flow test software can access different components within the flow test circuit through address decoding by this module. For example... Figure 5 As shown, the test signal parsing module 110 includes: command memory 111, data memory 112, and control unit 113; wherein, the command memory can also be named CMD_RAM; the data memory can also be named DATA_RAM; and the control unit can also be named RD_CTRL.

[0110] The traffic testing software can cache the test data from the traffic test signals in the data memory and the test commands from the traffic test signals in the command memory via the address decoding module BUS_DEC. Then, the control unit can package the test commands in the command memory according to the bus requirements of the TMP interface, obtaining the target access command. This control unit then sends the target access command to the access traffic control module. Simultaneously, the control unit can also determine the target test data in the data memory according to the data reading requirements indicated by the command identifier. The control unit then sends the target test data to the access traffic control module.

[0111] In another embodiment, the flow test circuit further includes a register, with both the test signal parsing module and the access flow control module connected to the register; an address decoding module for the flow test program to send control signals to the flow test circuit to the register, and for the register to temporarily store the control signals; a register for sending a first control instruction from the control signal to the test signal parsing module; the first control instruction is used to instruct the test signal parsing module to perform an operation corresponding to the first control instruction; the register is also used to send a second control instruction from the control signal to the access flow control module; the second control instruction is used to instruct the access flow control module to perform an operation corresponding to the second control instruction.

[0112] For specific implementation details, please refer to [link / reference]. Figure 4 The flow test circuit 100 also includes a register 150, with an address decoding module 140, a test signal parsing module 110, and an access flow control module 120 all connected to the register 150. The flow test program can send control signals to the register via the address decoding module. Upon receiving the control signal, the register can temporarily store the control instructions within it. In practical applications, the control signal may include a first control instruction for controlling the test signal parsing module and a second control instruction for controlling the access flow control module. The register can send the first control instruction from the control signal to the test signal parsing module, thereby instructing the test signal parsing module to perform the operation corresponding to the first control instruction; the register can also send the second control instruction from the control signal to the access flow control module, thereby instructing the access flow control module to perform the operation corresponding to the second control instruction.

[0113] For example, when a traffic testing program initiates a traffic testing process on a test object, it can configure and control registers to complete the initialization process. Specifically, the traffic testing program can send the initialization process instruction to the register through the address decoding module. Then, the test signal parsing module and the access flow control module can read the initialization process instruction temporarily stored in the register and execute the initialization operation corresponding to that instruction. Alternatively, the traffic testing program can also control the start of the control unit and access flow control module in the test signal parsing module through registers. Specifically, the traffic testing program can send the start instruction to the register through the address decoding module. Then, the test signal parsing module and the access flow control module can read the start instruction temporarily stored in the register, and the control unit and access flow control module in the test signal parsing module respond to the start instruction and execute the start operation.

[0114] The technical solution of this embodiment enables the traffic test circuit to adaptively convert the traffic test signal, i.e., the software-defined command, issued by the traffic test program into a traffic test model that meets the current test task, thereby applying access traffic that meets the current test task to each component in the test object using the traffic test circuit.

[0115] In another embodiment, such as Figure 6 As shown, a principle block diagram of a flow rate testing circuit is provided. The flow rate testing program initiates the flow rate testing process on the test object. The flow rate testing program can configure and control register 150 to complete the initialization process. The test signal parsing module 110 includes a command memory 111, a data memory 112, and a control unit 113. The flow rate testing software can cache the test data in the flow rate test signal in the data memory 112 and the test command in the flow rate test signal in the command memory 111 through the address decoding module 140. Simultaneously, the flow rate testing program can control the start of the control unit 113 in the test signal parsing module and access the flow control module 120 through register 150.

[0116] Then, the control unit 113 reads and parses the test command. Based on the command identifier in the test command and according to the bus requirements of the TMP interface, the control unit 113 packages the test command in the command memory 111, completing the command packaging to obtain the target access command, and sends the target access command to the access flow control module 120. Simultaneously, the control unit 113 can also determine the target test data in the data memory 112 according to the data reading requirements indicated by the command identifier, and send the target test data to the access flow control module 120.

[0117] The access flow control module 120 includes a write command buffer 121, a read command buffer 122, and a data buffer 123. The target access command includes a write command and a read command. After receiving the read command, the write command, and the target test data sent by the test signal parsing module, the access flow control module 120 caches the write command in the write command buffer 121, the read command in the read command buffer 122, and the target test data in the data buffer 123 based on the received command word indication.

[0118] Then, the access flow control module 120 can read the write command buffer 121, the read command buffer 122 and the data buffer 123 according to the TMP bus protocol, and send the read read command, write command and target test data as target test signals to the monitoring module 130. The monitoring module 130 receives the target access command and target test data sent by the access flow control module, and sends the test access flow to each component in the test object through the read and write channel provided by the test port.

[0119] The monitoring module 130 can also monitor the data traffic of the read and write channels and send the traffic monitoring information obtained to the access traffic control module so as to use the traffic monitoring information to dynamically or statically control the access traffic applied to the test object.

[0120] Based on the same inventive concept, this application also provides an intellectual property core, which includes the flow test circuit as described above. The solution provided by this intellectual property core is similar to the solution described in the flow test circuit above. Therefore, the specific limitations of one or more intellectual property core embodiments provided below can be found in the limitations of the flow test circuit above, and will not be repeated here.

[0121] In one embodiment, an intellectual property core (IP core) is provided, comprising: a test signal parsing module and an access flow control module connected together. The test signal parsing module is used to receive traffic test signals issued by a traffic test program for a test object, parse the test commands in the traffic test signals, determine the command identifier carried by the test commands, and convert the traffic test signals into target test signals adapted to the test object according to the data traffic test method indicated by the command identifier. The access flow control module is used to send the target test signals to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access flow for testing to each component in the test object.

[0122] In another embodiment, the test signal parsing module is configured to determine the target access command from the test commands of the traffic test signal according to the bus requirements of the test port; and to determine the target test data from the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; the access traffic control module is configured to cache the target access command and the target test data according to the caching method indicated by the command identifier, and to send the target access command and the target test data as the target test signal to the test port according to the test signal transmission protocol.

[0123] In another embodiment, the access flow control module includes a command buffer and a data buffer; the access flow control module is configured to store the target access command in the command buffer and the target test data in the data buffer according to the caching method indicated by the command identifier; the access flow control module is configured to read the command buffer and the data buffer according to the test signal transmission protocol, and send the target access command and the target test data as the target test signal to the test port.

[0124] In another embodiment, the traffic testing circuit further includes a monitoring module connected to the access traffic control module: the monitoring module is used to receive the target access command and the target test data sent by the access traffic control module, and send the test access traffic to each component in the test object through the read / write channel provided by the test port; the monitoring module is also used to monitor the data traffic of the read / write channel, and send the monitored traffic monitoring information to the access traffic control module, so as to control the access traffic applied to the test object using the traffic monitoring information.

[0125] In another embodiment, the traffic test circuit further includes an address decoding module, and the test signal parsing module includes a command memory, a data memory, and a control unit; the address decoding module is further configured to allow the traffic test program to cache test data in the traffic test signal in the data memory, and to cache test commands in the traffic test signal in the command memory; the control unit is configured to package the test commands in the command memory according to the bus requirements to obtain the target access command; and is further configured to read the target test data from the data memory according to the data reading requirements indicated by the command identifier.

[0126] In another embodiment, the flow test circuit further includes a register, and the address decoding module, the test signal parsing module, and the access flow control module are all connected to the register. The address decoding module is used for the flow test program to send control signals to the flow test circuit to the register, and the register temporarily stores the control signals. The register is used to send a first control instruction from the control signals to the test signal parsing module. The first control instruction is used to instruct the test signal parsing module to perform an operation corresponding to the first control instruction. The register is also used to send a second control instruction from the control signals to the access flow control module. The second control instruction is used to instruct the access flow control module to perform an operation corresponding to the second control instruction.

[0127] In another embodiment, such as Figure 7 As shown, a traffic testing method is provided, which can be applied to... Figure 1 Taking the flow test circuit in the example, the following steps are included:

[0128] Step S710: Receive the traffic test signal sent by the traffic test program for the test object.

[0129] Step S720: Parse the test command in the flow test signal to determine the command identifier carried by the test command.

[0130] Step S730: According to the data traffic test method indicated by the command identifier, the traffic test signal is converted into a target test signal that is compatible with the test object.

[0131] Step S740: According to the test signal transmission protocol adopted by the test port of the test object, the target test signal is sent to the test port so that the traffic test program can apply access traffic for testing to each component in the test object.

[0132] In another embodiment, step S740 includes: monitoring access traffic and determining the current traffic value; if the current traffic value is less than or equal to a preset target traffic value, sending a target test signal to the test port at full speed; if the current traffic value is greater than the preset target traffic value, adjusting the sending frequency of the target test signal to a pre-configured target sending frequency.

[0133] In another embodiment, step S730 above includes: packaging the test commands in the command memory according to the bus requirements of the test port to obtain a target access command; determining the target test data in the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; and using the target access command and the target test data as the target test signal.

[0134] In another embodiment, step S740 above includes: storing the target access command into a command buffer and storing the target test data into a data buffer according to the caching method indicated by the command identifier; reading the command buffer and the data buffer according to the test signal transmission protocol, and sending the read target access command and the target test data to the test port.

[0135] It should be noted that the specific limitations of the above steps can be found in the specific limitations of a flow test circuit described above.

[0136] In another embodiment, such as Figure 8The diagram illustrates a control flow chart for a traffic testing method. The traffic testing program initiates the traffic testing process on the test object. The program can configure and control registers to complete the initialization process. The traffic testing software can cache test data from the traffic test signals in data memory and test commands from the traffic test signals in command memory via an address decoding module. Simultaneously, the traffic testing program can control the start of the control unit and access traffic control module in the test signal parsing module via registers. Then, the control unit reads and parses the test commands. Based on the command identifier in the test command and according to the bus requirements of the TMP interface, the control unit packages the test commands in the command memory, obtaining the target access command, and sends the target access command to the access traffic control module. Simultaneously, the control unit can also determine the target test data in the data memory according to the data reading requirements indicated by the command identifier and send the target test data to the access traffic control module. The target access commands include write commands and read commands. After receiving the read commands, write commands, and target test data from the test signal parsing module, the access flow control module, based on the received command word indication, caches the write commands in the write command buffer, the read commands in the read command buffer, and the target test data in the data buffer. Then, the access flow control module can read the write command buffer, read command buffer, and data buffer according to the TMP bus protocol, and send the read commands, write commands, and target test data as target test signals to the monitoring module. The monitoring module receives the target access commands and target test data sent by the access flow control module and sends the test access traffic to each component in the test object through the read / write channel provided by the test port. The monitoring module can also monitor the data traffic of the read / write channel and send the monitored traffic information to the access flow control module to dynamically or statically control the access traffic applied to the test object using the traffic monitoring information.

[0137] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0138] Based on the same inventive concept, this application also provides a flow testing apparatus for implementing the flow testing method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more flow testing apparatus embodiments provided below can be found in the limitations of the flow testing method described above, and will not be repeated here.

[0139] In one embodiment, such as Figure 9 As shown, a flow rate testing device is provided, comprising:

[0140] The receiving module 910 is used to receive the traffic test signal sent by the traffic test program to the test object;

[0141] The parsing module 920 is used to parse the test commands in the flow test signal and determine the command identifier carried by the test command;

[0142] The conversion module 930 is used to convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test mode indicated by the command identifier.

[0143] The sending module 940 is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access traffic for testing to each component in the test object.

[0144] In one embodiment, the sending module 940 is specifically used to monitor the access traffic and determine the current traffic value of the access traffic; if the current traffic value is less than or equal to a preset target traffic value, send the target test signal to the test port at full speed; if the current traffic value is greater than the preset target traffic value, adjust the sending frequency of the target test signal to a pre-configured target sending frequency.

[0145] In one embodiment, the conversion module 930 is specifically configured to package the test commands in the command memory according to the bus requirements of the test port to obtain the target access command; determine the target test data in the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; and use the target access command and the target test data as the target test signal.

[0146] In one embodiment, the sending module 940 is specifically configured to store the target access command into a command buffer and the target test data into a data buffer according to the caching method indicated by the command identifier; read the command buffer and the data buffer according to the test signal transmission protocol, and send the read target access command and the target test data to the test port.

[0147] Each module in the aforementioned flow testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0148] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a flow rate testing method. The display screen can be an LCD screen or an e-ink display screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0149] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0150] It is understood that the computer device can also be a data processing unit (DPU), network interface card, server, or other similar device. The server can be a single computer device, a server cluster consisting of multiple computer devices, or a distributed server.

[0151] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the steps of the traffic testing method described above. The steps of the traffic testing method described here may be steps from one of the traffic testing methods in the various embodiments described above.

[0152] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, causes the processor to perform the steps of the traffic testing method described above. The steps of the traffic testing method described here may be steps from one of the traffic testing methods in the various embodiments described above.

[0153] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the steps of the traffic testing method described above. The steps of the traffic testing method described here may be steps from one of the traffic testing methods in the various embodiments described above.

[0154] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0155] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0156] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0157] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A flow rate testing circuit, characterized in that, include: The connected test signal parsing module and access flow control module, The test signal parsing module is used to receive the traffic test signal issued by the traffic test program for the test object, parse the test command in the traffic test signal, determine the command identifier carried by the test command, and convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test method indicated by the command identifier. The access traffic control module is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access traffic for testing to each component in the test object.

2. The circuit according to claim 1, characterized in that, The test signal parsing module is used to determine the target access command in the test command of the flow test signal according to the bus requirements of the test port; and is also used to determine the target test data in the test data of the flow test signal according to the data reading requirements indicated by the command identifier. The access flow control module is used to cache the target access command and the target test data according to the caching method indicated by the command identifier, and send the target access command and the target test data as the target test signal to the test port according to the test signal transmission protocol.

3. The circuit according to claim 2, characterized in that, The access flow control module includes a command buffer and a data buffer; The access flow control module is used to store the target access command into the command buffer and the target test data into the data buffer according to the caching method indicated by the command identifier. The access flow control module is used to read the command buffer and data buffer according to the test signal transmission protocol, and send the target access command and the target test data as the target test signal to the test port.

4. The circuit according to claim 2, characterized in that, The flow testing circuit also includes a monitoring module connected to the access flow control module: The monitoring module is used to receive the target access command and the target test data sent by the access traffic control module, and send the test access traffic to each component in the test object through the read and write channel provided by the test port; The monitoring module is also used to monitor the data traffic of the read / write channel and send the monitored traffic information to the access traffic control module so as to control the access traffic applied to the test object using the traffic monitoring information.

5. The circuit according to claim 2, characterized in that, The flow test circuit also includes an address decoding module, and the test signal parsing module includes: command memory, data memory, and control unit; The address decoding module is also used to allow the traffic test program to cache the test data in the traffic test signal in the data memory, and to cache the test command in the traffic test signal in the command memory; The control unit is configured to package the test commands in the command memory according to the bus requirements to obtain the target access command; and is also configured to read the target test data from the data memory according to the data reading requirements indicated by the command identifier.

6. The circuit according to claim 5, characterized in that, The flow test circuit also includes a register, and the address decoding module, the test signal parsing module and the access flow control module are all connected to the register; The address decoding module is used to allow the flow test program to send control signals to the flow test circuit to the register, and the register temporarily stores the control signals. The register is used to send a first control instruction from the control signal to the test signal parsing module; the first control instruction is used to instruct the test signal parsing module to perform an operation corresponding to the first control instruction; The register is also used to send a second control instruction from the control signal to the access flow control module; the second control instruction is used to instruct the access flow control module to perform an operation corresponding to the second control instruction.

7. A flow rate testing method, characterized in that, The method includes: Receive traffic test signals sent by the traffic test program to the test object; The test commands in the flow test signal are parsed to determine the command identifier carried by the test commands; According to the data traffic testing method indicated by the command identifier, the traffic test signal is converted into a target test signal that is compatible with the test object; According to the test signal transmission protocol adopted by the test port of the test object, the target test signal is sent to the test port so that the traffic test program can apply access traffic for testing to each component in the test object.

8. The method according to claim 7, characterized in that, Sending the target test signal to the test port includes: Monitor the access traffic and determine the current traffic value of the access traffic; If the current traffic value is less than or equal to the preset target traffic value, the target test signal is sent to the test port at full speed. If the current traffic value is greater than the preset target traffic value, the transmission frequency of the target test signal is adjusted to the pre-configured target transmission frequency.

9. The method according to claim 7, characterized in that, The data traffic testing method indicated by the command identifier converts the traffic test signal into a target test signal adapted to the test object, including: According to the bus requirements of the test port, the test commands in the traffic test signal are packaged to obtain the target access command; According to the data reading requirements indicated by the command identifier, the target test data is determined from the test data of the flow test signal; The target access command and the target test data are used as the target test signal.

10. The method according to claim 9, characterized in that, Sending the target test signal to the test port according to the test signal transmission protocol used by the test port of the test object includes: According to the caching method indicated by the command identifier, the target access command is stored in the command buffer, and the target test data is stored in the data buffer. According to the test signal transmission protocol, the command buffer and the data buffer are read, and the read target access command and the target test data are sent to the test port.

11. A flow rate testing device, characterized in that, The device includes: The receiving module is used to receive traffic test signals sent by the traffic test program to the test object; The parsing module is used to parse the test commands in the traffic test signal and determine the command identifier carried by the test command; The conversion module is used to convert the traffic test signal into a target test signal that is compatible with the test object according to the data traffic test method indicated by the command identifier; The sending module is used to send the target test signal to the test port according to the test signal transmission protocol adopted by the test port of the test object, so as to enable the traffic test program to apply access traffic for testing to each component in the test object.

12. The apparatus according to claim 11, characterized in that, The sending module is specifically used to monitor the access traffic and determine the current traffic value of the access traffic; if the current traffic value is less than or equal to a preset target traffic value, the target test signal is sent to the test port at full speed; if the current traffic value is greater than the preset target traffic value, the sending frequency of the target test signal is adjusted to a pre-configured target sending frequency.

13. The apparatus according to claim 11, characterized in that, The conversion module is specifically used to package the test commands in the traffic test signal according to the bus requirements of the test port to obtain the target access command; determine the target test data in the test data of the traffic test signal according to the data reading requirements indicated by the command identifier; and use the target access command and the target test data as the target test signal.

14. The apparatus according to claim 13, characterized in that, The sending module is specifically used to store the target access command into a command buffer and the target test data into a data buffer according to the caching method indicated by the command identifier; read the command buffer and the data buffer according to the test signal transmission protocol, and send the read target access command and the target test data to the test port.

15. An intellectual property core, characterized in that, include: The flow test circuit as described in any one of claims 1 to 6.

16. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 7 to 10.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7 to 10.

18. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program performs the steps of the method according to any one of claims 7 to 10.

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