System protection circuit, chip system, reset method, device and storage medium

Abstract

The application provides a system protection circuit, a chip system, a reset method, equipment and a storage medium. The circuit comprises a plurality of target modules, a bus circuit, a reset control circuit and a reset protection circuit. The target modules are host circuits or slave circuits, and the plurality of target modules comprises at least one host circuit and at least one slave circuit. The host circuit is connected with the slave circuit through the bus circuit. The reset control circuit is connected with the bus circuit and the target modules respectively. The reset protection circuit is connected with the bus circuit and the reset control circuit respectively. The reset protection circuit is used for obtaining a reset request, processing a target task corresponding to a specified target module, and outputting a response signal when the bus circuit is idle. The system protection circuit provided by the application makes the system work more smoothly and improves the system performance.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a system protection circuit, chip system, reset method, device and storage medium. Background Technology

[0002] Multi-chip systems typically consist of multiple master circuits and multiple slave circuits connected via a bus. In system design, reset control needs to be added to each master and slave circuit. During circuit system design, each system requires a control unit capable of correctly resetting the entire system, performing a global reset control on all unit circuits and chips within the system upon power-up. For the chips themselves, it is also necessary to ensure that they are reset upon power-up, initializing their internal components to ensure they enter a defined state.

[0003] In circuit system design, a dedicated reset control module is typically included. This module transmits a hard reset signal to the corresponding slave or master circuit to achieve a reset effect. However, there is a delay between the hard reset signal transmitted by the reset control module and the reset command issued by the master circuit. If there are unfinished transactions on the bus when the reset occurs, the entire bus system may freeze after the reset is lifted. Summary of the Invention

[0004] This application provides a system protection circuit, a chip system, a reset method, a device, and a storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this application, a system protection circuit is provided, the circuit comprising: a plurality of target modules, a bus circuit, a reset control circuit, and a reset protection circuit. The target modules are either master circuits or slave circuits, and the plurality of target modules include at least one master circuit and at least one slave circuit. The master circuit is connected to the slave circuit via the bus circuit. The reset control circuit is connected to both the bus circuit and the target modules, and the reset protection circuit is connected to both the bus circuit and the reset control circuit. The reset control circuit is configured to output a reset request corresponding to a reset instruction, the reset instruction originating from the master circuit, and the reset instruction is used to perform a hard reset on a specified target module. The reset protection circuit is configured to acquire the reset request, process the target task corresponding to the specified target module, and output an acknowledgment signal when the bus state corresponding to the specified target module is idle. The reset control circuit is further configured to perform a hard reset on the specified target module upon acquiring the acknowledgment signal.

[0006] In one embodiment, the number of host circuits and / or slave circuits is multiple, and the bus circuit includes a bus control circuit, a first branch, and a second branch. The first branch is connected between the bus control circuit and the host circuit, and the second branch is connected between the bus control circuit and the slave circuit. The bus control circuit is used to establish a transmission relationship between the host circuit and the slave circuit based on preset logic. The preset logic is at least one of control logic based on circuit identification and control logic based on priority.

[0007] In one embodiment, the reset protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first protection sub-circuit is connected to the first branch, and the second protection sub-circuit is connected to the second branch. The target task includes a new transaction and / or a residual transaction. The first protection sub-circuit is used to restrict the first branch from transmitting new transactions and / or residual transactions corresponding to the specified host circuit based on a reset request from the specified host circuit, and to perform signal detection on the first branch. When the bus state corresponding to the specified host circuit is idle, it outputs an acknowledgment signal. The second protection sub-circuit is used to restrict the second branch from transmitting new transactions and / or residual transactions corresponding to the specified slave circuit based on a reset request from the specified slave circuit, and to perform signal detection on the second branch. When the bus state corresponding to the specified slave circuit is idle, it outputs an acknowledgment signal.

[0008] In one embodiment, the number of slave circuits is multiple. The reset control circuit includes a master reset control sub-circuit. The first protection sub-circuit includes a first limiting sub-circuit, a first transmission sub-circuit, and a first detection sub-circuit, all of which are connected to the first branch. The master reset control sub-circuit is used to output a reset request corresponding to a specified master circuit to the first protection sub-circuit. The first limiting sub-circuit is used to limit the transmission of a first command control signal on the first branch. The first command control signal is used to indicate whether a new transaction corresponding to the specified master circuit exists. The first transmission sub-circuit is used to transmit a first data control signal transmitted on the first branch. The first data control signal is used to indicate whether a residual transaction corresponding to the specified master circuit exists. The first detection sub-circuit is used to detect a first bus status signal transmitted on the first branch. The first bus status signal is used to indicate whether the bus status corresponding to the specified master circuit is idle.

[0009] In one embodiment, the first limiting sub-circuit includes: a first configuration unit, configured to configure a first command control signal, wherein when the first command control signal is low, the first branch stops transmitting new transactions corresponding to the designated host circuit; wherein the number of the first command control signals is at least one; the first transmission sub-circuit includes: a second configuration unit, configured to configure a first data control signal, wherein when the first data control signal is high, the first branch transmits residual transactions corresponding to the designated host circuit; wherein the number of the first data control signals is at least one; the first detection sub-circuit includes: a first detection unit, configured to determine that the bus state corresponding to the designated host circuit is idle when the first bus state signal is detected to be high.

[0010] In one embodiment, there are multiple first branches, each connected to the bus control circuit and the designated host circuit respectively, and each first branch is provided with a first protection sub-circuit; multiple slave circuits are configured with different slave IP addresses; the bus control circuit is used to establish a slave transmission relationship between the slave circuit and the corresponding first branch based on the slave IP address.

[0011] In one possible implementation, the system further includes a first fan-out circuit and a first response circuit. The first fan-out circuit is connected to the host reset control sub-circuit and the first branch, respectively. The first response circuit is connected to the host reset control sub-circuit and the first branch, respectively. The first fan-out circuit is used to transmit the reset request to all first protection sub-circuits through fan-out logic. The first response circuit is used to send a valid response signal to the host reset control sub-circuit when it receives response signals from all the first protection sub-circuits.

[0012] In one embodiment, the number of host circuits is multiple. The reset control circuit includes a slave reset control sub-circuit. The second protection sub-circuit includes a second limiting sub-circuit, a second transmission sub-circuit, and a second detection sub-circuit. The second limiting sub-circuit, the second transmission sub-circuit, and the second detection sub-circuit are all connected to the second branch. The slave reset control sub-circuit is used to output a reset request corresponding to a specified slave circuit to the second protection sub-circuit. The second limiting sub-circuit is used to limit the transmission of a second command control signal on the second branch. The second command control signal is used to transmit a new transaction corresponding to the specified slave circuit. The second transmission sub-circuit is used to transmit a second data control signal transmitted on the second branch. The second data control signal is used to transmit residual transactions corresponding to the specified slave circuit. The second detection sub-circuit is used to detect a second bus status signal transmitted on the second branch. The second bus status signal is used to characterize whether the bus status corresponding to the specified slave circuit is idle.

[0013] In one embodiment, the second limiting sub-circuit includes: a third configuration unit, configured to configure a second command control signal, wherein when the second command control signal is low, the second branch stops transmitting new transactions corresponding to the designated slave circuit; wherein the number of the second command control signals is at least one; the second transmission sub-circuit includes: a fourth configuration unit, configured to configure a second data control signal, wherein when the second data control signal is high, the second branch transmits residual transactions corresponding to the designated slave circuit; wherein the number of the second data control signals is at least one; the second detection sub-circuit includes: a second detection unit, configured to determine that the bus state corresponding to the designated master circuit is idle when the second bus state signal is detected to be high.

[0014] In one embodiment, there are multiple second branches, each connected to the bus control circuit and the designated slave circuit respectively, and each second branch is provided with a second protection sub-circuit; multiple master circuits are configured with different master index numbers; the bus control circuit is used to establish a master transmission relationship between the master circuit and the corresponding second branch based on the master index number.

[0015] In one possible implementation, the system further includes a second fan-out circuit and a second acknowledgment circuit. The second fan-out circuit is connected to the slave reset control sub-circuit and the second branch, respectively. The second acknowledgment circuit is connected to the slave reset control sub-circuit and the second branch, respectively. The second fan-out circuit is used to transmit the reset request to all second protection sub-circuits through fan-out logic. The second acknowledgment circuit is used to send a valid acknowledgment signal to the slave reset control sub-circuit when it receives acknowledgment signals from all second protection sub-circuits.

[0016] According to a second aspect of this application, a chip system is provided, including a system protection circuit. The circuit includes: a plurality of target chips, a bus circuit, a reset control circuit, and a reset protection circuit. The target chips are master chips or slave chips, and the plurality of target chips include at least one master chip and at least one slave chip. The master chip is connected to the slave chip through the bus circuit. The reset control circuit is connected to both the bus circuit and the target chips. The reset protection circuit is connected to both the bus circuit and the reset control circuit. The reset control circuit is used to output a reset request corresponding to a reset instruction, the reset instruction originating from the master chip, and the reset instruction is used to perform a hard reset on a specified target chip. The reset protection circuit is used to acquire the reset request, detect the bus circuit, and output an acknowledgment signal when the current task corresponding to the specified target chip is detected as completed. The reset control circuit is also used to perform a hard reset on the specified target chip when the acknowledgment signal is acquired.

[0017] According to a third aspect of this application, a reset method is provided, the method being applied to a system protection circuit, the circuit comprising: a plurality of target modules, a bus circuit, a reset control circuit, and a reset protection circuit, wherein the target modules are master circuits or slave circuits, and the plurality of target modules include at least one master circuit and at least one slave circuit, the master circuit being connected to the slave circuit via the bus circuit, the reset control circuit being connected to both the bus circuit and the target modules, and the reset protection circuit being connected to both the bus circuit and the reset control circuit, the method comprising: the reset control circuit outputting a reset request corresponding to a reset instruction, the reset instruction originating from the master circuit, the reset instruction being used to perform a hard reset on a specified target module; the reset protection circuit acquiring the reset request, processing a target task corresponding to the specified target module, and outputting an acknowledgment signal when the bus state corresponding to the specified target module is idle; and the reset control circuit performing a hard reset on the specified target module upon acquiring the acknowledgment signal.

[0018] According to a fourth aspect of this application, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0019] According to a fifth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0020] This application provides a system protection circuit, chip system, reset method, device, and storage medium. Based on the reset protection circuit, the target task corresponding to the specified target module is processed, enabling the specified target module to perform a hard reset when the bus state corresponding to the specified target module is idle. This solves the system hang problem that may be caused by other target modules not resetting when the specified target module is reset, and improves system stability.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, wherein:

[0023] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0024] Figure 1 A schematic diagram of the implementation module of a system protection circuit according to the first embodiment of this application is shown;

[0025] Figure 2 A schematic diagram of an implementation module for a system protection circuit according to a second embodiment of this application is shown;

[0026] Figure 3 A schematic diagram of an implementation module for a system protection circuit according to a third embodiment of this application is shown;

[0027] Figure 4 A schematic diagram of an implementation module for a system protection circuit according to a fourth embodiment of this application is shown;

[0028] Figure 5 A schematic diagram of the circuit structure of a system protection circuit according to a third embodiment of this application is shown;

[0029] Figure 6 A timing diagram of a system protection circuit according to a third embodiment of this application is shown;

[0030] Figure 7 A schematic diagram of the circuit structure of a system protection circuit according to a fourth embodiment of this application is shown;

[0031] Figure 8 A timing diagram of a system protection circuit according to a fourth embodiment of this application is shown;

[0032] Figure 9 This paper shows a schematic diagram of an implementation module of a chip system according to an embodiment of the present application;

[0033] Figure 10 A schematic diagram illustrating the implementation flow of a reset method according to an embodiment of this application is shown;

[0034] Figure 11 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown.

[0035] The reference numerals in the attached diagram are as follows: 100, Reset control circuit; 110, Master reset control sub-circuit; 120, Slave reset control sub-circuit; 200, Reset protection circuit; 210, First protection sub-circuit; 211, First limiting sub-circuit; 212, First transmission sub-circuit; 213, First detection sub-circuit; 220, Second protection sub-circuit; 221, Second limiting sub-circuit; 222, Second transmission sub-circuit; 223, Second detection sub-circuit; 300, Slave circuit; 400, Bus circuit; 410, First branch; 420, Bus control circuit; 430, Second branch; 500, Master circuit; 610, First fan-out circuit; 620, First acknowledgment circuit; 710, Second fan-out circuit; 720, Second acknowledgment circuit; 800, Slave chip; 900, Master chip. Detailed Implementation

[0036] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] Figure 1 A schematic diagram of the implementation module of a system protection circuit according to the first embodiment of this application is shown; Figure 2 A schematic diagram of an implementation module for a system protection circuit according to a second embodiment of this application is shown; Figure 3 A schematic diagram of an implementation module for a system protection circuit according to a third embodiment of this application is shown; Figure 4 A schematic diagram of an implementation module of a system protection circuit according to the fourth embodiment of this application is shown.

[0038] Combination Figures 1 to 4 According to a first aspect of this application, a system protection circuit is provided, comprising: multiple target modules, a bus circuit 400, a reset control circuit 100, and a reset protection circuit 200. The target modules are either a master circuit 500 or a slave circuit 300, and the multiple target modules include at least one master circuit 500 and at least one slave circuit 300. The master circuit 500 is connected to the slave circuit 300 via the bus circuit 400. The reset control circuit 100 is connected to both the bus circuit 400 and the target modules. The reset protection circuit 200 is connected to both the bus circuit 400 and the reset control circuit. The reset control circuit 100 is used to output a reset request corresponding to a reset command, the reset command originating from the master circuit 500, and the reset command is used to perform a hard reset on the specified target module. The reset protection circuit 200 is used to acquire the reset request, process the target task corresponding to the specified target module, and output an acknowledgment signal when the bus state corresponding to the specified target module is idle. The reset control circuit 100 is also used to perform a hard reset on the specified target module when the acknowledgment signal is acquired.

[0039] This application provides a system protection circuit that includes a reset control circuit 100 and a reset protection circuit 200. The reset protection circuit 200 processes the target task corresponding to a specified target module and outputs an acknowledgment signal to the reset control circuit 100 when the bus state corresponding to the specified target module is idle. This enables the specified target module to perform a hard reset when the corresponding bus state is idle, and the circuit will not retain the task corresponding to the specified target module. This solves the problem of system hang-up that may be caused by other target modules not resetting when the specified target module is reset, improves system stability, makes the system work more smoothly, and improves system performance.

[0040] The system protection circuit provided in this application embodiment can be applied to a system-on-chip (SOC) chip. The target module can be one of the hardware components used to construct the SOC chip, including but not limited to: a core, a memory module, an interrupt module, and a clock module. Based on the target function corresponding to different hardware, the target module can be divided into two types: a master circuit 500 and a slave circuit 300. The master circuit 500 represents hardware with the authority to send reset commands, such as a core. The slave circuit 300 represents hardware without the authority to send reset commands, such as a memory module.

[0041] Based on the specific number of host circuit 500 and slave circuit 300, the system protection circuit provided in this application embodiment is applicable to... Figures 1 to 4 The four scenarios shown are: a scenario with one master circuit 500 and one slave circuit 300, a scenario with one master circuit 500 and multiple slave circuits 300, a scenario with multiple master circuits 500 and one slave circuit 300, and a scenario with multiple master circuits 500 and multiple slave circuits 300.

[0042] See Figure 1 This is a system protection circuit with a master circuit 500 and a slave circuit 300. The master circuit 500 and the slave circuit 300 are connected by a bus circuit 400, which is used for data and signal transmission between the master circuit 500 and the slave circuit 300.

[0043] The input terminals of the reset control circuit 100 are connected to the output terminals of the bus circuit 400 and the reset protection circuit 200, respectively. The output terminals of the reset control circuit 100 are connected to the input terminals of the bus circuit 400, the reset protection circuit 200, the master circuit 500, and the slave circuit 300, respectively. The input terminals of the reset control circuit 100 receive the reset command transmitted by the bus circuit 400, which is issued by the master circuit 500. The reset command can be used to instruct the master circuit 500 to perform a self-reset or to instruct the slave circuit 300 to perform a hard reset.

[0044] When the reset control circuit 100 receives a reset command, it determines the designated target module according to the reset command, that is, determines the designated target module as a designated master circuit or a designated slave circuit, and outputs a reset request corresponding to the designated target module. The reset request is used to instruct the reset protection circuit 200 to process the target task corresponding to the designated target module, and outputs an acknowledgment signal when the bus state corresponding to the designated target module is idle.

[0045] The number of reset protection circuits 200 can be consistent with the number of target modules, ensuring a one-to-one correspondence between reset protection circuits and target modules. When there are multiple reset protection circuits, all of them are set on the bus circuit 400. The input terminal of the reset protection circuit 200 receives a reset request and processes the target task corresponding to the specified target module according to the reset request. The target task is a bus transmission transaction related to the specified target module, including but not limited to new transactions related to the specified target module that need to be transmitted through the bus circuit 400, and residual transactions related to the specified target module that need to be transmitted through the bus circuit 400.

[0046] By processing the target task through the reset protection circuit 200, the bus state corresponding to the specified target module can be made idle as soon as possible. The idle bus state corresponding to the specified target module indicates that no bus transmission transactions related to the specified target module are being performed on the bus circuit 400. When the bus state corresponding to the specified target module is idle, the reset protection circuit 200 outputs an acknowledgment signal through its output terminal.

[0047] The reset control circuit 100 receives an acknowledgment signal at its input. After receiving the acknowledgment signal, the reset control circuit 100 sends a hard reset command to the designated target module through its output, causing the designated target module to perform a hard reset. Through the reset protection circuit 200, the designated target module can be safely and smoothly hard reset without the need for software control. Compared to hard reset operations using software, the reset protection circuit 200 can quickly idle the bus state corresponding to the designated target module, without waiting for an excessively long time, thus reducing resource consumption.

[0048] See Figures 2 to 4 In one embodiment, there are multiple master circuits 500 and / or slave circuits 300. The bus circuit 400 includes a bus control circuit 420, a first branch 410, and a second branch 430. The first branch 410 is connected between the bus control circuit 420 and the master circuit 500, and the second branch 430 is connected between the bus control circuit 420 and the slave circuit 300. The bus control circuit 420 is used to establish a transmission relationship between the master circuit 500 and the slave circuit 300 based on preset logic. The preset logic is at least one of control logic based on circuit identification and control logic based on priority.

[0049] This solution addresses three scenarios: a circuit with one master circuit 500 and multiple slave circuits 300; a circuit with multiple master circuits 500 and one slave circuit 300; and a circuit with multiple master circuits 500 and multiple slave circuits 300. Since there can be multiple master circuits 500 and / or slave circuits 300, the bus circuit 400 includes a bus control circuit 420, a first branch 410, and a second branch 430. Each master circuit 500 is connected to the bus control circuit 420 via the first branch 410, and each slave circuit 300 is connected to the bus control circuit 420 via the second branch 430. The bus control circuit 420 establishes a transmission relationship between any master circuit 500 and any slave circuit 300 according to preset logic. Furthermore, the bus control circuit 420 can also be used to establish a transmission relationship between any two master circuits 500 and between any two slave circuits 300.

[0050] In one implementation scenario, different master circuits 500 can be configured with different master index numbers as circuit identifiers for the master circuits. The master index number of each master circuit is fixed. Different slave circuits 300 can be configured with different slave IP addresses as circuit identifiers for the slave circuits. The bus control circuit 420 can establish a transmission relationship through the master index number and the slave IP address.

[0051] In another implementation scenario, different master circuits 500 and slave circuits 300 can be configured with different priorities. The bus control module can establish transmission relationships between multiple master circuits 500 and / or multiple slave circuits 300 through different priorities to ensure that bus transmission transactions can proceed smoothly.

[0052] In another implementation scenario, different master circuits 500 and slave circuits 300 have corresponding IP addresses and priorities. In regular transmission tasks, the bus control circuit 420 can establish a transmission relationship through the master index number and the slave IP address. When there are multiple transmission transactions for the same master circuit 500 or slave circuit 300, the bus control module can sort the multiple transmission transactions by priority to ensure that the bus transmission transactions can proceed smoothly.

[0053] In one embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220. The first protection sub-circuit 210 is connected to a first branch 410, and the second protection sub-circuit 220 is connected to a second branch 430. The target task includes new transactions and / or residual transactions. The first protection sub-circuit 210 is used to restrict the first branch 410 from transmitting new transactions and / or residual transactions corresponding to the specified host circuit based on a reset request corresponding to the specified host circuit, and to perform signal detection on the first branch 410. When the bus state corresponding to the specified host circuit is idle, it outputs an acknowledgment signal. The second protection sub-circuit 220 is used to restrict the second branch 430 from transmitting new transactions and / or residual transactions corresponding to the specified slave circuit based on a reset request corresponding to the specified slave circuit, and to perform signal detection on the second branch 430. When the bus state corresponding to the specified slave circuit is idle, it outputs an acknowledgment signal.

[0054] The circuit is designed for three scenarios: a circuit with one master circuit 500 and multiple slave circuits 300, a circuit with multiple master circuits 500 and one slave circuit 300, and a circuit with multiple master circuits 500 and multiple slave circuits 300.

[0055] Because the processing and detection methods of the host circuit 500 and the slave circuit 300 differ to a certain extent, in order for the reset protection circuit 200 to accurately process and detect the specified target module, in this embodiment of the application, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220. The first protection sub-circuit 210 is connected to the first branch 410 and to the reset control circuit 100. The first protection sub-circuit 210 obtains the reset request from the reset control circuit 100 for the specified host circuit and processes and detects the target task related to the specified host circuit. The second protection sub-circuit 220 is connected to the second branch 430 and to the reset control circuit 100. The second protection sub-circuit 220 obtains the reset request from the reset control circuit 100 for the specified slave circuit and processes and detects the target task related to the specified slave circuit.

[0056] Specifically, the target tasks include new transactions and / or residual transactions. New transactions refer to various commands generated by the master circuit 500, which are then sent to other slave circuits 300 and the master circuit 500. Residual transactions refer to feedback information corresponding to the commands; this feedback information can be simple feedback signals or data signals based on the commands.

[0057] The first protection sub-circuit 210 is used to limit the transmission of new transactions from the designated master circuit by the first branch 410. The first protection sub-circuit 210 is also used to complete the transmission of any remaining transactions destined for the designated master circuit as quickly as possible. By detecting the bus status of the first branch 410, the first protection sub-circuit 210 can determine whether the bus status corresponding to the first branch 410 is idle. When the bus status corresponding to the first branch 410 is idle, it outputs an acknowledgment signal. When the first branch is transmitting a new transaction from the designated master circuit, if a reset request exists for the first protection sub-circuit 210, the first protection sub-circuit 210 will no longer transmit new transactions to the slave circuit 300, thereby enabling the remaining bus transactions to be processed as quickly as possible and allowing the bus to reach an idle state as soon as possible.

[0058] Similarly, the second protection sub-circuit 220 is used to restrict new transactions transmitted from the second branch 430 to the designated slave circuit. New transactions can originate from any master circuit 500. The second protection sub-circuit 220 is also used to quickly send any remaining transactions output by the designated slave circuit to the corresponding master circuit 500 or other slave circuits 300. The second protection sub-circuit 220 detects the bus status of the second branch 430 to determine whether the bus status corresponding to the designated slave circuit is idle. When the bus status corresponding to the designated slave circuit is idle, it outputs an acknowledgment signal.

[0059] See Figure 3 and Figure 5In one embodiment, there are multiple slave circuits 300. The reset control circuit 100 includes a master reset control sub-circuit 110. The first protection sub-circuit 210 includes a first limiting sub-circuit 211, a first transmission sub-circuit 212, and a first detection sub-circuit 213. The first limiting sub-circuit 211, the first transmission sub-circuit 212, and the first detection sub-circuit 213 are all connected to the first branch 410. The master reset control sub-circuit 110 is used to output a reset request corresponding to a specified master circuit to the first protection sub-circuit 210. The first limiting sub-circuit 211 is used to limit the transmission of the first command control signal of the first branch 410. The first command control signal is used to indicate whether there is a new transaction corresponding to the specified master circuit. The first transmission sub-circuit 212 is used to transmit the first data control signal transmitted by the first branch 410. The first data control signal is used to indicate whether there is a residual transaction corresponding to the specified master circuit. The first detection sub-circuit 213 is used to detect the first bus status signal transmitted by the first branch 410. The first bus status signal is used to indicate whether the bus status corresponding to the first branch 410 is idle.

[0060] The following provides a specific implementation scenario for a circuit that has one master circuit 500 and multiple slave circuits 300.

[0061] In this scenario, there are multiple slave circuits 300, each of which is connected to the bus control circuit 420 via a corresponding second branch 430. The reset control circuit 100 includes a master reset control sub-circuit 110, which is connected to the bus control circuit 420 and is used to perform a master hard reset on a designated master circuit.

[0062] The first protection sub-circuit 210 can be configured on the first branch 410, allowing signals transmitted through the first branch 410 to pass through the first protection sub-circuit 210. Correspondingly, when the first protection sub-circuit 210 does not receive a reset request for the specified host circuit, it maintains a transparent transmission state. When the first protection sub-circuit 210 receives a reset request, it processes and detects the signals and data transmitted through the first limiting sub-circuit 211, the first transmission sub-circuit 212, and the first detection sub-circuit 213, respectively.

[0063] Specifically, the first command control signal is obtained through the first limiting sub-circuit 211. Based on the first command control signal, it can be determined whether the designated host circuit has output a new transaction. When it is determined that the designated host circuit has output a new transaction based on the first command control signal, the first command control signal is configured to restrict the bus circuit 400 from transmitting the new transaction output by the designated host circuit.

[0064] The first data control signal is obtained through the first transmission sub-circuit 212. Based on the first data control signal, it can be determined whether the designated host circuit needs to receive the feedback residual transaction. When it is determined that the designated host circuit needs to receive the feedback residual transaction based on the first data control signal, the bus circuit 400 transmits the residual transaction that needs to be sent to the designated host circuit as soon as possible by configuring the first data control signal.

[0065] The first detection sub-circuit 213 acquires the status signal of the first bus that has passed through it. Based on the first bus status signal, it can determine whether the bus status corresponding to the first branch 410 is idle. When the bus status corresponding to the first branch 410 is idle, it indicates that there are neither new transactions corresponding to the specified host circuit nor residual transactions corresponding to the specified host circuit on the bus circuit 400. At this time, an acknowledgment signal can be fed back to the host reset control sub-circuit 110, causing the host reset control sub-circuit 110 to send a host hard reset command to the specified host circuit to perform a host hard reset process on the specified host circuit.

[0066] In one embodiment, the first limiting sub-circuit 211 includes: a first configuration unit (not shown in the figure), configured to configure a first command control signal, wherein when the first command control signal is low, the first branch 410 stops transmitting new transactions corresponding to the designated host circuit; wherein the number of the first command control signals is at least one; the first transmission sub-circuit 212 includes: a second configuration unit (not shown in the figure), configured to configure a first data control signal, wherein when the first data control signal is high, the first branch 410 transmits residual transactions corresponding to the designated host circuit; wherein the number of the first data control signals is at least one; and the first detection sub-circuit 213 includes: a first detection unit (not shown in the figure), configured to determine that the bus state corresponding to the designated host circuit is idle when a first bus state signal is detected to be high.

[0067] The first configuration unit can be configured to keep the first command control signal low. When the first command control signal is low, the bus circuit 400 stops transmitting the new transaction corresponding to the designated master circuit. The type and number of the first command control signals used by different bus circuits 400 may differ depending on the bus type. In this embodiment, the corresponding first command control signal is determined based on the type of the bus circuit 400. For example, the first command control signal can be a read command flow control signal and a read command valid signal; further, it can be selected as a read command flow control signal transmitted to the designated master circuit and a read command valid signal transmitted to any slave circuit 300.

[0068] Figure 6 A timing diagram of a system protection circuit according to a third embodiment of this application is shown.

[0069] See Figure 6 , Figure 6 This is a timing diagram illustrating the first protection sub-circuit when the bus is an AXI bus. In the AXI bus, the first command control signals are selected as `arready_m` and `arvalid_s`, which set `arready_m` sent to the designated master circuit to 0 and `arvalid_s` sent to any slave circuit 300 to 0, thereby achieving the purpose of the bus circuit 400 not transmitting the newly created transaction corresponding to the designated master circuit.

[0070] The second configuration unit can be configured to keep the first data control signal high. When the first data control signal is high, the bus circuit 400 will transmit the remaining transactions that need to be transmitted to the designated master circuit as quickly as possible. Similarly, depending on the bus type of the bus circuit 400, the type and number of the first data control signals used by different bus circuits 400 may be different. For example, the first data control signal can be a read data flow control signal, further selected as a read data flow control signal transmitted to any slave circuit 300. For example, in the AXI bus, the first data control signal is selected as rready_s, making rready_s = 1 when sent to any slave circuit 300, so that the bus circuit 400 can transmit the remaining transactions to the designated master circuit as quickly as possible.

[0071] Similarly, the first detection unit can perform level detection on the first bus status signal. When the first bus status signal is high, it determines that the bus status corresponding to the first branch 410 is idle. Different bus circuits 400 correspond to different first bus status signals. In the AXI bus, it can be detected by the bus_idle signal. When the bus_idle signal is high, the bus status corresponding to the first branch 410 is idle; when the bus_idle signal is low, the bus status corresponding to the first branch 410 is not idle.

[0072] It should be added that in the AXI bus, the rst_req signal corresponding to the master reset control subcircuit is used to represent a reset request. When a reset request is sent to the first protection subcircuit, the signal is configured as rst_req = 1. The rst_ack signal is used to represent an acknowledgment signal. When the first protection subcircuit returns an acknowledgment signal, the signal is configured as rst_ack = 1. The mst_rst signal is used to represent a hard reset command. After receiving a valid acknowledgment, the master reset control subcircuit sends a hard reset command to the designated master circuit, and the signal is configured as mst_rst = 0. At the same time, the master reset control subcircuit stops sending reset requests, and the signal is configured as rst_req = 0. When the hard reset is released, the signal is configured as mst_rst = 1, and transactions can be transmitted normally between the master circuit and the slave circuit, and the system works normally.

[0073] In one embodiment, there are multiple first branches 410, which are respectively connected to the bus control circuit 420 and the designated master circuit. Each first branch 410 is provided with a first protection sub-circuit 210. Multiple slave circuits 300 are configured with different slave IP addresses. The bus control circuit 420 is used to establish a slave transmission relationship between the slave circuit 300 and the corresponding first branch 410 based on the slave IP address.

[0074] A master circuit 500 can be connected to a bus control circuit 420 via multiple first branches 410, and each first branch 410 is equipped with a first protection submodule. This configuration allows for rapid signal and data transmission through multiple first branches 410 when circuit operations are complex. In this implementation scenario, multiple slave circuits 300 can be configured with different slave IP addresses. The bus control circuit 420 establishes slave transmission relationships between different slave circuits 300 and their corresponding first branches 410 based on their slave IP addresses, thereby achieving reasonable distribution and rapid transmission of signals and data on the first branches 410.

[0075] In one embodiment, the system further includes a first fan-out circuit 610 and a first response circuit 620. The first fan-out circuit 610 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively. The first response circuit 620 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively. The first fan-out circuit 610 is used to transmit a reset request to all first protection sub-circuits 210 through fan-out logic. The first response circuit 620 is used to send a valid response signal to the host reset control sub-circuit 110 when it receives response signals from all first protection sub-circuits 210.

[0076] When there are multiple first branch circuits 410 and multiple first protection submodules, the host reset control subcircuit 110 needs to transmit the reset request to each first protection submodule connected to the specified host circuit through the first fan-out circuit 610. Correspondingly, a first response circuit 620 needs to be set in the circuit to receive the response signal sent by each first protection submodule. Through response AND logic, when all first protection submodules have sent response signals, the response signal is forwarded to the host reset control subcircuit 110, so that the host reset control subcircuit 110 performs a host hard reset on the specified host circuit.

[0077] See Figure 4 and Figure 7In one embodiment, the number of host circuits 500 is multiple. The reset control circuit 100 includes a slave reset control sub-circuit 120. The second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmission sub-circuit 222, and a second detection sub-circuit 223. The second limiting sub-circuit 221, the second transmission sub-circuit 222, and the second detection sub-circuit 223 are all connected to the second branch 430. The slave reset control sub-circuit 120 is used to output a reset request corresponding to a specified slave circuit to the second protection sub-circuit 220. The second limiting sub-circuit 221 is used to limit the transmission of the second command control signal in the second branch 430. The second command control signal is used to transmit a new transaction corresponding to the specified slave circuit. The second transmission sub-circuit 222 is used to transmit the second data control signal in the second branch 430. The second data control signal is used to transmit the residual transaction corresponding to the specified slave circuit. The second detection sub-circuit 223 is used to detect the second bus status signal transmitted in the second branch 430. The second bus status signal is used to characterize whether the bus status corresponding to the second branch 430 is idle.

[0078] The following provides a specific implementation scenario for a circuit that has multiple master circuits 500 and one slave circuit 300.

[0079] In this scenario, there are multiple master circuits 500, each of which is connected to the bus control circuit 420 via a corresponding first branch 410. The reset control circuit 100 includes a slave reset control sub-circuit 120, which is connected to the bus control circuit 420 and is used to perform a slave hard reset on a specified slave circuit.

[0080] The second protection sub-circuit 220 can be configured on the second branch 430, allowing signals transmitted through the second branch 430 to pass through the second protection sub-circuit 220. Correspondingly, when the second protection sub-circuit 220 does not receive a reset request for the specified slave circuit, it maintains a transparent transmission state. When the second protection sub-circuit 220 receives a reset request, it processes and detects the signals and data transmitted through the second branch 430 through the second limiting sub-circuit 221, the second transmission sub-circuit 222, and the second detection sub-circuit 223, respectively.

[0081] Specifically, the second command control signal is obtained through the second limiting sub-circuit 221. Based on the second command control signal, it can be determined whether any master circuit 500 outputs a new transaction to the designated slave circuit. When it is determined based on the second command control signal that any master circuit 500 outputs a new transaction to the designated slave circuit, the second command control signal is configured to restrict the bus circuit 400 from transmitting new transactions that need to be output to the designated slave circuit.

[0082] The second data control signal is obtained through the second transmission sub-circuit 222. Based on the second data control signal, it can be determined whether the designated slave circuit needs to transmit residual transactions to the master circuit 500. When it is determined from the second data control signal that the designated slave circuit needs to transmit residual transactions to the master circuit 500, the bus circuit 400 is configured to transmit the residual transactions output by the designated slave circuit as soon as possible.

[0083] The second detection sub-circuit 223 acquires the status signal of the second bus, and determines whether the bus status corresponding to the second branch 430 is idle based on the second bus status signal. When the bus status corresponding to the second branch 430 is idle, it indicates that there are neither new transactions corresponding to the specified slave circuit nor residual transactions corresponding to the specified slave circuit on the bus circuit 400. At this time, an acknowledgment signal can be fed back to the slave reset control sub-circuit 120, causing the slave reset control sub-circuit 120 to send a hard reset command to the specified slave circuit to perform a slave hard reset process on the specified slave circuit.

[0084] Furthermore, the embodiments of this application may also include a limiting program, which can be implemented by software or hardware circuitry. The limiting program can be set in any module with data processing capabilities, such as the slave reset control sub-circuit 120. When the limiting program is set in the slave reset control sub-circuit 120, the slave reset control sub-circuit 120, while sending a reset request, simultaneously sends a request to limit the generation of new commands to the master circuit 500 to avoid congestion on the bus circuit 400. Correspondingly, after the slave reset control sub-circuit 120 sends a hard reset command to the designated slave circuit, it can send a release command to the master circuit 500, causing the master circuit 500 to restart the generation of new commands.

[0085] In one embodiment, the second limiting sub-circuit 221 includes: a third configuration unit (not shown in the figure) for configuring a second command control signal, wherein when the second command control signal is low, the second branch 430 stops transmitting new transactions corresponding to the specified slave circuit; wherein the number of second command control signals is at least one; the second transmission sub-circuit 222 includes: a fourth configuration unit (not shown in the figure) for configuring a second data control signal, wherein when the second data control signal is high, the second branch 430 transmits residual transactions corresponding to the specified slave circuit; wherein the number of second data control signals is at least one; and the second detection sub-circuit 223 includes: a second detection unit (not shown in the figure) for determining that the bus state corresponding to the specified slave circuit is idle when a second bus state signal is detected to be high.

[0086] The third configuration unit can be configured to keep the second command control signal low. When the second command control signal is low, the bus circuit 400 stops transmitting the new transaction corresponding to the designated slave circuit. The type and number of the second command control signals used by different bus circuits 400 may differ depending on the bus type. In this embodiment, the corresponding second command control signal is determined based on the type of the bus circuit 400. For example, the second command control signal can be a read command flow control signal and a read command valid signal; more specifically, it can be a read command flow control signal transmitted to any master circuit 500 and a read command valid signal transmitted to the designated slave circuit.

[0087] Figure 8 A timing diagram of a system protection circuit according to a fourth embodiment of this application is shown.

[0088] See Figure 8 , Figure 8 This is a timing diagram illustrating the second protection sub-circuit when the bus is an AXI bus. In the AXI bus, the second command control signals are selected as `arready_m` and `arvalid_s`, which set `arready_m` to 0 when sent to any master circuit 500 and `arvalid_s` to 0 when sent to a specified slave circuit, thereby preventing the bus circuit 400 from transmitting the newly created transaction corresponding to the specified slave circuit.

[0089] The fourth configuration unit can be configured to keep the second data control signal high. When the second data control signal is high, the bus circuit 400 will transmit the residual transactions that need to be output by the specified slave circuit as soon as possible. Similarly, depending on the bus type of the bus circuit 400, the type and number of the second data control signals used by different bus circuits 400 may be different. For example, the second data control signal can be a read data flow control signal, further selected as a read data flow control signal transmitted to the specified slave circuit. For example, in the AXI bus, the second data control signal is selected as rready_s, making rready_s = 1 when sent to the specified slave circuit, so that the bus circuit 400 transmits the residual transactions output by the specified master circuit.

[0090] Similarly, the second detection unit can perform level detection on the passing second bus status signal. When the second bus status signal is high, it determines that the bus status corresponding to the second branch 430 is idle. Different bus circuits 400 correspond to different second bus status signals. In the AXI bus, it can be detected by the bus_idle signal. When the bus_idle signal is high, the bus status corresponding to the second branch 430 is idle; when the bus_idle signal is low, the bus status corresponding to the second branch 430 is not idle.

[0091] Similarly, in the AXI bus, the rst_req signal corresponding to the slave reset control subcircuit is used to represent a reset request. When a reset request is sent to the second protection subcircuit, the signal is configured as rst_req = 1. The rst_ack signal is used to represent an acknowledgment signal. When the second protection subcircuit returns an acknowledgment signal, the signal is configured as rst_ack = 1. The mst_rst signal is used to represent a hard reset command. After receiving a valid acknowledgment, the slave reset control subcircuit sends a hard reset command to the designated slave circuit, and the signal is configured as mst_rst = 0. At the same time, the slave reset control subcircuit stops sending reset requests, and the signal is configured as rst_req = 0. When the hard reset is released, the signal is configured as mst_rst = 1, and the master and slave circuits can transmit transactions normally, and the system works normally.

[0092] In one embodiment, there are multiple second branches 430, which are respectively connected to the bus control circuit 420 and the designated slave circuit. Each second branch 430 is provided with a second protection sub-circuit 220. Multiple master circuits 500 are configured with different master index numbers. The bus control circuit 420 is used to establish a master transmission relationship between the master circuit 500 and the corresponding second branch 430 based on the master index number.

[0093] The slave circuit 300 can be connected to the bus control circuit 420 through multiple second branches 430, and each second branch 430 is equipped with a second protection submodule. This configuration allows for rapid signal and data transmission through multiple second branches 430 when circuit operations are complex. In this implementation scenario, multiple master circuits 500 can be configured with different master index numbers. The bus control circuit 420 establishes master transmission relationships between different slave circuits 300 and their corresponding second branches 430 based on the master index numbers, thereby achieving reasonable distribution and rapid transmission of signals and data on the second branches 430.

[0094] In one embodiment, the system further includes a second fan-out circuit 710 and a second response circuit 720. The second fan-out circuit 710 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively. The second response circuit 720 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively. The second fan-out circuit 710 is used to transmit a reset request to all second protection sub-circuits 220 through fan-out logic. The second response circuit 720 is used to send a valid response signal to the slave reset control sub-circuit 120 when it receives response signals from all second protection sub-circuits 220.

[0095] When there are multiple second branch circuits 430 and multiple second protection submodules, the slave reset control subcircuit 120 needs to transmit the reset request to each second protection submodule associated with the specified slave circuit through the second fan-out circuit 710. Correspondingly, a second acknowledgment circuit 720 needs to be set in the circuit to receive the acknowledgment signal sent by each second protection submodule. Through acknowledgment AND logic, when all second protection submodules have sent acknowledgment signals, the acknowledgment signal is forwarded to the slave reset control subcircuit 120, so that the slave reset control subcircuit 120 performs a slave hard reset on the specified slave circuit.

[0096] Figure 9 A schematic diagram of the implementation module of a chip system according to an embodiment of this application is shown.

[0097] Combination Figures 1 to 4 and Figure 9 According to a second aspect of this application, a chip system is provided, including a system protection circuit. The circuit includes: a plurality of target chips, a bus circuit 400, a reset control circuit 100, and a reset protection circuit 200. The target chips are either a master chip 900 or a slave chip 800, and the plurality of target chips include at least one master chip 900 and at least one slave chip 800. The master chip 900 is connected to the slave chip 800 via the bus circuit 400. The reset control circuit 100 is connected to both the bus circuit 400 and the target chips. The reset protection circuit 200 is connected to both the bus circuit 400 and the reset control circuit 100. The reset control circuit 100 is used to output a reset request corresponding to a reset instruction. The reset instruction comes from the master chip 900 and is used to perform a hard reset on the specified target chip. The reset protection circuit 200 is used to acquire the reset request, detect the bus circuit 400, and output an acknowledgment signal when the current task corresponding to the specified target chip is detected to be completed. The reset control circuit 100 is also used to perform a hard reset on the specified target chip when the acknowledgment signal is acquired.

[0098] In one embodiment, there are multiple master chips 900 and / or slave chips 800. The bus circuit 400 includes a bus control circuit 420, a first branch 410, and a second branch 430. The first branch 410 is connected between the bus control circuit 420 and the master chip 900, and the second branch 430 is connected between the bus control circuit 420 and the slave chip 800. The bus control circuit 420 is used to establish a transmission relationship between the master chip 900 and the slave chip 800 based on preset logic. The preset logic is at least one of control logic based on circuit identification and control logic based on priority.

[0099] In one embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220. The first protection sub-circuit 210 is connected to the first branch 410, and the second protection sub-circuit 220 is connected to the second branch 430. The target task includes new transactions and / or residual transactions. The first protection sub-circuit 210 is used to restrict the transmission of new transactions and / or residual transactions corresponding to the specified master chip 900 by the first branch 410 based on the reset request of the specified master chip 900, and to perform signal detection on the first branch 410. When the bus circuit 400 is idle, it outputs an acknowledgment signal. The second protection sub-circuit 220 is used to restrict the transmission of new transactions and / or residual transactions corresponding to the specified slave chip 800 by the second branch 430 based on the reset request of the specified slave chip 800, and to perform signal detection on the second branch 430. When the bus circuit 400 is idle, it outputs an acknowledgment signal.

[0100] In one embodiment, there are multiple chips 800. The reset control circuit 100 includes a host reset control sub-circuit 110, and the first protection sub-circuit 210 includes a first limiting sub-circuit 211, a first transmission sub-circuit 212, and a first detection sub-circuit 213. The first limiting sub-circuit 211, the first transmission sub-circuit 212, and the first detection sub-circuit 213 are all connected to the first branch 410. The host reset control sub-circuit 110 is used to output a reset request corresponding to a specified host chip 900 to the first protection sub-circuit 210. The first limiting sub-circuit 211 is used to limit the transmission of a first command control signal by the first branch 410. The first command control signal is used to transmit a new transaction corresponding to the specified host chip 900. The first transmission sub-circuit 212 is used to transmit a first data control signal transmitted by the first branch 410. The first data control signal is used to transmit residual transactions corresponding to the specified host chip 900. The first detection sub-circuit 213 is used to detect a first bus status signal transmitted by the first branch 410. The first bus status signal is used to characterize whether the bus circuit 400 is idle.

[0101] In one embodiment, the first limiting sub-circuit 211 includes: a first configuration unit, configured to configure a first command control signal, wherein when the first command control signal is low, the first branch 410 stops transmitting new transactions corresponding to the designated main chip 900; wherein the number of the first command control signals is at least one; the first transmission sub-circuit 212 includes: a second configuration unit, configured to configure a first data control signal, wherein when the first data control signal is high, the first branch 410 transmits residual transactions corresponding to the designated main chip 900; wherein the number of the first data control signals is at least one; and a first detection sub-circuit 213 includes: a first detection unit, configured to determine that the bus circuit 400 is idle when a first bus status signal is detected to be high.

[0102] In one embodiment, there are multiple first branches 410, which are respectively connected to the bus control circuit 420 and the designated master chip 900. Each first branch 410 is provided with a first protection sub-circuit 210. Multiple slave chips 800 are configured with different slave IP addresses. The bus control circuit 420 is used to establish a slave transmission relationship between the slave chip 800 and the corresponding first branch 410 based on the slave IP address.

[0103] In one embodiment, the system further includes a first fan-out circuit 610 and a first response circuit 620. The first fan-out circuit 610 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively. The first response circuit 620 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively. The first fan-out circuit 610 is used to transmit a reset request to all first protection sub-circuits 210 through fan-out logic. The first response circuit 620 is used to send a valid response signal to the host reset control sub-circuit 110 when it receives response signals from all first protection sub-circuits 210.

[0104] In one embodiment, there are multiple master chips 900. The reset control circuit 100 includes a slave reset control sub-circuit 120, and the second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmission sub-circuit 222, and a second detection sub-circuit 223. The second limiting sub-circuit 221, the second transmission sub-circuit 222, and the second detection sub-circuit 223 are all connected to the second branch 430. The slave reset control sub-circuit 120 is used to output a reset request corresponding to a specified slave chip 800 to the second protection sub-circuit 220. The second limiting sub-circuit 221 is used to limit the transmission of the second command control signal in the second branch 430. The second command control signal is used to transmit a new transaction corresponding to the specified slave chip 800. The second transmission sub-circuit 222 is used to transmit the second data control signal transmitted in the second branch 430. The second data control signal is used to transmit the residual transaction corresponding to the specified slave chip 800. The second detection sub-circuit 223 is used to detect the second bus status signal transmitted in the second branch 430. The second bus status signal is used to characterize whether the bus circuit 400 is idle.

[0105] In one embodiment, the second limiting sub-circuit 221 includes: a third configuration unit for configuring a second command control signal, wherein when the second command control signal is low, the second branch 430 stops transmitting the newly created transaction corresponding to the specified slave chip 800; wherein the number of the second command control signals is at least one; the second transmission sub-circuit 222 includes: a fourth configuration unit for configuring a second data control signal, wherein when the second data control signal is high, the second branch 430 transmits the residual transaction corresponding to the specified slave chip 800; wherein the number of the second data control signals is at least one; and the second detection sub-circuit 223 includes: a second detection unit for determining that the bus circuit 400 is idle when a second bus status signal is detected to be high.

[0106] In one embodiment, there are multiple second branches 430, which are respectively connected to the bus control circuit 420 and the designated slave chip 800. Each second branch 430 is provided with a second protection sub-circuit 220. Multiple master chips 900 are configured with different host index numbers. The bus control circuit 420 is used to establish a host transmission relationship between the master chip 900 and the corresponding second branch 430 based on the host index number.

[0107] In one embodiment, the system further includes a second fan-out circuit 710 and a second response circuit 720. The second fan-out circuit 710 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively. The second response circuit 720 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively. The second fan-out circuit 710 is used to transmit a reset request to all second protection sub-circuits 220 through fan-out logic. The second response circuit 720 is used to send a valid response signal to the slave reset control sub-circuit 120 when it receives response signals from all second protection sub-circuits 220.

[0108] Figure 10 A schematic diagram illustrating the implementation flow of a reset method according to an embodiment of this application is shown.

[0109] Combination Figures 1 to 4 and Figure 10 According to a third aspect of this application, a reset method is provided. The method is applied to a system protection circuit, the circuit including: multiple target modules, a bus circuit 400, a reset control circuit 100, and a reset protection circuit 200. Each target module is a master circuit 500 or a slave circuit 300, and the multiple target modules include at least one master circuit 500 and at least one slave circuit 300. The master circuit 500 is connected to the slave circuit 300 via the bus circuit 400. The reset control circuit 100 is connected to both the bus circuit 400 and the target modules. The reset protection circuit 200 is connected to both the bus circuit 400 and the target modules. The method, connected to the bus circuit 400 and the reset control circuit 100, includes: operation 801, whereby the reset control circuit 100 outputs a reset request corresponding to a reset command, the reset command originating from the host circuit 500, and the reset command being used to perform a hard reset on a specified target module; operation 802, whereby the reset protection circuit 200 acquires the reset request, processes the target task corresponding to the specified target module, and outputs an acknowledgment signal when the bus state corresponding to the specified target module is idle; and operation 803, whereby the reset control circuit 100 performs a hard reset on the specified target module upon acquiring the acknowledgment signal.

[0110] In one embodiment, there are multiple host circuits 500 and / or slave circuits 300. The bus circuit 400 includes a bus control circuit 420, a first branch 410 and a second branch 430. The first branch 410 is connected between the bus control circuit 420 and the host circuit 500, and the second branch 430 is connected between the bus control circuit 420 and the slave circuit 300.

[0111] The method also includes: the bus control circuit 420 establishing the transmission relationship between the master circuit 500 and the slave circuit 300 based on preset logic; the preset logic is at least one of control logic based on circuit identification and control logic based on priority.

[0112] In one embodiment, the reset protection circuit 200 includes a first protection sub-circuit 210 and a second protection sub-circuit 220. The first protection sub-circuit 210 is connected to the first branch 410, and the second protection sub-circuit 220 is connected to the second branch 430. The target task includes new transactions and / or residual transactions.

[0113] The reset protection circuit 200 processes the target task corresponding to the specified target module. When the bus state corresponding to the specified target module is idle, it outputs an acknowledgment signal, including:

[0114] The first protection sub-circuit 210, based on the reset request of the corresponding designated host circuit, restricts the first branch 410 from transmitting new transactions and / or residual transactions corresponding to the designated host circuit, and performs signal detection on the first branch 410. When the bus state corresponding to the designated host circuit is idle, it outputs an acknowledgment signal.

[0115] The second protection sub-circuit 220, based on the reset request of the corresponding designated slave circuit, restricts the second branch 430 from transmitting new transactions and / or residual transactions corresponding to the designated slave circuit, and performs signal detection on the second branch 430. When the bus state corresponding to the designated slave circuit is idle, it outputs an acknowledgment signal.

[0116] In one embodiment, there are multiple slave circuits 300, the reset control circuit 100 includes a master reset control sub-circuit 110, and the first protection sub-circuit 210 includes a first limiting sub-circuit 211, a first transmission sub-circuit 212 and a first detection sub-circuit 213. The first limiting sub-circuit 211, the first transmission sub-circuit 212 and the first detection sub-circuit 213 are all connected to the first branch 410.

[0117] The reset control circuit 100 outputs a reset request corresponding to the reset command, including: the host reset control sub-circuit 110 outputs a reset request corresponding to the specified host circuit to the first protection sub-circuit 210;

[0118] The first protection sub-circuit 210, based on the reset request of the designated host circuit, restricts the first branch 410 from transmitting new transactions and / or residual transactions corresponding to the designated host circuit, and performs signal detection on the first branch 410. When the bus state corresponding to the designated host circuit is idle, it outputs an acknowledgment signal, including:

[0119] The first limiting sub-circuit 211 limits the transmission of the first command control signal in the first branch 410. The first command control signal is used to indicate whether there is a new transaction corresponding to the specified host circuit.

[0120] The first transmission sub-circuit 212 transmits the first data control signal transmitted by the first branch 410. The first data control signal is used to characterize whether there is a residual transaction corresponding to the specified host circuit.

[0121] The first detection sub-circuit 213 detects the first bus status signal transmitted by the first branch 410. The first bus status signal is used to characterize whether the bus status corresponding to the specified host circuit is idle.

[0122] In one embodiment, there are multiple first branches 410, and the multiple first branches 410 are respectively connected to the bus control circuit 420 and the designated host circuit. Each first branch 410 is provided with a first protection sub-circuit 210.

[0123] The method also includes:

[0124] Multiple slave circuits 300 are configured with different slave IP addresses;

[0125] The bus control circuit 420 establishes a slave transmission relationship between the slave circuit 300 and the corresponding first branch 410 based on the slave IP address.

[0126] In one embodiment, it further includes a first fan-out circuit 610 and a first response circuit 620. The first fan-out circuit 610 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively, and the first response circuit 620 is connected to the host reset control sub-circuit 110 and the first branch 410, respectively.

[0127] The method also includes:

[0128] The first fan-out circuit 610 transmits the reset request to all first protection sub-circuits 210 through fan-out logic;

[0129] When the first response circuit 620 receives the response signals from all the first protection sub-circuits 210, it sends a valid response signal to the host reset control sub-circuit 110.

[0130] In one embodiment, there are multiple host circuits 500, the reset control circuit 100 includes a slave reset control sub-circuit 120, and the second protection sub-circuit 220 includes a second limiting sub-circuit 221, a second transmission sub-circuit 222, and a second detection sub-circuit 223. The second limiting sub-circuit 221, the second transmission sub-circuit 222, and the second detection sub-circuit 223 are all connected to the second branch 430.

[0131] The reset control circuit 100 outputs a reset request corresponding to the reset command, including: the slave reset control sub-circuit 120 outputs a reset request corresponding to the specified slave circuit to the second protection sub-circuit 220;

[0132] The second protection sub-circuit 220, based on the reset request of the designated slave circuit, restricts the second branch 430 from transmitting new transactions and / or residual transactions corresponding to the designated slave circuit, and performs signal detection on the second branch 430. When the bus state corresponding to the designated slave circuit is idle, it outputs an acknowledgment signal, including:

[0133] The second limiting sub-circuit 221 limits the transmission of the second command control signal in the second branch 430. The second command control signal is used to transmit a new transaction corresponding to the specified slave circuit.

[0134] The second transmission sub-circuit 222 transmits the second data control signal transmitted by the second branch 430. The second data control signal is used to transmit residual transactions corresponding to the specified slave circuit.

[0135] The second detection sub-circuit 223 detects the second bus status signal transmitted by the second branch 430. The second bus status signal is used to characterize whether the bus status corresponding to the specified slave circuit is idle.

[0136] In one embodiment, there are multiple second branches 430, and the multiple second branches 430 are respectively connected to the bus control circuit 420 and the designated slave circuit. Each second branch 430 is provided with a second protection sub-circuit 220.

[0137] The method also includes:

[0138] Multiple host circuits 500 are configured with different host index numbers;

[0139] The bus control circuit 420 establishes a host transmission relationship between the host circuit 500 and the corresponding second branch 430 based on the host index number.

[0140] In one embodiment, it further includes a second fan-out circuit 710 and a second response circuit 720. The second fan-out circuit 710 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively. The second response circuit 720 is connected to the slave reset control sub-circuit 120 and the second branch 430, respectively.

[0141] The method also includes:

[0142] The second fan-out circuit 710 transmits the reset request to all second protection sub-circuits 220 through fan-out logic;

[0143] When the second response circuit 720 receives the response signals from all the second protection sub-circuits 220, it sends a valid response signal to the slave reset control sub-circuit 120.

[0144] According to a fourth aspect of this application, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of this application.

[0145] According to a fifth aspect of this application, a non-transitory computer-readable storage medium is provided that stores computer instructions for causing a computer to execute the method of this application.

[0146] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0147] Figure 11 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0148] like Figure 11 As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 902 or a computer program loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.

[0149] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0150] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as the reset method. For example, in some embodiments, the reset method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the reset method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the reset method by any other suitable means (e.g., by means of firmware).

[0151] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0152] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0153] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0154] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0155] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0156] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0157] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0158] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0159] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A system protection circuit, characterized in that, The system protection circuit includes: multiple target modules, a bus circuit, a reset control circuit, and a reset protection circuit. The target modules are either master circuits or slave circuits, and the multiple target modules include at least one master circuit and at least one slave circuit. The master circuit is connected to the slave circuit through the bus circuit. The reset control circuit is connected to both the bus circuit and the target modules. The reset protection circuit is connected to both the bus circuit and the reset control circuit. The reset control circuit is used to output a reset request corresponding to the reset command. The reset command comes from the host circuit and is used to perform a hard reset on the specified target module. The reset protection circuit is used to acquire the reset request, process the target task corresponding to the specified target module, and output an acknowledgment signal when the bus state corresponding to the specified target module is idle. The reset control circuit is further configured to perform a hard reset on the designated target module upon receiving the response signal; wherein, there are multiple host circuits and slave circuits, and the bus circuit includes a bus control circuit, a first branch, and a second branch, wherein the first branch is connected between the bus control circuit and the host circuit, and the second branch is connected between the bus control circuit and the slave circuit; the bus control circuit is configured to establish a transmission relationship between the host circuit and the slave circuit based on preset logic; the preset logic is at least one of control logic based on circuit identification and control logic based on priority; The reset protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first protection sub-circuit is connected to the first branch, and the second protection sub-circuit is connected to the second branch. The target task includes new transactions and residual transactions. The first protection sub-circuit is used to restrict the transmission of new transactions and residual transactions corresponding to the specified host circuit in the first branch based on the reset request of the specified host circuit, and to perform signal detection on the first branch. When the bus state corresponding to the specified host circuit is idle, an acknowledgment signal is output. The second protection sub-circuit is used to restrict the transmission of new transactions and residual transactions corresponding to the specified slave circuit in the second branch based on the reset request of the specified slave circuit, and to perform signal detection on the second branch. When the bus state corresponding to the specified slave circuit is idle, an acknowledgment signal is output.

2. The circuit according to claim 1, characterized in that, The reset control circuit includes a host reset control sub-circuit, and the first protection sub-circuit includes a first limiting sub-circuit, a first transmission sub-circuit, and a first detection sub-circuit, all of which are connected to the first branch. The host reset control sub-circuit is used to output a reset request corresponding to a specified host circuit to the first protection sub-circuit. The first limiting sub-circuit is used to limit the first command control signal transmitted by the first branch, the first command control signal being used to indicate whether there is a new transaction corresponding to the designated host circuit; the first transmission sub-circuit is used to transmit the first data control signal transmitted by the first branch, the first data control signal being used to indicate whether there is a residual transaction corresponding to the designated host circuit. The first detection sub-circuit is used to detect the first bus status signal transmitted by the first branch, and the first bus status signal is used to characterize whether the bus status corresponding to the designated host circuit is idle.

3. The circuit according to claim 2, characterized in that, The first limiting sub-circuit includes: a first configuration unit, configured to configure a first command control signal, wherein when the first command control signal is low, the first branch stops transmitting the new transaction corresponding to the designated host circuit; wherein the number of the first command control signal is at least one. The first transmission sub-circuit includes: a second configuration unit, configured to configure a first data control signal, wherein when the first data control signal is high, the first branch transmits the residual transaction corresponding to the designated host circuit; wherein the number of the first data control signal is at least one. The first detection sub-circuit includes: a first detection unit, used to determine that the bus state corresponding to the designated host circuit is idle when the first bus state signal is detected to be high.

4. The circuit according to claim 2, characterized in that, There are multiple first branches, and each of the multiple first branches is connected to the bus control circuit and the designated host circuit respectively. Each first branch is provided with the first protection sub-circuit. Multiple slave circuits are configured with different slave IP addresses; The bus control circuit is used to establish a slave transmission relationship between the slave circuit and the corresponding first branch based on the slave IP address.

5. The circuit according to claim 4, characterized in that, It also includes a first fan-out circuit and a first response circuit, wherein the first fan-out circuit is connected to the host reset control sub-circuit and the first branch respectively, and the first response circuit is connected to the host reset control sub-circuit and the first branch respectively. The first fan-out circuit is used to transmit the reset request to all first protection sub-circuits through fan-out logic; The first response circuit is used to send a valid response signal to the host reset control sub-circuit when it receives response signals from all the first protection sub-circuits.

6. The circuit according to claim 1, characterized in that, The reset control circuit includes a slave reset control sub-circuit, and the second protection sub-circuit includes a second limiting sub-circuit, a second transmission sub-circuit, and a second detection sub-circuit. The second limiting sub-circuit, the second transmission sub-circuit, and the second detection sub-circuit are all connected to the second branch. The slave reset control sub-circuit is used to output a reset request corresponding to a specified slave circuit to the second protection sub-circuit; The second limiting sub-circuit is used to limit the transmission of the second command control signal in the second branch, the second command control signal being used to transmit the new transaction corresponding to the specified slave circuit; The second transmission sub-circuit is used to transmit the second data control signal transmitted by the second branch, and the second data control signal is used to transmit the residual transaction corresponding to the designated slave circuit; The second detection sub-circuit is used to detect the second bus status signal transmitted by the second branch. The second bus status signal is used to characterize whether the bus status corresponding to the specified slave circuit is idle.

7. The circuit according to claim 6, characterized in that, The second limiting sub-circuit includes: a third configuration unit, configured to configure a second command control signal, wherein when the second command control signal is low, the second branch stops transmitting the new transaction corresponding to the designated slave circuit; wherein the number of the second command control signal is at least one. The second transmission sub-circuit includes: a fourth configuration unit, configured to configure a second data control signal, wherein when the second data control signal is high, the second branch transmits the residual transaction corresponding to the designated slave circuit; wherein the number of the second data control signal is at least one. The second detection sub-circuit includes: a second detection unit, used to determine that the bus state corresponding to the designated host circuit is idle when the second bus state signal is detected to be high.

8. The circuit according to claim 7, characterized in that, There are multiple second branches, and each of the multiple second branches is connected to the bus control circuit and the designated slave circuit respectively. Each second branch is provided with a second protection sub-circuit. Multiple host circuits are configured with different host index numbers; The bus control circuit is used to establish a host transmission relationship between the host circuit and the corresponding second branch based on the host index number.

9. The circuit according to claim 8, characterized in that, It also includes a second fan-out circuit and a second response circuit. The second fan-out circuit is connected to the slave reset control sub-circuit and the second branch respectively, and the second response circuit is connected to the slave reset control sub-circuit and the second branch respectively; The second fan-out circuit is used to transmit the reset request to all second protection sub-circuits via fan-out logic; The second response circuit is used to send a valid response signal to the slave reset control sub-circuit when it receives response signals from all the second protection sub-circuits.

10. A chip system, characterized in that, The system includes a system protection circuit, which comprises: multiple target chips, a bus circuit, a reset control circuit, and a reset protection circuit. The target chips are either master chips or slave chips, and the multiple target chips include at least one master chip and at least one slave chip. The master chip is connected to the slave chip through the bus circuit. The reset control circuit is connected to both the bus circuit and the target chip. The reset protection circuit is connected to both the bus circuit and the reset control circuit. The reset control circuit is used to output a reset request corresponding to a reset command. The reset command comes from the main chip and is used to perform a hard reset on a specified target chip. The reset protection circuit is used to acquire the reset request, process the target task corresponding to the specified target chip, and output an acknowledgment signal when the bus state corresponding to the specified target chip is idle. The reset control circuit is further configured to perform a hard reset on the designated target chip upon receiving the response signal; wherein there are multiple master chips and slave chips, and the bus circuit includes a bus control circuit, a first branch, and a second branch, wherein the first branch is connected between the bus control circuit and the master chip, and the second branch is connected between the bus control circuit and the slave chip; the bus control circuit is configured to establish a transmission relationship between the master chip and the slave chip based on preset logic; the preset logic is at least one of control logic based on circuit identification and control logic based on priority; The reset protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first protection sub-circuit is connected to the first branch, and the second protection sub-circuit is connected to the second branch. The target task includes new transactions and residual transactions. The first protection sub-circuit is used to restrict the transmission of new transactions and residual transactions corresponding to the specified main chip in the first branch based on the reset request of the specified main chip, and to perform signal detection on the first branch. When the bus state corresponding to the specified main chip is idle, an acknowledgment signal is output. The second protection sub-circuit is used to restrict the transmission of new transactions and residual transactions corresponding to the specified slave chip in the second branch based on the reset request of the specified slave chip, and to perform signal detection on the second branch. When the bus state corresponding to the specified slave chip is idle, an acknowledgment signal is output.

11. A reset method, characterized in that, The reset method is applied to a system protection circuit, which includes: multiple target modules, a bus circuit, a reset control circuit, and a reset protection circuit. Each target module is a master circuit or a slave circuit, and the multiple target modules include at least one master circuit and at least one slave circuit. The master circuit is connected to the slave circuit via the bus circuit. The reset control circuit is connected to both the bus circuit and the target modules. The reset protection circuit is connected to both the bus circuit and the reset control circuit. The method includes: The reset control circuit outputs a reset request corresponding to the reset command. The reset command comes from the host circuit and is used to perform a hard reset on the specified target module. The reset protection circuit acquires the reset request, processes the target task corresponding to the specified target module, and outputs an acknowledgment signal when the bus state corresponding to the specified target module is idle. When the reset control circuit receives the response signal, it performs a hard reset on the designated target module. The system includes multiple host circuits and slave circuits. Each bus circuit comprises a bus control circuit, a first branch, and a second branch. The first branch connects the bus control circuit and the host circuit, and the second branch connects the bus control circuit and the slave circuit. The bus control circuit establishes the transmission relationship between the host circuit and the slave circuit based on preset logic. The preset logic is at least one of control logic based on circuit identification and control logic based on priority. The reset protection circuit includes a first protection sub-circuit and a second protection sub-circuit. The first protection sub-circuit is connected to the first branch, and the second protection sub-circuit is connected to the second branch. The target task includes new transactions and residual transactions. The first protection sub-circuit, based on the reset request of the corresponding designated host circuit, restricts the first branch from transmitting new transactions and residual transactions corresponding to the designated host circuit, and performs signal detection on the first branch. When the bus state corresponding to the designated host circuit is idle, it outputs an acknowledgment signal. The second protection sub-circuit, based on the reset request of the corresponding designated slave circuit, restricts the transmission of new transactions and residual transactions corresponding to the designated slave circuit in the second branch, and performs signal detection on the second branch. When the bus state corresponding to the designated slave circuit is idle, it outputs an acknowledgment signal.

12. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the reset method of claim 11.

13. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to claim 11.

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