A device aging sensitive point analysis method

Abstract

The application discloses a device aging sensitive point analysis method. The application carries out aging analysis on devices in each module level in the circuit according to the module levels of the circuit design. When aging simulation is carried out on the devices in a random module level in the circuit, the devices in the remaining module levels are reset to zero, so that the aging analysis on the devices in the current module level is facilitated. After the circuit network simulation is completed, the aging performance degradation index of each module level of the circuit network is compared with the aging performance degradation index threshold. If the aging performance degradation index of the current module level of the circuit network is greater than the aging performance degradation index threshold, aging simulation is carried out on M circuit network tables of the next level in the circuit network of the current module level until the devices of the lowest level. The application can greatly reduce the calculation amount of the circuit reliability sensitive point analysis, improve the efficiency and speed of the circuit reliability sensitive point analysis, and will not affect the accuracy of the sensitive point analysis.

Description

Technical Field

[0001] This invention belongs to the field of device aging technology, and specifically relates to a method for analyzing device aging sensitivity points. Background Technology

[0002] Device aging simulation and post-aging simulation processes can obtain the performance parameters of the circuit after aging. Once designers obtain these aging performance parameters, they need to modify the circuit to extend its lifespan. Typically, a circuit contains multiple devices, each with varying degrees of aging. Accurately locating the device requiring modification is a significant challenge for younger designers. While device aging simulation can provide the electrical performance of each device after aging, concluding that the most severely aged device has the greatest impact on the circuit is unreliable.

[0003] Reliability aging simulation already supports various techniques. Current aging simulation pipelines provide the performance of the aged circuit and the drift of all MOSFET parameters (Vth, mobility, and others), and then use these degradations for post-aging simulation. However, current pipelines do not provide information about which devices are causing changes in circuit performance. While they can provide information on the failure of each device and the performance of the aged circuit, they do not offer a method to identify which devices contribute to changes in overall circuit performance. Especially for complex circuits, there is a need to implement aging sensitivity analysis and incorporate it into the current aging pipeline to show which devices are causing changes in circuit performance.

[0004] Aging simulation provides the results of circuit aging. By comparing these results with new simulations, designers can understand the performance of the aged circuit and whether they need to update the design to correct performance changes caused by reliability issues. When a circuit fails during testing or simulation, designers need to identify which components in the design are causing the failure. Typically, this search process is based on experience and complex testing, increasing design cycles and testing costs. In providing aging simulation support to designers, it has been found that while a large number of degraded MOSFETs exist, only a small fraction significantly affect the overall circuit performance or cause failures. Furthermore, these critical components may not necessarily have the greatest degradation. Especially for complex circuits, it is difficult to determine which components are causing changes in circuit performance. Therefore, a solution is needed to identify relevant sensitive components and their contribution to changes in circuit performance. Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of existing technologies by providing a method for analyzing device aging sensitivity points.

[0006] Because circuits typically contain a large number of components and their functions are increasingly complex, circuit reliability sensitivity analysis involves computations on a massive scale. Therefore, circuit reliability sensitivity analysis technology is not only related to server computing power but also requires improved analysis algorithms. To understand the impact of components on the circuit, sensitivity analysis is needed within the reliability simulation process to obtain the impact factor of each aged component on the overall circuit performance. The specific process is as follows: Aging parameters for only one or a few components are enabled, and post-aging simulation is performed to output the key electrical indicators of the circuit; the key electrical indicators of the circuit after aging are compared with those before aging to obtain the impact factor of the aging of these components on the overall circuit performance.

[0007] This invention proposes to use hierarchical and parallel computing methods to analyze circuit reliability-sensitive points. Specifically, the following algorithm can be used to analyze circuit reliability-sensitive points:

[0008] (1) Existing circuit designs are often carried out using a hierarchical and modular approach. According to the N module levels provided by the circuit design, the devices in each module level are subjected to aging analysis in turn. That is, when aging simulation is performed on a device in a random module level of the circuit, the devices in the other N-1 module levels are reset to zero, which facilitates the aging analysis of the devices in the current module level.

[0009] Furthermore, the aging simulation of the N module levels is processed in parallel, that is, the aging simulation is performed on each module level in parallel to obtain the aging performance degradation index of each module level.

[0010] (2) After the simulation of all module-level circuit networks is completed, compare the aging performance degradation index of each module-level circuit network with the aging performance degradation index threshold. If the aging performance degradation index of the current module-level circuit network is greater than the aging performance degradation index threshold, then perform aging simulation on the M circuit nets of the next level in the current module-level circuit network, until the lowest level device. This can greatly reduce the computational load of circuit reliability sensitivity analysis, improve the efficiency and speed of circuit reliability sensitivity analysis, and will not affect the accuracy of circuit reliability sensitivity analysis.

[0011] Furthermore, the aging simulation of the M circuit nets in the next level of the current module level is the same as the aging simulation of the module level in step (1). That is, when aging simulation is performed on a random next level circuit net of the current module level, the devices in the remaining M-1 next level circuit nets are reset to zero, and the aging simulation of the M next level circuit nets is processed in parallel.

[0012] like Figure 1 As shown, the specific process steps of this patent are as follows:

[0013] Step 1: Perform a simulation of the module circuit network before aging and save the simulation results (I).

[0014] Step 2: Perform an aging simulation on the module circuit network and save the simulation result II; the simulation result contains the degradation value of each MOSFET. The MOSFET degradation value includes changes in threshold voltage vth, mobility, and other parameters.

[0015] Step 3: Based on simulation result II, perform aging simulation on the module circuit network and save simulation result III.

[0016] Step 4: Compare simulation result I and simulation result III, and use the difference between the two simulation results as the standard value.

[0017] Step 5: Following the N module levels provided in the circuit design, perform aging analysis on the components in each module level sequentially. Specifically, when aging simulation is performed on a component in a randomly selected module level, the components in the remaining N-1 module levels are reset to zero to facilitate aging analysis of the components in the current module level. More specifically: in each simulation, run a subset of aged MOSFETs, while keeping the other MOSFETs at their pre-aging (time0) parameters (i.e., the simulation parameters obtained in Step 1).

[0018] Furthermore, the aging simulation of the N module levels is processed in parallel, that is, the aging simulation is performed on each module level in parallel to obtain the aging performance degradation index of each module level.

[0019] Furthermore, the aging simulation environment is the same for each module level, that is, the netlist and test bench used are the same.

[0020] Step 6: After the simulation of all module-level circuit networks is completed, compare the aging performance degradation index of each module-level circuit network with the aging performance degradation index threshold. If the aging performance degradation index of the current module-level circuit network is greater than the aging performance degradation index threshold, then perform aging simulation on the M circuit nets of the next level in the current module-level circuit network, until the lowest level device.

[0021] Furthermore, the aging performance degradation index threshold R0 is obtained by calculating the standard value Q, as follows:

[0022] R0=λ0Q

[0023] Wherein, λ0 is the set aging impact factor.

[0024] Furthermore, if the result relative to the comparison is less than R0, it means that enabling the damaged module level, the next level of circuit network, or the lowest level device (MOSFET) does not contribute to the change in circuit performance. If there is a difference and the result is greater than R0, then a loop is run to resubmit several parallel aging simulations.

[0025] Furthermore, the several parallel aging simulations that are resubmitted are at the same level, that is, the same level of module hierarchy, or the next level of circuit network, or the lowest level of device.

[0026] Step 7: After the above steps, obtain the percentage difference R = λQ for each lowest level device (MOSFET), thereby identifying the devices that are sensitive to reliability impact.

[0027] The beneficial effects of this invention are as follows:

[0028] This invention provides an aging sensitivity analysis method that automatically runs multiple simulations to identify which components contribute to changes in overall circuit performance caused by reliability effects. By using this function, designers can clearly understand which devices require attention, and when a design fails, they will know which devices caused the failure. Other existing technologies lack this functionality; their aging simulation techniques are limited to providing only aging circuit performance data.

[0029] This invention aims to provide a useful analytical method to help designers identify which components contribute to variations in overall circuit performance. They will then know which components to pay attention to during the design process. When a design fails, they know which components to fix. By using this method, it is unnecessary to add margins to all components. This method reduces the required burn-in margin / over-design, which translates into various benefits such as reduced block size / power consumption.

[0030] The advantages of this invention are:

[0031] 1. Help designers identify changes in circuit performance caused by sensitive components affecting reliability.

[0032] 2. When a circuit fault is discovered, testing costs are reduced and weak points are identified. Edge space is also saved during the repair process.

[0033] 3. It fully supports current aging simulation processes. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the device aging simulation technology and sensitivity analysis technology of the present invention.

[0035] Figure 2 This is a flowchart of the device aging sensitivity analysis method of the present invention.

[0036] Figure 3 The VCO circuit diagrams for NBTI and HCI are considered for the present invention.

[0037] Figure 4 This is a schematic diagram of the vth drift value of the VCO circuit of the present invention. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0039] like Figure 1 and 2 As shown, a method for analyzing device aging-sensitive points includes the following specific contents:

[0040] Component 1: Simulate the module circuit network before aging and save the simulation results (I). The simulation results include plotted waveforms, measurement results, or original files.

[0041] Component2: Perform an aging simulation on the module's circuit network and save the simulation result II. Simultaneously, based on the simulation result II, perform a post-aging simulation on the module's circuit network and save the simulation result III.

[0042] Component3: Compares the simulation results from component1 and component2, that is, compares simulation result I and simulation result III, and uses the difference between the two simulation results as the standard value.

[0043] Example 1:

[0044] The net voltages at 1 second in the pre-aging and post-aging simulations were 1.0V and 1.2V, respectively, with a standard value of 0.2V saved.

[0045] Example 2:

[0046] A ring oscillator was simulated at frequencies of 1.0 GHz and 0.9 GHz before and after aging, respectively. The standard value of 0.1 GHz was saved.

[0047] Component 4: Following the N module levels provided by the circuit design, perform aging analysis on the components in each module level sequentially. Specifically, when aging simulation is performed on a component in a randomly selected module level, the components in the remaining N-1 module levels are reset to zero to facilitate aging analysis of the components in the current module level. More precisely: submit a post-aging simulation where some components are still usable after degradation, while others are unusable.

[0048] Component 5: Similar to Component 4, compare the results of Component 4 and Component 1. Obtain the aging performance degradation index for each module level, and then use the aging performance degradation index of Component 3 to calculate the percentage.

[0049] Component 6: Submit multiple Component 4 and Component 5 sets simultaneously. Each set includes a post-aging simulation and a result comparison. In each post-aging simulation (Component 4), the name of the device available for degradation differs from other submissions. The device availability degradation is set based on a specific degradation distribution algorithm. The comparison percentage is saved after each submission.

[0050] Component 7: Analyzes the results of Component 6. If the result is less than R0 relative to the comparison result, it means that enabling the damaged module level, the next level of circuit network, or the lowest level device (MOSFET) does not contribute to the change in circuit performance. If there is a difference and the result is greater than R0, and the current loop is the lowest level device; if only one device degradation is enabled in the aging simulation, the contribution of that device to reliability is directly output. If there are multiple devices supporting degradation in the aging simulation, then Component 6 is rerun, during which time these devices will be assigned to different simulations.

[0051] Component8: When the loop of component7 is complete, obtain all components and their comparison percentages.

[0052] Figure 3 This is the simulation circuit diagram for the VCO. Figure 4 Based on the simulation results of the VTH drift, after sensitivity analysis, only four devices affect the frequency shift, so there is no need to add edge margin or optimize other devices.

Claims

1. A device aging sensitive point analysis system, characterized in that... This system employs hierarchical and parallel computing methods to analyze circuit reliability-sensitive points, as detailed below: (1) According to the N module levels provided by the circuit design, perform aging analysis on the devices in each module level of the circuit in sequence. That is, when performing aging simulation on the devices in a random module level of the circuit, the devices in the other N-1 module levels are reset to zero, which facilitates the aging analysis of the devices in the current module level. (2) After the simulation of the circuit network at all module levels is completed, compare the aging performance degradation index of the circuit network at each module level with the aging performance degradation index threshold. If the aging performance degradation index of the current module level circuit network is greater than the aging performance degradation index threshold, then perform aging simulation on the M circuit network tables of the next level in the current module level circuit network until the lowest level device. This greatly reduces the computational load of circuit reliability sensitivity analysis, improves the efficiency and speed of circuit reliability sensitivity analysis, and does not affect the accuracy of circuit reliability sensitivity analysis.

2. The device aging sensitive point analysis system according to claim 1, characterized in that... The aging simulation of the N module levels is processed in parallel, that is, the aging simulation is performed on each module level in parallel to obtain the aging performance degradation index of each module level.

3. A device aging sensitive point analysis system according to claim 1 or 2, characterized in that... The aging simulation of the M circuit nets in the next level of the current module level is the same as the aging simulation of the module level in step (1). That is, when aging simulation is performed on a random next level circuit net of the current module level, the devices in the other M-1 next level circuit nets are reset to zero, and the aging simulation of the M next level circuit nets is processed in parallel.

4. A method for analyzing device aging-sensitive points, characterized in that... The specific steps are as follows: Step 1: Perform a simulation of the module circuit network before aging and save the simulation results (I). Step 2: Perform an aging simulation on the circuit network of this module and save the simulation result II; the simulation result contains the degradation value of each MOSFET; the MOSFET degradation value includes changes in threshold voltage vth, mobility and other parameters; Step 3: Based on simulation result II, perform aging simulation on the module circuit network and save simulation result III; Step 4: Compare simulation result I and simulation result III, and use the difference between the two simulation results as the standard value; Step 5: According to the N module levels provided by the circuit design, perform aging analysis on the devices in each module level of the circuit in sequence; that is, when aging simulation is performed on a device in a random module level of the circuit, the devices in the other N-1 module levels are reset to zero, which facilitates the aging analysis of the devices in the current module level; specifically: in each simulation, run a subset of aged MOSFETs, while the other MOSFETs remain at their pre-aging parameters. Step 6: After the simulation of the circuit network at all module levels is completed, compare the aging performance degradation index of each module level circuit network with the aging performance degradation index threshold. If the aging performance degradation index of the current module level circuit network is greater than the aging performance degradation index threshold, then perform aging simulation on the M circuit network tables of the next level in the current module level circuit network until the lowest level device. Step 7: After the above steps, the percentage of aging performance degradation indicators at each module level is calculated using standard values, thereby identifying devices that are sensitive to reliability impacts.

5. The method for analyzing device aging sensitive points according to claim 4, characterized in that... The aging simulation of the N module levels is processed in parallel, that is, the aging simulation is performed on each module level in parallel to obtain the aging performance degradation index of each module level.

6. A method for analyzing device aging sensitive points according to claim 4 or 5, characterized in that... The aging simulation environment is the same for each module level, that is, the netlist and test bench used are the same.

7. The method for analyzing device aging sensitive points according to claim 6, characterized in that... The aforementioned aging performance degradation index threshold Through standard values The calculation is as follows: in, It is a set aging-related factor.

8. The method for analyzing device aging sensitive points according to claim 7, characterized in that... If the aging performance degradation index is less than the aging performance degradation index threshold This means that activating a damaged module level, the next level of circuit network, or the lowest level device MOSFET does not contribute to changes in circuit performance. If there is a difference and the result is greater than If necessary, a loop is run to resubmit several parallel aging simulations.

9. The method for analyzing device aging sensitive points according to claim 8, characterized in that... The resubmitted parallel aging simulations are at the same level, that is, the same level of module hierarchy, or the next level of circuit network, or the lowest level of device.

Images