Control device and control method thereof

Abstract

This invention discloses a control device and its control method. The control device is used to drive a display device including a first channel and includes a first output device. The first output device outputs first transfer data to the first channel according to an enable signal. The first transfer data includes a preamble and a function code. The first output device also includes a preamble generator and a function code generator. The preamble generator outputs a predetermined value of the number of bits as the preamble, based on the number of bits in the preamble. The number of bits and the predetermined value are defined by the user. The function code generator converts the instruction codes of the function code number into bit codes according to a lookup table. The bit codes of the function code number are output as function codes. The correspondence between the instruction codes and the bit codes is defined by the user and stored in the lookup table.

Description

Technical Field

[0001] This invention relates to a control device and control method for a display device, and more particularly to a control device and control method for display units that can be user-defined with preamble and function codes and which time-divisionally activate different channels to reduce resistance voltage drop. Background Technology

[0002] Backlight panels can be driven using various interface signals, with Bi-phase Mark Code (BMC) being one such signal interface. In backlight driving systems of different sizes, the resistive voltage drop (IR drop) of the supply voltage to the display device will affect the overall power consumption and image clarity. Therefore, it is necessary to optimize the backlight panel control method to reduce the IR drop of the display device's supply voltage.

[0003] Furthermore, when using this transmission interface, preambles or function codes are methods for the receiving end to determine the start of information data. However, during development, it often happens that designers provide incorrect k-code mapping tables. To improve design efficiency, it is necessary to develop a biphase marker code packet transmission synchronization format that can meet the needs of various current applications and also satisfy the requirements of any future system applications. Summary of the Invention

[0004] This invention proposes a control device and method for user-definable preamble and function codes. By redefining the preamble and function codes, the control device and method can be adapted to different needs. Furthermore, this invention also proposes a control device and method for time-division multiplexing display units on different channels to reduce resistive voltage drop. By staggering the time when different channels of different display devices receive the preamble and adjusting the bit width ratio of logic 0 to logic 1, the number of display units simultaneously activated is reduced, thereby reducing the degree of voltage drop caused by the supply voltage of the display device.

[0005] In view of this, the present invention proposes a control device for driving a display device, wherein the display device includes a first channel. The control device includes a first output device. The first output device outputs first transfer data to the first channel according to an enable signal, wherein the first transfer data includes a preamble and a function code. The first output device further includes a preamble generator and a function code generator. The preamble generator outputs a predetermined value of a number of bits as the preamble, wherein the number of bits and the predetermined value are defined by a user. The function code generator converts a number of instruction codes of a function code into one-bit codes according to a lookup table, wherein the bit codes of the number of function codes are output as the function codes, and the correspondence between the instruction codes and the bit codes is defined by the user and stored in the lookup table.

[0006] According to an embodiment of the present invention, the preamble generator includes a preamble bit length register, a preamble value register, a bit counter, a preamble shift register, and a bit comparator. The preamble bit length register stores the number of bits. The preamble value register stores a predetermined value. The bit counter counts according to the enable signal and a preamble enable signal to generate a first count value and a first shift signal. The preamble shift register shifts the predetermined value according to the first shift signal and outputs it as the preamble. The bit comparator compares the first count value with the number of bits to generate the preamble enable signal. When the first count value is not greater than the number of bits, the preamble enable signal enables the preamble bit counter to count and generate the first shift signal. When the first count value is greater than the number of bits, the preamble enable signal disables the preamble bit counter from counting and generating the first shift signal.

[0007] According to an embodiment of the present invention, the function code generator includes a function code count register, a function code register, a function code counter, a function code shift register, and a function code count comparator. The function code count register stores the function code count and the instruction code corresponding to the function code count. When the first count value is greater than the number of bits, the function code counter counts to generate a second count value and a second shift signal. The function code shift register outputs the instruction code stored in it sequentially according to the second shift signal. The function code count comparator compares the second count value and the function code count to generate a function code enable signal. The first output device further includes a lookup table register and a lookup table comparator. The lookup table register stores the lookup table. The lookup table comparator converts the instruction code into the corresponding bit code using the lookup table according to the function code enable signal. When the second count value is not greater than the number of function codes, the lookup table comparator converts the instruction code into the corresponding bit code. When the second count value is greater than the number of function codes, the lookup table comparator stops receiving the instruction code.

[0008] According to an embodiment of the present invention, the first transfer data further includes a data code. The first output device further includes a bit generator. The bit generator converts the bit code output by the lookup table comparator into a biphase marker code. When the bit code is at a first logic level, the biphase marker code switches once every half cycle. When the bit code is at a second logic level, the biphase marker code switches once per cycle.

[0009] According to an embodiment of the present invention, when the second count value is greater than the number of function codes, the lookup table comparator receives a first input data and generates the bit code corresponding to the first data according to the lookup table, and the bit generator converts the bit code corresponding to the first data into the biphase marker code and outputs it as the data code.

[0010] According to an embodiment of the present invention, the display device further includes a second channel. The control device further includes a second output device, a first delay generator, a second delay generator, a first multiplexer, and a second multiplexer. The second output device outputs second transfer data to the second channel according to the enable signal. The second transfer data includes the preamble, the function code, and the data code, wherein the second output device is the same as the first output device. The first delay generator generates a first trigger signal by counting a first delay time according to the enable signal. The second delay generator generates a second trigger signal by counting a second delay time according to the enable signal. The first multiplexer provides the first transfer data to the first channel according to the first trigger signal. The second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

[0011] According to an embodiment of the present invention, each of the first delay generator and the second delay generator includes a delay counter, a delay register, and a delay comparator. The delay counter counts a first time and / or a second time based on the enable signal and a clock signal. The delay register stores the first delay time or the second delay time. The delay comparator compares the first time and the first delay time to generate the first trigger signal, or compares the second time and the second delay time to generate the second trigger signal. When the first time equals the first delay time, the delay comparator generates the first trigger signal. When the second time equals the second delay time, the delay comparator generates the second trigger signal.

[0012] According to one embodiment of the present invention, one of the first output device and the second output device further includes a one-bit width register, a width counter, and a one-bit width comparator. The bit width register stores a one-bit width ratio. The width counter generates a counting signal based on a system clock. The bit width comparator generates a half-bit pulse and a full-bit pulse based on the bit width ratio and the counting signal. The ratio of the period of the full-bit pulse to the period of the half-bit pulse is the bit width ratio.

[0013] According to an embodiment of the present invention, when the bit code is the first logic level, the bit generator generates the biphase marker code that switches once every half cycle based on the half-bit pulse.

[0014] According to an embodiment of the present invention, when the bit code is the second logic level, the bit generator generates the biphase marker code that switches once per cycle based on the full bit pulse.

[0015] The present invention also proposes a control method for driving a display device. The control method includes outputting first transfer data to a first channel of the display device according to an enable signal. The first transfer data includes a preamble and a function code. The step of outputting the first transfer data to the first channel of the display device according to the enable signal further includes outputting a predetermined value of a number of bits in the preamble as the preamble, wherein the number of bits and the predetermined value are defined by a user; and converting a number of function code instruction codes into one-bit codes according to a lookup table. The bit codes of the number of function codes are output as the function codes, and the correspondence between the instruction codes and the bit codes is defined by the user and stored in the lookup table.

[0016] According to an embodiment of the present invention, the step of outputting the predetermined value of the number of bits as the preamble based on the number of bits of the preamble further includes storing the number of bits using a preamble bit length register; storing the predetermined value using a preamble value register; when a first count value is not greater than the number of bits, accumulating the first count value and generating a first shift signal; when the first count value is greater than the number of bits, stopping the accumulation of the first count value and stopping the generation of the first shift signal; and shifting the predetermined value according to the first shift signal to output the preamble.

[0017] According to an embodiment of the present invention, the step of converting the instruction code of the number of function codes into the bit code according to the lookup table includes: storing the number of function codes in a function code count register; storing the instruction code of the number of function codes in a function code count register; when the first count value is greater than the number of bits, accumulating a second count value and generating a second shift signal; outputting the instruction code stored in the function code count register sequentially according to the second shift signal; and when the second count value is not greater than the number of function codes, converting the instruction code into the corresponding bit code according to a lookup table.

[0018] According to an embodiment of the present invention, the first transfer data further includes a data code, wherein the control method further includes converting the bit code into a biphase marker code. The step of converting the bit code into the biphase marker code further includes switching the biphase marker code once every half cycle when the bit code is a first logic level; and switching the biphase marker code once per cycle when the bit code is a second logic level.

[0019] According to an embodiment of the present invention, the control method further includes receiving a first input data when the second count value is greater than the number of function codes; and generating a bit code corresponding to the first input data according to the lookup table, wherein the output of the biphase marker code corresponding to the bit code is the data code.

[0020] According to an embodiment of the present invention, the control method further includes outputting a second transfer data to a second channel of the display device according to the enable signal, wherein the second transfer data includes the preamble, the function code, and the data code; generating a first trigger signal and a second trigger signal respectively by counting a first delay time and a second delay time according to the enable signal; providing the first transfer data to the first channel according to the first trigger signal; and providing the second transfer data to the second channel according to the second trigger signal.

[0021] According to an embodiment of the present invention, the step of generating the first trigger signal and the second trigger signal respectively by counting the first delay time and the second delay time according to the enable signal further includes using a delay register to store the first delay time and the second delay time; counting a first time and a second time according to the enable signal and a clock signal; generating the first trigger signal when the first time is equal to the first delay time; and generating the second trigger signal when the second time is equal to the second delay time.

[0022] According to an embodiment of the present invention, the steps of outputting the first transfer data to the first channel of the display device according to the enable signal and outputting the second transfer data to the second channel of the display device according to the enable signal further include storing a bit width ratio using a bit width register; generating a counting signal according to a system clock; and generating a half-bit pulse and a full-bit pulse according to the bit width ratio and the counting signal. The ratio of the period of the full-bit pulse to the period of the half-bit pulse is the bit width ratio.

[0023] According to an embodiment of the present invention, the step of switching the biphase marker code once every half cycle further includes generating the biphase marker code that switches once every half cycle using the half-bit pulse when the bit code is the first logic level.

[0024] According to an embodiment of the present invention, the step of switching the biphase marker code once per cycle further includes generating the biphase marker code that switches once per cycle using the full-bit pulse when the bit code is the second logic level. Attached Figure Description

[0025] Figure 1 This is a block diagram showing a control device according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram showing the transfer data according to an embodiment of the present invention;

[0027] Figure 3 This is a block diagram showing an output device according to an embodiment of the present invention;

[0028] Figure 4 This is a block diagram showing a preamble generator according to an embodiment of the present invention;

[0029] Figure 5 This is a block diagram showing an output device according to an embodiment of the present invention;

[0030] Figure 6 This is a diagram showing the relationship between the bit code and the biphase marker code according to an embodiment of the present invention;

[0031] Figure 7 This is a block diagram showing a control device according to another embodiment of the present invention;

[0032] Figure 8 This is a display of the present invention. Figure 7 A schematic diagram of delayed data transfer as described in the embodiments;

[0033] Figure 9 This is a block diagram showing a delay generator according to an embodiment of the present invention;

[0034] Figure 10 This is a block diagram showing the output device according to another embodiment of the present invention;

[0035] Figures 11A-11B This is a display of the present invention. Figure 10 The waveform diagram of the biphase marker code described in the embodiment; and

[0036] Figure 12 This is a flowchart illustrating a control method according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures

[0038] 100, 700: Control device

[0039] 10: Display device

[0040] 111: First output device

[0041] 112: Second output device

[0042] 11N: Nth output device

[0043] 200: Transfer Data

[0044] 300, 500, 1000: Output devices

[0045] 310,400: Prefix generator

[0046] 320: Function Code Generator

[0047] 420: Prefix value temporary register

[0048] 430: Bit Counter

[0049] 440: Prefix Shift Register

[0050] 450: Bit Comparator

[0051] 510: Function Code Generator

[0052] 511: Function Code Count Register

[0053] 512: Function Code Register

[0054] 513: Function Code Counter

[0055] 514: Function Code Shift Register

[0056] 515: Function Code Number Comparator

[0057] 520: Lookup table temporary register

[0058] 530: Lookup Table Comparator

[0059] 540: Width Counter

[0060] 550: Bit-width comparator

[0061] 560: Bit Generator

[0062] 721: First Delay Generator

[0063] 722: Second Delay Generator

[0064] 72N: Nth Delay Generator

[0065] 731: First Multiplexer

[0066] 732: Second Multiplexer

[0067] 73N: The Nth Multiplexer

[0068] 800: Delayed data transfer

[0069] 900: Delay Generator

[0070] 910: Delay Counter

[0071] 920: Delay Register

[0072] 930: Delay Comparator

[0073] 1070: Bit-width register

[0074] 1200: Control Method

[0075] EN: Enable signal

[0076] CH1: First Channel

[0077] CH2: Second channel

[0078] CHN: Nth channel

[0079] DI: Input Data

[0080] DI1: First input data

[0081] DI2: Second Input Data

[0082] DIN: Nth input data

[0083] DT1: First transfer data

[0084] DT2: Second Transfer Data

[0085] DTN: Nth transfer data

[0086] PRE: Prefix

[0087] FNC: Function Code

[0088] DTC: Data Code

[0089] EOP: End of Packet

[0090] CC: Instruction Code

[0091] CC1: First instruction code

[0092] CC2: Second instruction code

[0093] CC3: Third instruction code

[0094] CC4: Fourth instruction code

[0095] D1: First Data

[0096] D2: Second Data

[0097] DM: Data of the Mth generation

[0098] Idle: Inactive

[0099] P1: Number of bits

[0100] P2: Number of function codes

[0101] PV: a predetermined value

[0102] ENPRE: Prefix Enable Signal

[0103] ENFC: Function Code Enable Signal

[0104] CV1: First count value

[0105] CV2: Second count value

[0106] SFT1: First shift signal

[0107] SFT2: Second shift signal

[0108] BTC:bit code

[0109] BMC: Bidirectional Marker Code

[0110] CLK: Clock signal

[0111] CNT: Counting signal

[0112] HBP: Half-position pulse

[0113] FBP: Full Position Pulse

[0114] LUT: Lookup Table

[0115] DL: Preset logic level

[0116] DLY: Delay Time

[0117] DLY1: First delay time

[0118] DLY2: Second delay time

[0119] DLYN: Nth delay time

[0120] TR1: First trigger signal

[0121] TR2: Second trigger signal

[0122] TRN: Nth trigger signal

[0123] DDT1: First Delayed Transfer Data

[0124] DDT2: Second Delayed Transfer Data

[0125] DDTN: Nth Delayed Transfer Data

[0126] TM: predetermined time

[0127] TR: Trigger signal

[0128] Q: Bit width ratio

[0129] S1210~S1230: Procedure Flow Detailed Implementation

[0130] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the invention and should not be considered as a limitation thereof. The scope of the invention should be determined by the scope of the claims.

[0131] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments of the present invention.

[0132] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit the scope of the invention. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on another feature may actually encompass multiple different embodiments, including direct contact between the features, or additional features formed between the features, such that the features are not in direct contact.

[0133] Figure 1 This is a block diagram showing a control device according to an embodiment of the present invention. Figure 1 As shown, the control device 100 is coupled to the display device 10, wherein the display device 10 includes a first channel CH1, a second channel CH2, ... and an Nth channel CHN. According to some embodiments of the present invention, the first channel CH1, the second channel CH2, ... and the Nth channel CHN each include at least one display unit.

[0134] The control device 100 includes a first output device 111, a second output device 112, ..., and an Nth output device 11N. The first output device 111, the second output device 112, ..., and the Nth output device 11N convert the first input data DI1, the second input data DI2, ..., and the Nth input data DIN into first transfer data DT1, second transfer data DT2, ..., and Nth transfer data DTN, respectively, according to the enable signal EN. Furthermore, the first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN are respectively provided to the corresponding first channel CH1, second channel CH2, ..., and Nth channel CHN of the display device 10.

[0135] Figure 2 This is a schematic diagram illustrating the transfer data according to an embodiment of the present invention. Figure 2 As shown, the transfer data 200 includes a preamble code (PRE), a functional code (FNC), a data code (DTC), and a packet end (EOP). According to an embodiment of the present invention, the transfer data 200 corresponds to... Figure 1 The first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN. The preamble PRE is used to... Figure 1 The display units of the first channel CH1, the second channel CH2, ... or the Nth channel CHN of the display device 10 are initially set.

[0136] The function code FNC includes a first instruction code CC1, a second instruction code CC2, a third instruction code CC3, and a fourth instruction code CC4. According to an embodiment of the present invention, the first instruction code CC1, the second instruction code CC2, the third instruction code CC3, and the fourth instruction code CC4 are used to set the synchronization format between the control device 100 and the display device 10.

[0137] The Data Code (DTC) includes first data D1, second data D2, ..., and the Mth data DM, where first data D1, second data D2, ..., and the Mth data DM are used to transmit control data for the corresponding display unit. The packet end (EOP) indicates the end of transmission.

[0138] According to one embodiment of the present invention, the transfer data 200 is in an idle state before the preamble PRE and after the end-of-packet EOP. Figure 2 As shown in the embodiment, the data transfer 200 is at a high logic level when in the idle state. According to another embodiment of the present invention, the data transfer 200 may also be at a low logic level when in the idle state.

[0139] Figure 3This is a block diagram showing an output device according to an embodiment of the present invention. Figure 3 As shown, the output device 300 includes a preamble generator 310 and a function code generator 320. According to an embodiment of the present invention, the output device 300 corresponds to... Figure 1 The first output device 111, the second output device 112, ... and the Nth output device 11N.

[0140] Prefix generator 310 generates prefix (PRE), and function code generator 320 generates function code (FNC). Output device 300 converts input data (DI) into data code (DTC), and sequentially outputs prefix (PRE), function code (FNC), data code (DTC), and end-of-packet (EOP) as transfer data (DT). According to an embodiment of the present invention, function code (FNC), data code (DTC), and end-of-packet (EOP) are biphase marker codes.

[0141] According to one embodiment of the present invention, Figure 3 The input data DI corresponds to Figure 1 The first input data DI1, the second input data DI2, ... and one of the Nth input data DIN. Figure 3 The transfer data DT corresponds to Figure 1 One of the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN. The generation of the preamble PRE, the function code FNC, and the data code DTC will be explained in detail below.

[0142] Figure 4 This is a block diagram showing a preamble generator according to an embodiment of the present invention. Figure 4 As shown, the preamble generator 400 includes a preamble bit length register 410, a preamble value register 420, a bit counter 430, a preamble shift register 440, and a bit comparator 450.

[0143] Prefix bit register 410 is used to store the number of bits P1 of the prefix PRE, and prefix value register 420 is used to store a predetermined value PV. According to some embodiments of the present invention, the prefix value register 420 stores the predetermined value PV corresponding to the number of bits P1. Bit counter 430 counts according to the enable signal EN and the prefix enable signal ENPRE to generate a first count value CV1 and a first shift signal SFT1. According to one embodiment of the present invention, the enable signal EN is equivalent to... Figure 1 The enable signal EN.

[0144] According to one embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 440 outputs the least significant bit (LSB) first, the predetermined value PV is 0xAA to facilitate the generation of the maximum number of logic transitions. According to another embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 440 outputs the most significant bit (MSB) first, the predetermined value PV is 0x55 to facilitate the generation of the maximum number of logic transitions.

[0145] According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 440 outputs the least significant bit (LSB) first, the predetermined value PV is 0x55. According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 440 outputs the most significant bit (MSB) first, the predetermined value PV is 0xAA.

[0146] According to other embodiments of the present invention, the given value PV may also be other values. Here, 0x55 and 0xAA are used only for illustrative purposes and are not limited to them in any way.

[0147] Prefix shift register 440 shifts a predetermined value PV according to the first shift signal SFT1 and outputs a prefix PRE. Bit comparator 450 compares the first count value CV1 with the bit number P1 and generates a prefix enable signal ENPRE.

[0148] When the first count value CV1 is not greater than the number of bits P1, the preamble enable signal ENPRE is at the first logic level, enabling the preamble bit counter 430 to continue counting. When the first count value CV1 is greater than the number of bits P1, the preamble enable signal ENPRE is at the second logic level and the preamble bit counter 430 is disabled and stops counting.

[0149] For example, suppose the number of bits P1 is 32, representing Figure 2 The preamble PRE shown has 32 bits. The bit counter 430 starts counting according to the enable signal EN and outputs a first count value CV1 and a first shift signal SFT1. The bit comparator 450 compares the first count value CV1 with the bit P1.

[0150] When the first count value CV1 is not greater than the number of bits P1, the bit comparator 450 uses the preamble enable signal ENPRE to control the bit counter 430 to continue counting. The preamble shift register 440 outputs the most significant bit or least significant bit of the predetermined value PV stored in the preamble value register 420 as the preamble PRE according to the first shift signal SFT1 generated by the bit counter 430.

[0151] When the first count value CV1 is greater than the number of bits P1 (in this embodiment, the first count value CV1 is 33 and the number of bits P1 is 32), the bit comparator 450 uses the preamble enable signal ENPRE to control the bit counter 430 to stop counting.

[0152] According to one embodiment of the present invention, since the preamble value register 420 stores a predetermined value PV for the corresponding bit P1, the preamble shift register 440 immediately stops outputting the preamble PRE after each bit of the preamble value register 420 is output. According to another embodiment of the present invention, when the bit counter 430 stops counting according to the preamble enable signal ENPRE, the bit counter 430 simultaneously stops generating the first shift signal SFT1.

[0153] Figure 5 This is a block diagram showing an output device according to an embodiment of the present invention. Figure 5 As shown, the output device 500 includes a function code generator 510, a lookup table temporary register 520, and a lookup table comparator 530. According to an embodiment of the present invention, the output device 500 combines... Figure 4 The preamble generator 400 corresponds to... Figure 1 One of the first output device 111, the second output device 112, ... and the Nth output device 11N.

[0154] like Figure 5 As shown, the function code generator 510 includes a function code number register 511, a function code register 512, a function code counter 513, a function code shift register 514, and a function code number comparator 515. The function code number register 511 is used to store the function code number P2, and the function code register 512 is used to store the instruction code CC of the function code number P2.

[0155] like Figure 2 As shown in the embodiment, the function code FNC includes four instruction codes, representing a function code number P2 of 4. Furthermore, the function code register 512 is used to sequentially store the first instruction code CC1, the second instruction code CC2, the third instruction code CC3, and the fourth instruction code CC4. According to some embodiments of the present invention, when the function code FNC includes Y instruction codes, the function code number register 511 stores a function code number P2 of Y, and the function code register 512 sequentially stores Y function codes.

[0156] Back Figure 5 Function code counter 513 according to Figure 4 The bit comparator 450 generates a preamble enable signal ENPRE, and starts counting to generate a second count value CV2 and a second shift signal SFT2. The function code shift register 514 outputs the instruction code CC stored in the function code register 514 sequentially according to the second shift signal SFT2. The function code count comparator 515 compares the second count value CV2 and the function code count P2, and generates a function code enable signal ENFC.

[0157] like Figure 2 As shown in the embodiment, when the second count value CV2 is 1, the function code shift register 514 outputs the first instruction code CC1; when the second count value CV2 is 2, the function code shift register 514 outputs the second instruction code CC2, and so on.

[0158] like Figure 5 As shown, the lookup table register 520 is used to store the lookup table LUT. The lookup table comparator 530 converts the instruction code CC and / or input data DI into the corresponding bit code BTC based on the function code enable signal ENFC and the lookup table LUT.

[0159] According to an embodiment of the present invention, when the second count value CV2 is not greater than the number of function codes P2, the lookup table comparator 530 operates in the first state according to the function code enable signal ENFC, so as to convert the instruction code CC into the corresponding bit code BTC.

[0160] According to another embodiment of the present invention, when the second count value CV2 is greater than the function code number P2, the lookup table comparator 530 operates in the second state according to the function code enable signal ENFC, so as to convert the input data DI into the corresponding bit code BTC.

[0161] like Figure 5 As shown, the output device 500 also includes a width counter 540, a bit width comparator 550, and a bit generator 560. The width counter 540 generates a counting signal CNT based on the clock signal CLK. The bit width comparator 550 generates a half-bit pulse HBP and a full-bit pulse FBP based on the counting signal CNT. The bit generator 560 converts the bit code BTC into a bidirectional tag code BMC.

[0162] According to one embodiment of the present invention, when the bit code BTC is logic 1, the biphase marker code BMC switches once every half cycle; when the bit code BTC is logic 0, the biphase marker code BMC switches once per cycle. According to another embodiment of the present invention, when the bit code BTC is logic 0, the biphase marker code BMC switches once every half cycle; when the bit code BTC is logic 1, the biphase marker code BMC switches once per cycle.

[0163] like Figure 3 Output device 300, Figure 4 Prefix generator 400 and Figure 5 As shown in the output device 500, the preamble generator 400 outputs a preamble PRE according to the enable signal EN. When the preamble PRE is output, the output device 500 is enabled to output the function code FNC by the preamble enable signal ENPRE. When the function code FNC is output, the output device 500 outputs the input data DI as the data code DTC according to the function code enable signal ENFC, where the function code FNC and the data code DTC are biphase marker codes BMC.

[0164] According to one embodiment of the present invention, when the data code DTC transmission is completed, the output device 500 also outputs the end-of-packet (EOP), wherein the end-of-packet (EOP) is a biphase marker code (BMC). In other words, apart from the preamble (PRE), the function code (FNC) of the transfer data DT, the data code DTC, and the end-of-packet (EOP) output by the output device 300 are all biphase marker codes (BMC).

[0165] Back Figure 5 When the designer provides an incorrect function code lookup table or needs to change the design, the requirements can be met by modifying the instruction code CC stored in function code register 512 and the lookup table LUT stored in lookup table register 520. Furthermore, users can also meet various different needs by modifying the function code number P2 stored in function code number register 511, the instruction code CC stored in function code register 512, and the lookup table LUT stored in lookup table register 520.

[0166] Figure 6 This is a diagram showing the relationship between bit codes and biphase marker codes according to an embodiment of the present invention. According to an embodiment of the present invention, Figure 6 The BTC code corresponds to Figure 5 The bit code BTC and the biphase marker code BMC correspond to... Figure 5 The biphase marker code BMC.

[0167] like Figure 6As shown, the bit code BTC is a combination of logic 0 and logic 1. When the bit code BTC is logic 0, the biphase marker code BMC changes once per cycle. When the bit code BTC is logic 1, the biphase marker code BMC changes once every half cycle.

[0168] According to another embodiment of the present invention, when the bit code BTC is logic 0, the biphase marker code BMC switches once every half cycle, and when the bit code BTC is logic 1, the biphase marker code BMC switches once per cycle. Figure 6 The embodiments shown are for illustrative purposes only and are not intended to limit the scope of the embodiments in any way.

[0169] Figure 7 This is a block diagram showing a control device according to another embodiment of the present invention. Figure 7 Control device 700 and Figure 1 Compared to the control device 100, the control device 700 further includes a first delay generator 721, a second delay generator 722, ..., an Nth delay generator 72N, a first multiplexer 731, a second multiplexer 732, ..., and an Nth multiplexer 73N.

[0170] The first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN respectively according to the enable signal EN, and generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN accordingly.

[0171] According to an embodiment of the present invention, the first multiplexer 731, the second multiplexer 732, ... and the Nth multiplexer 73N respectively provide the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the corresponding first channel CH1, the second channel CH2, ... and the Nth channel CHN according to the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN, so as to form the first delayed transfer data DDT1, the second delayed transfer data DDT2, ... and the Nth delayed transfer data DDTN.

[0172] According to another embodiment of the present invention, when the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N have not yet counted to the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, the corresponding first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN are not generated.

[0173] In other words, the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN are delayed by the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, respectively, before being provided to the corresponding first channel CH1, second channel CH2, ... and Nth channel CHN.

[0174] According to one embodiment of the present invention, when any one of the first delay generator 721, the second delay generator 722, ..., and the Nth delay generator 72N has not yet counted to the first delay time DLY1, the second delay time DLY2, ..., and the Nth delay time DLYN, the first multiplexer 731, the second multiplexer 732, ..., and the Nth multiplexer 73N provide a preset logic level DL to one of the corresponding channels CH1, CH2, ..., and CHN. According to one embodiment of the present invention, the preset logic level DL may be a high logic level. According to another embodiment of the present invention, the preset logic level DL may be a low logic level.

[0175] According to one embodiment of the present invention, the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N are different from each other, and the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are different from each other.

[0176] According to another embodiment of the present invention, at least two of the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N are the same, and at least two of the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are the same.

[0177] In other words, a first predetermined number of output devices share the first delay time generated by the first delay generator, and a second predetermined number of output devices share the second delay time generated by the second delay generator. Here, we use... Figure 7 The embodiments shown are for illustrative purposes only and are not intended to limit the scope of the embodiments in any way.

[0178] Figure 8 This is a display of the present invention. Figure 7 A schematic diagram of delayed data transfer as described in an embodiment. Figure 8 Delayed transfer data 800 and Figure 2 Compared to transfer data 200, delayed transfer data 800 also includes a delay time DLY before the preamble PRE.

[0179] According to one embodiment of the present invention, the delayed transfer data 800 corresponds to... Figure 7The first delayed transfer data DDT1, the second delayed transfer data DDT2, ..., and the Nth delayed transfer data DDTN, where the delay time DLY corresponds to... Figure 7 The first delay time is DLY1, the second delay time is DLY2, ..., and the Nth delay time is DLYN. In other words, the preamble PRE is provided only after a delay time DLY compared to the preamble PRE of the data 800.

[0180] In addition, such as Figure 7 In the illustrated embodiment, the first transfer data DT1, the second transfer data DT2, ..., and the Nth transfer data DTN are respectively delayed by the first delay time DLY1, the second delay time DLY2, ..., and the Nth delay time DLYN (corresponding to ... Figure 8 The delayed transfer data (800) is then provided to the corresponding first channel CH1, second channel CH2, ... and Nth channel CHN.

[0181] Figure 9 This is a block diagram showing a delay generator according to an embodiment of the present invention. Figure 9 As shown, the delay generator 900 includes a delay counter 910, a delay register 920, and a delay comparator 930. The delay counter 910 counts a predetermined time TM based on an enable signal EN and a clock signal CLK. The delay register 920 stores the delay time DLY, and the delay comparator 930 compares the predetermined time TM with the delay time DLY. According to an embodiment of the present invention, when the predetermined time TM equals the delay time DLY, the delay comparator 930 generates a trigger signal TR.

[0182] According to one embodiment of the present invention, the delay generator 900 is corresponding to... Figure 7 Any one of the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N. Figure 7 as well as Figure 9 As shown, the delay counters 910 of the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N count a predetermined time TM according to the enable signal EN and the clock signal CLK.

[0183] When the predetermined time TM counted by the first delay generator 721 is equal to the first delay time DLY1, the first delay generator 721 generates the first trigger signal TR1; when the predetermined time TM counted by the second delay generator 722 is equal to the second delay time DLY2, the second delay generator 722 generates the second trigger signal TR2, and so on.

[0184] According to another embodiment of the present invention, Figure 9The delay register 920 is used to store Figure 7 The delay time is defined as a first delay time DLY1, a second delay time DLY2, ..., and an Nth delay time DLYN. When the predetermined time TM counted by the delay counter 910 is equal to the first delay time DLY1, the delay comparator 930 generates a first trigger signal TR1; when the predetermined time TM counted by the delay counter 910 is equal to the second delay time DLY2, the delay comparator 930 generates a second trigger signal TR2, and so on.

[0185] Figure 10 This is a block diagram showing an output device according to another embodiment of the present invention. Compared to Figure 5 The output device 500, Figure 10 The output device 1000 further includes a bit width register 1070. The bit width register 1070 stores the bit width ratio Q, and the bit width comparator 550 further generates a half-bit pulse HBP and a full-bit pulse FBP based on the counting signal CNT and the bit width ratio Q. According to another embodiment of the present invention, Figure 4 Prefix generator 400 combined Figure 10 The output device 1000 is corresponding to Figure 1 or Figure 7 One of the first output device 111, the second output device 112, ... and the Nth output device 11N.

[0186] Figures 11A-11B This is a display of the present invention. Figure 10 The waveform diagram of the biphase marker code described in the embodiment. For example... Figure 11A As shown, when the bit width ratio Q is 1, it means that the bit width ratio of logic 0 and logic 1 in the biphase marker code BMC is 1:1. Therefore, the bit width of logic 0 in the biphase marker code BMC is the same as the bit width of logic 1.

[0187] like Figure 11B As shown, when the bit width ratio Q is 1.6, it means that the bit width of logic 0 in the biphase marker code (BMC) is 1.6 times the bit width of logic 1. In other words, the bit width of logic 0 in the biphase marker code (BMC) is greater than the bit width of logic 1.

[0188] like Figures 11A-11B As shown in the embodiment, the bit width of logic 1 is fixed, and the bit width ratio Q is used to adjust the bit width of logic 0. According to one embodiment of the invention, the bit width ratio Q is greater than 1 and less than 2. According to other embodiments of the invention, the bit width of logic 0 can also be fixed, and the bit width ratio Q can be used to adjust the bit width of logic 1.

[0189] Back Figure 10 , Figure 10The bit width comparator 550 adjusts the ratio of the full-wave pulse FBP to the half-wave pulse HBP based on the bit width ratio Q, thereby adjusting the bit width ratio of logic 0 to logic 1 in the biphase marker code BMC. According to one embodiment of the present invention, the ratio of the period of the full-wave pulse FBP to the period of the half-wave periodic pulse HBP is equal to the bit width ratio Q.

[0190] Back Figure 7 Because there are at least two different first delay times DLY1, second delay time DLY2, ... and Nth delay time DLYN, the turn-on times of the display units on the first channel CH1, second channel CH2, ... and Nth channel CHN are staggered. Furthermore, the bit width ratio Q of the first transfer data DT1, second transfer data DT2, ... and Nth transfer data DTN is not 1, resulting in different conversion times for different transfer data. Therefore, the turn-on times of different display units are further staggered, thereby reducing the degree of voltage drop caused by the supply voltage of the display device.

[0191] Figure 12 This is a flowchart illustrating a control method according to an embodiment of the present invention. The following is for... Figure 12 The description of control method 1200 will be combined with Figure 7 The control device 700 is described in detail below.

[0192] First, based on the enable signal EN, using Figure 7 The first output device 711, the second output device 712, ... and the Nth multiplexer 73N generate first transfer data DT1, second transfer data DT2, ... and Nth transfer data DTN (step S1210).

[0193] like Figure 3 , Figure 4 as well as Figure 5 As shown in the embodiment, based on the enable signal EN, the preamble PRE, function code FNC, data code DTC, and transfer data DT at the end of the packet EOP are generated sequentially. Figure 3 , Figure 4 as well as Figure 10 As shown in the embodiment, the bit width ratio Q is the ratio of the logic 0 and logic 1 of the generated function code FNC, data code DTC, and packet end EOP, based on the enable signal EN and the bit width ratio Q.

[0194] Back Figure 12 Based on the enable signal EN, using Figure 7The first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, and generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN respectively (step S1220).

[0195] like Figure 9 As shown in the embodiment, a predetermined time TM is counted, and when the predetermined time TM equals the delay time DLY (corresponding to... Figure 7 When the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN are reached, a trigger signal TR (corresponding to...) is generated. Figure 7 The first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN).

[0196] Back Figure 12 Based on the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN, the first multiplexer 731, the second multiplexer 732, ... and the Nth multiplexer 73N respectively provide the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the corresponding first channel CH1, the second channel CH2, ... and the Nth channel CHN of the display device 10 (step S1230).

[0197] like Figure 7 As shown in the embodiment, since the first delay generator 721, the second delay generator 722, ... and the Nth delay generator 72N are used to count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN to generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN respectively, the first multiplexer 731, the second multiplexer 732, ... and the Nth multiplexer 73N delay the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN respectively before providing the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the first channel CH1, the second channel CH2, ... and the Nth channel CHN respectively, thereby reducing the degree of voltage drop caused by the supply voltage of the display device.

[0198] This invention proposes a control device and method for user-definable preamble and function codes. By redefining the preamble and function codes, the control device and method can be adapted to different needs. Furthermore, this invention also proposes a control device and method for time-division multiplexing display units on different channels to reduce resistive voltage drop. By staggering the time when different channels of different display devices receive the preamble and adjusting the bit width ratio of logic 0 to logic 1, the number of display units simultaneously activated is reduced, thereby reducing the degree of voltage drop caused by the supply voltage of the display device.

[0199] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of the present invention, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claims and embodiments.

Claims

1. A control device for driving a display device, characterized in that, The display device includes a first channel, and the control device includes: A first output device outputs first transfer data to the first channel according to an enable signal, wherein the first transfer data includes a preamble and a function code, and wherein the first output device further includes: A preamble generator, based on a preamble of one bit, outputs a predetermined value of the preamble as the preamble, wherein the number of bits and the predetermined value are defined by a user; and A function code generator converts a number of instruction codes into one-bit codes according to a lookup table, wherein the bit codes of the number of function codes are output as the function codes, and the correspondence between the instruction codes and the bit codes is redefined by the user and stored in the lookup table.

2. The control device as described in claim 1, characterized in that, The preamble generator includes: A prefix bit length register is provided to store the bit length. A preamble value register is used to store the predetermined value; A one-bit counter, based on the enable signal and a preamble enable signal, counts to generate a first count value and a first shift signal. A preamble shift register, which shifts the predetermined value according to the first shift signal and outputs the preamble; and A single-digit comparator compares the first count value with the number of bits to generate the preamble enable signal, wherein when the first count value is not greater than the number of bits, the preamble enable signal enables the preamble bit counter to count and generates the first shift signal, wherein when the first count value is greater than the number of bits, the preamble enable signal disables the preamble bit counter to count and generates the first shift signal.

3. The control device as described in claim 2, characterized in that, The function code generator includes: A function code number register is provided to store the number of function codes. A function code register is used to store the instruction codes for the number of function codes; A function code counter, wherein when the first count value is greater than the number of bits, the function code counter counts to generate a second count value and a second shift signal; A function code shift register sequentially outputs the instruction codes stored in the function code shift register according to the second shift signal; and A function code count comparator compares the second count value with the function code count to generate a function code enable signal; The first output device further includes: A lookup table temporary register for storing the lookup table; and A lookup table comparator converts the instruction code into the corresponding bit code using the lookup table according to the function code enable signal. When the second count value is not greater than the number of function codes, the lookup table comparator converts the instruction code into the corresponding bit code. When the second count value is greater than the number of function codes, the lookup table comparator stops receiving the instruction code.

4. The control device as described in claim 3, characterized in that, The first transfer data further includes a data code, wherein the first output device further includes: A generator converts the bit code output by the lookup table comparator into a biphase marker code, wherein when the bit code is a first logic level, the biphase marker code switches once every half cycle, and when the bit code is a second logic level, the biphase marker code switches once per cycle.

5. The control device as described in claim 4, characterized in that, The display device further includes a second channel, and the control device further includes: A second output device outputs a second transfer data to the second channel according to the enable signal, wherein the second transfer data includes the preamble, the function code, and the data code, wherein the second output device is the same as the first output device; A first delay generator generates a first trigger signal by counting a first delay time according to the enable signal; A second delay generator, based on the enable signal, counts a second delay time to generate a second trigger signal; A first multiplexer, based on the first trigger signal, provides the first transfer data to the first channel; and A second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

6. The control device as described in claim 5, characterized in that, One of the first output device and the second output device further includes: A one-bit width register stores the width ratio; A width counter that generates a counting signal based on a system clock; and A bit width comparator generates a half-bit pulse and a full-bit pulse based on the bit width ratio and the counting signal, wherein the ratio of the period of the full-bit pulse to the period of the half-bit pulse is the bit width ratio.

7. The control device as described in claim 6, characterized in that, When the bit code is the first logic level, the bit generator generates the biphase marker code that switches once every half cycle based on the half-bit pulse.

8. A control method for driving a display device, characterized in that, The control method includes: According to an enable signal, a first transfer data is output to a first channel of the display device, wherein the first transfer data includes a preamble and a function code, and the step of outputting the first transfer data to the first channel of the display device according to the enable signal further includes: Based on a single digit of the preamble, a predetermined value of that digit is output as the preamble, wherein the digit and the predetermined value are defined by a user; and Based on a lookup table, convert each function code number of instruction codes into a single-bit code; The bit code output of the number of function codes is the function code, and the correspondence between the instruction code and the bit code is redefined by the user and stored in the lookup table.

9. The control method as described in claim 8, characterized in that, The step of outputting the predetermined value of the number of bits as the preamble based on the number of bits of the preamble further includes: The number of bits is stored using a preamble bit register; The predetermined value is stored using a preamble value register; When a first count value is not greater than the number of bits, the first count value is accumulated and a first shift signal is generated; When the first count value is greater than the number of bits, the accumulation of the first count value stops and the generation of the first shift signal stops; and Based on the first shift signal, the predetermined value is shifted and output as the preamble.

10. The control method as described in claim 9, characterized in that, The step of converting the instruction codes of the number of function codes into the bit codes according to the lookup table includes: The number of function codes is stored in a function code count register. The instruction codes for the number of function codes are stored in a function code register; When the first count value is greater than the number of bits, a second count value is accumulated and a second shift signal is generated. Based on the second shift signal, the instruction codes stored in the function code register are output sequentially; and When the second count value is not greater than the number of function codes, the instruction code is converted into the corresponding bit code according to a lookup table.

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