Diamond-based gallium nitride transistor preparation method and diamond-based gallium nitride transistor

Abstract

The application is suitable for the technical field of semiconductor devices, and provides a diamond-based gallium nitride transistor preparation method and a diamond-based gallium nitride transistor. The method comprises the following steps: preparing an electrode field plate area on the upper surface of a silicon-based gallium nitride wafer; sputtering a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of a silicon wafer, and performing pre-bonding; temporarily bonding a carrier and the silicon wafer; removing the silicon substrate of the silicon-based gallium nitride wafer to obtain a gallium nitride epitaxial layer supported by the silicon wafer, and sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer and the upper surface of a diamond, and performing bonding; removing the carrier, the silicon wafer and the first metal layer to obtain a diamond-based gallium nitride wafer; and performing metal interconnection on the electrodes and the field plates on the upper surface of the diamond-based gallium nitride wafer to obtain a diamond-based gallium nitride transistor. The application can effectively improve the bonding effect, and further improve the output power of the prepared diamond-based gallium nitride transistor.

Description

Technical Field

[0001] This application belongs to the field of semiconductor device technology, and particularly relates to a method for fabricating a diamond-based gallium nitride transistor and the diamond-based gallium nitride transistor. Background Technology

[0002] Gallium nitride (GaN), as a wide bandgap semiconductor material, possesses numerous advantages such as a large bandgap, high breakdown field strength, high electron saturation drift velocity, and high thermal conductivity, making it highly promising for applications in high-speed, high-power switching and radio frequency power device manufacturing. Diamond, with its high thermal conductivity (typically 800-2000 W / mK), is therefore frequently used as a heat dissipation substrate for GaN devices in related technologies.

[0003] In related technologies, there are three main methods for bonding diamond wafers and gallium nitride (GaN) wafers: The first method involves directly epitaxially growing GaN on a diamond wafer. This method has a complex growth process, and lattice mismatch can lead to high dislocation density, resulting in poor quality GaN wafers. The second method involves growing diamond on GaN wafers. However, since diamond growth requires chemical vapor deposition (CVD) at temperatures exceeding 600°C, this method can affect the quality of the grown diamond. To avoid the poor quality of GaN and diamond wafers caused by the above two methods, the third method involves bonding the diamond and GaN wafers using a dielectric layer. However, in application, this method suffers from significant differences in the thermal expansion coefficients of diamond and GaN, increased on-chip ripples due to device interconnect processes, and wafer deformation caused by directly using flexible adhesive in contact with the GaN wafer. These issues result in poor bonding performance, affecting the output power of the fabricated diamond-based GaN transistors. Summary of the Invention

[0004] This application provides a method for fabricating a diamond-based gallium nitride transistor and a diamond-based gallium nitride transistor, in order to solve the technical problem in the related art where the bonding effect between diamond wafers and gallium nitride wafers is poor, resulting in low output power of the fabricated diamond-based gallium nitride transistor.

[0005] This application is achieved through the following technical solution:

[0006] In a first aspect, embodiments of this application provide a method for fabricating a diamond-based gallium nitride (GaN) transistor, comprising: fabricating an electrode field plate region on the upper surface of a silicon-based GaN wafer, the electrode field plate region including a gate, a source, a drain, and a field plate; sputtering a first metal layer on the upper surface of the silicon-based GaN wafer and the upper surface of the electrode field plate region to form a first bonding surface, and sputtering a first metal layer on the upper surface of the silicon wafer to form a second bonding surface; placing the first bonding surface of the silicon-based GaN wafer and the second bonding surface of the silicon wafer opposite to each other for pre-bonding; coating a die-attach adhesive on the upper surface of a carrier to form a third bonding surface, and placing the third bonding surface of the carrier opposite to the fourth bonding surface of the silicon wafer for temporary bonding; the fourth bonding surface of the silicon wafer is the surface opposite to the second bonding surface of the silicon wafer.

[0007] The silicon substrate of the silicon-based gallium nitride (GaN) wafer is removed to obtain a GaN epitaxial layer supported by the silicon wafer. A second metal layer or a dielectric layer is sputtered onto the lower surface of the GaN epitaxial layer to form a fifth bonding surface. A second metal layer or a dielectric layer is sputtered onto the upper surface of the diamond wafer to form a sixth bonding surface. The fifth bonding surface of the GaN epitaxial layer and the sixth bonding surface of the diamond wafer are placed opposite each other and bonded. The adhesive, carrier, silicon wafer, first bonding surface, and second bonding surface are removed to obtain a diamond-based GaN wafer. The gate, source, drain, and field plate on the upper surface of the diamond-based GaN wafer are interconnected to form an interconnect metal layer, resulting in a diamond-based GaN transistor.

[0008] In conjunction with the first aspect, in some possible implementations, before sputtering a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a first bonding surface, and before sputtering the first metal layer on the upper surface of the silicon wafer to form a second bonding surface, the method further includes: depositing a dielectric on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a protective layer, and polishing the protective layer.

[0009] In conjunction with the first aspect, in some possible implementations, the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer are placed opposite each other for bonding, including: placing the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer opposite each other, applying pressure sequentially from the center to the edge of the diamond wafer for preliminary bonding, and obtaining a pre-bonded wafer; wherein the pressure in the preliminary bonding is 2000-4000 mbar and the time is 1-3 minutes; and bonding the pre-bonded wafer; wherein the pressure in the bonding is 4000-6000 mbar, the time is 10-12 hours, and the temperature is 100-150°C.

[0010] In conjunction with the first aspect, in some possible implementations, a first bonding surface of a gallium nitride (GaN) silicon wafer and a second bonding surface of a silicon wafer are placed opposite each other for pre-bonding, including: placing the first bonding surface of the GaN silicon wafer and the second bonding surface of the silicon wafer opposite each other, applying pressure sequentially from the center to the edge of the silicon wafer to obtain bonded GaN silicon wafers and silicon wafers; and pre-bonding the bonded GaN silicon wafers and silicon wafers; wherein the pressure during pre-bonding is 6500–8000 mbar, the time is 1–2 hours, and the temperature is 150–250°C.

[0011] In conjunction with the first aspect, in some possible implementations, the silicon substrate of the silicon-based gallium nitride wafer is removed to obtain a gallium nitride epitaxial layer supported by the silicon wafer, including: thinning and polishing the silicon substrate of the silicon-based gallium nitride wafer to a predetermined thickness; and etching the remaining silicon substrate with an corrosive liquid to obtain a gallium nitride epitaxial layer supported by the silicon wafer.

[0012] In conjunction with the first aspect, in some possible implementations, before sputtering a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a first bonding surface, and before sputtering a first metal layer on the upper surface of the silicon wafer to form a second bonding surface, the method further includes cleaning the silicon-based gallium nitride wafer and the silicon wafer.

[0013] In conjunction with the first aspect, in some possible implementations, before sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and before sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, the method further includes cleaning the gallium nitride epitaxial layer and the diamond wafer.

[0014] After sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, the process further includes: activating the gallium nitride epitaxial layer and the diamond wafer using plasma.

[0015] In conjunction with the first aspect, in some possible implementations, the first metal layer is, from bottom to top, a titanium layer, a tungsten layer, and a gold layer; the second metal layer is, from bottom to top, a metal buffer layer and a gold layer, wherein the metal buffer layer is a titanium layer, a molybdenum layer, or an aluminum layer; and the dielectric layer is a silicon nitride layer, a silicon dioxide layer, or a silicon layer.

[0016] Secondly, embodiments of this application provide a diamond-based gallium nitride transistor, obtained by applying the diamond-based gallium nitride transistor fabrication method as described in any one of the first aspects; the diamond-based gallium nitride transistor includes: a multilayer structure consisting of a diamond wafer, a second metal layer or dielectric layer, and gallium nitride, arranged from bottom to top; an electrode field plate region disposed on the upper surface of gallium nitride, the electrode field plate region including a gate, a source, a drain, and a field plate; and an interconnect metal layer disposed on the upper surface of the electrode field plate region, wherein the gate, source, drain, and field plate in the electrode field plate region are interconnected via the interconnect metal layer.

[0017] In conjunction with the second aspect, in some possible implementations, the diamond-based gallium nitride transistor also includes a protective layer disposed on the upper surface of the gallium nitride and the upper surface of the electrode field plate region.

[0018] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0019] The beneficial effects of the embodiments in this application compared with the prior art are:

[0020] The diamond-based gallium nitride (GaN) transistor fabrication method and the diamond-based GaN transistor provided in this application embodiment involve fabricating an electrode field plate region on the upper surface of a silicon-based GaN wafer, and sputtering a first metal layer on the upper surface of the GaN wafer, the upper surface of the electrode field plate region, and the upper surface of the silicon wafer for pre-bonding. Then, a carrier is temporarily bonded to the silicon wafer, and the silicon substrate of the GaN wafer is removed to obtain a GaN epitaxial layer supported by the silicon wafer. A second metal layer or a dielectric layer is sputtered on the lower surface of the GaN epitaxial layer and the upper surface of the diamond wafer for bonding. Finally, the electrodes and field plate on the upper surface of the obtained diamond-based GaN wafer are interconnected to obtain a diamond-based GaN transistor. By setting up pre-bonding, performing final metal interconnection, ensuring a slow and linear heating and cooling process during the fabrication process, and ensuring that the maximum temperature does not exceed 200°C, the bonding effect can be effectively improved, thereby increasing the output power of the fabricated diamond-based GaN transistor.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1This is a schematic diagram of the structure of a diamond-based gallium nitride transistor provided in an embodiment of this application;

[0024] Figure 2 This is a schematic flowchart of a method for fabricating a diamond-based gallium nitride transistor according to an embodiment of this application;

[0025] Figure 3 This is a schematic diagram of the structure after the electrode field plate region is fabricated according to an embodiment of this application;

[0026] Figure 4 This is a schematic diagram of the structure after the protective layer is formed, according to an embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the structure after polishing the protective layer according to an embodiment of this application;

[0028] Figure 6 This is a schematic diagram of the structure after sputtering the first metal layer according to an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the pre-bonded structure provided in an embodiment of this application;

[0030] Figure 8 This is a schematic diagram of the structure after temporary bonding provided in an embodiment of this application;

[0031] Figure 9 This is a schematic diagram of the structure after removing the silicon substrate according to an embodiment of this application;

[0032] Figure 10 This is a schematic diagram of the structure after sputtering a second metal layer or depositing a dielectric layer according to an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the bonded structure provided in one embodiment of this application;

[0034] Figure 12 This is a schematic diagram of the structure of a diamond-based gallium nitride wafer provided in an embodiment of this application.

[0035] Figure label:

[0036] 1: Electrode field plate region; 2: Gallium nitride / gallium nitride epitaxial layer; 31: Silicon substrate; 32: Silicon wafer; 4: Protective layer; 5: New metal layer; 51: First bonding surface; 52: Second bonding surface; 6: Carrier; 7: Second metal layer or dielectric layer; 71: Fifth bonding surface; 72: Sixth bonding surface; 8: Diamond wafer; 9: Interconnect metal layer. Detailed Implementation

[0037] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0038] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0039] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0040] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0041] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0043] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.

[0044] Figure 1 This is a schematic diagram of the structure of a diamond-based gallium nitride transistor provided in an embodiment of this application. Figure 1 As shown, this diamond-based gallium nitride transistor is obtained using a method for fabricating diamond-based gallium nitride transistors, including:

[0045] From bottom to top, the structure consists of a diamond wafer 8, a second metal layer or dielectric layer 7, and gallium nitride 2, forming a multilayer structure.

[0046] Electrode field plate region 1 is disposed on the upper surface of gallium nitride 2. Electrode field plate region 1 includes gate, source, drain and field plate.

[0047] An interconnect metal layer 9 is disposed on the upper surface of the electrode field plate region 1, and the gate, source, drain and field plate in the electrode field plate region 1 are interconnected by the interconnect metal layer 9.

[0048] Optionally, in this embodiment, the diamond-based gallium nitride transistor may further include a protective layer 4, which is disposed on the upper surface of the gallium nitride 2 and the upper surface of the electrode field plate region 1.

[0049] The following combination Figure 1 The method for fabricating diamond-based gallium nitride transistors according to embodiments of this application will be described in detail.

[0050] Figure 2 This is a schematic flowchart of a method for fabricating a diamond-based gallium nitride transistor according to an embodiment of this application. (Refer to...) Figure 2 The detailed method for fabricating diamond-based gallium nitride transistors is described below:

[0051] Step 101: Prepare an electrode field plate region on the upper surface of a silicon-based gallium nitride wafer. The electrode field plate region includes a gate, a source, a drain, and a field plate.

[0052] For example, see Figure 3 In this embodiment, the silicon-based gallium nitride wafer includes a silicon substrate 31 and gallium nitride 2, and a gate, source, drain and field plate are fabricated on the upper surface of gallium nitride 2.

[0053] Step 102: Sputter a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a first bonding surface, and then sputter a first metal layer on the upper surface of the silicon wafer to form a second bonding surface.

[0054] In one possible implementation, prior to step 102, this embodiment may also deposit a dielectric on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a protective layer, and then polish the protective layer.

[0055] For example, see Figure 4 and Figure 5A dielectric material can be deposited on the upper surface of gallium nitride 2 and the upper surface of electrode field plate region 1 to form a protective layer 4. The protective layer 4 is then polished to make its upper surface smooth and flat. The deposited dielectric material can be silicon dioxide or silicon nitride, with a thickness at least 1.5 times the height of the in-wafer undulations, which is 1.5 times the height of electrode field plate region 1. After polishing, the thickness of the dielectric material deposited on the upper surface of electrode field plate region 1 is at least 1 micrometer. For example, a silicon dioxide layer with a thickness of 2 micrometers can be deposited as the protective layer 4, and the protective layer 4 can be chemically mechanically polished, resulting in a silicon dioxide layer thickness of 1 micrometer on the upper surface of electrode field plate region 1 after polishing.

[0056] In this embodiment, the protective layer is smooth and flat, uniformly covering the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate area, effectively protecting the silicon-based gallium nitride wafer and the electrode field plate area.

[0057] Optional, see Figure 6 In (a) of this embodiment, a first metal layer is sputtered on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region 1 to form a first bonding surface 51. Alternatively, a first metal layer can be sputtered on the upper surface of the protective layer 4 to form a first bonding surface 51.

[0058] For example, see Figure 6 In (b) of this embodiment, a first metal layer is sputtered on the upper surface of the silicon wafer 32 to form a second bonding surface 52.

[0059] Optionally, in this embodiment, the first metal layer consists of a titanium layer, a tungsten layer, and a gold layer from bottom to top. For example, a titanium layer, a tungsten layer, and a gold layer are sequentially sputtered onto the upper surface of the protective layer 4 and the upper surface of the silicon wafer 32, respectively. The thickness of the titanium layer can be 10–30 nanometers, the thickness of the tungsten layer can be 30–50 nanometers, and the thickness of the gold layer can be 300–500 nanometers.

[0060] In one possible implementation, prior to step 102, the silicon-based gallium nitride wafer and the silicon wafer may also be cleaned.

[0061] For example, in this embodiment, the silicon-based gallium nitride wafer and the silicon wafer 32 can be ultrasonically cleaned sequentially with acetone, ethanol, and deionized water for 20 minutes. Cleaning can remove impurities, oxide layers, particles, and contaminants from the surfaces of the silicon-based gallium nitride wafer and the silicon wafer 32, reducing particle size and roughness, and improving surface quality. This effectively improves the subsequent pre-bonding effect between the silicon-based gallium nitride wafer and the silicon wafer 32. Of course, other cleaning methods can also be used, and no specific limitations are made here.

[0062] Step 103: Place the first bonding surface of the silicon-based gallium nitride wafer opposite to the second bonding surface of the silicon wafer for pre-bonding.

[0063] In one possible implementation, the pre-bonding process may include: placing the first bonding surface of the gallium nitride silicon wafer opposite to the second bonding surface of the silicon wafer, applying pressure sequentially from the center to the edge of the silicon wafer to obtain a bonded gallium nitride silicon wafer and a silicon wafer; and pre-bonding the bonded gallium nitride silicon wafer and the silicon wafer.

[0064] The pre-bonding process involves a pressure of 6500–8000 mbar, a time of 1–2 hours, and a temperature of 150–250 °C.

[0065] For example, see Figure 7 In this embodiment, during pre-bonding, the bonded gallium nitride silicon wafer and silicon wafer are placed in a bonding machine to complete the pre-bonding. The pre-bonding can be performed without exposure to the atmosphere. After pre-bonding, the first bonding surface 51 and the second bonding surface 52 become a single unit, referred to as the new metal layer 5. In other words, the new metal layer 5 includes the first bonding surface 51 and the second bonding surface 52.

[0066] In this embodiment, before the temporary bonding between the carrier and the silicon wafer, a pre-bonding is performed between the silicon-based gallium nitride wafer and the silicon wafer. This pre-bonds the silicon-based gallium nitride wafer and the silicon wafer into a single unit, preventing direct contact between the flexible adhesive and gallium nitride during the subsequent temporary bonding with the carrier. Consequently, it ensures that the silicon-based gallium nitride wafer will not undergo "bow"-shaped deformation due to excessive or uneven stress during the subsequent removal of the silicon substrate, thus guaranteeing the effectiveness of silicon substrate removal and subsequent bonding.

[0067] Step 104: Coat the substrate surface with adhesive to form the third bonding surface. Place the third bonding surface of the substrate opposite to the fourth bonding surface of the silicon wafer and perform temporary bonding.

[0068] The fourth bonding surface of the silicon wafer 32 is the surface opposite to the second bonding surface 52 of the silicon wafer 32.

[0069] For example, see Figure 8 In this embodiment, adhesive is applied to the upper surface of the carrier 6, and the carrier 6 coated with adhesive is baked to obtain the third bonding surface. The adhesive can be applied to the upper surface of the carrier 6 by spin coating at a speed of 1500–3000 rpm for 60–90 seconds. The upper surface of the carrier 6 coated with adhesive can be placed upwards on a hot plate for baking at a temperature of 100–200°C for 3–5 minutes.

[0070] Optionally, in this embodiment, after the third bonding surface of the carrier 6 and the fourth bonding surface of the silicon wafer 32 are placed opposite each other and bonded, they are placed in a die bonder for temporary bonding.

[0071] Step 105: Remove the silicon substrate from the silicon-based gallium nitride wafer to obtain a gallium nitride epitaxial layer supported by the silicon wafer. Sputter a second metal layer or deposit a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface. Sputter a second metal layer or deposit a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface.

[0072] In one possible implementation, when removing the silicon substrate of the silicon-based gallium nitride wafer to obtain a gallium nitride epitaxial layer supported by the silicon wafer, the silicon substrate of the silicon-based gallium nitride wafer can be thinned and polished to a preset thickness, and the remaining silicon substrate can be etched using an corrosive liquid to obtain a gallium nitride epitaxial layer supported by the silicon wafer.

[0073] For example, see Figure 9 In this embodiment, the silicon substrate 31 of the gallium nitride wafer can be thinned to a preset thickness, such as 80 micrometers, by mechanical grinding. The corrosive liquid can be a mixture of nitric acid, hydrofluoric acid, and deionized water in a preset ratio.

[0074] For example, see Figure 10 In embodiment (a), a second metal layer or a dielectric layer is sputtered or deposited on the lower surface of the gallium nitride epitaxial layer 2 to form a fifth bonding surface 71. See also Figure 10 In (b) of this embodiment, a second metal layer or a dielectric layer is sputtered or deposited on the surface of the diamond wafer 8 to form a sixth bonding surface 72.

[0075] Optionally, in this embodiment, the second metal layer consists of a metal buffer layer and a gold layer from bottom to top. The metal buffer layer is a titanium layer, a molybdenum layer, or an aluminum layer. The thickness of the metal buffer layer can be 5–20 nanometers, and the thickness of the gold layer can be 10–50 nanometers. In this embodiment, the dielectric layer is a silicon nitride layer, a silicon dioxide layer, or a silicon layer, and the thickness of the dielectric layer can be 5–20 nanometers.

[0076] It should be noted that the gallium nitride in the aforementioned embodiments and the gallium nitride epitaxial layer in this embodiment are the same material, namely gallium nitride, only described differently in different steps according to specific needs. Therefore, gallium nitride and the gallium nitride epitaxial layer are represented by the same designation as the same material, for example, both gallium nitride and the gallium nitride epitaxial layer are represented by designation 2.

[0077] In one possible implementation, before sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and before sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, the gallium nitride epitaxial layer and the diamond wafer can be cleaned.

[0078] For example, in this embodiment, the gallium nitride epitaxial layer 2 and the diamond wafer 8 can be ultrasonically cleaned sequentially with acetone, ethanol, and deionized water for 20 minutes. Cleaning removes impurities, oxide layers, particles, and contaminants from the surfaces of the gallium nitride epitaxial layer 2 and the diamond wafer 8, reducing particle size and roughness, and improving surface quality. This effectively improves the bonding effect between the subsequent gallium nitride epitaxial layer 2 and the diamond wafer 8. Of course, other cleaning methods can also be used, and no specific limitations are made here.

[0079] In one possible implementation, after sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, plasma can be used to activate the gallium nitride epitaxial layer and the diamond wafer.

[0080] For example, in this embodiment, argon or nitrogen plasma can be used to activate the fifth bonding surface 71 of the gallium nitride epitaxial layer 2 and the sixth bonding surface 72 of the diamond wafer 8. The argon or nitrogen plasma can be generated by gas discharge with a discharge power of 50–200 W and an activation time of 1–10 minutes. The activation process can generate dangling bonds on the surfaces of the gallium nitride epitaxial layer 2 and the diamond wafer 8, creating new covalent bonds between the two bonding surfaces, and remove the surface oxide layer, thereby effectively improving the subsequent bonding effect between the gallium nitride epitaxial layer 2 and the diamond wafer 8.

[0081] Step 106: Place the fifth bonding surface of the gallium nitride epitaxial layer opposite to the sixth bonding surface of the diamond wafer and perform bonding.

[0082] In one possible implementation, the bonding process may include: placing the fifth bonding surface of the gallium nitride epitaxial layer opposite to the sixth bonding surface of the diamond wafer, applying pressure sequentially from the center to the edge of the diamond wafer to perform preliminary bonding, and obtaining a pre-bonded wafer; and then bonding the pre-bonded wafer.

[0083] The initial bonding process involves a pressure of 2000–4000 mbar and a time of 1–3 minutes; the bonding process involves a pressure of 4000–6000 mbar and a time of 10–12 hours, with a temperature of 100–150°C.

[0084] For example, see Figure 11 In this embodiment, during the initial bonding process, manual pressure can be applied sequentially from the center to the edge of the diamond wafer 8 to obtain a bonded gallium nitride epitaxial layer and diamond wafer. Afterward, the bonded gallium nitride epitaxial layer and diamond wafer are annealed and then placed into a bonding machine, or directly into the bonding machine to complete the bonding. The initial bonding is performed in an atmospheric environment, while the final bonding is performed in a vacuum environment. The annealing process is carried out in a nitrogen atmosphere, with the temperature slowly and linearly increased to 200°C for 2 hours. After bonding, the fifth bonding surface 71 and the sixth bonding surface 72 become a single unit, referred to as the second metal layer or dielectric layer 7. That is, the second metal layer or dielectric layer 7 includes the fifth bonding surface 71 and the sixth bonding surface 72. See [link to documentation]. Figure 1 and Figure 11 wait.

[0085] It should be noted that the bonded gallium nitride epitaxial layer and diamond wafer obtained in this embodiment are actually the entirety of the diamond wafer 8, the second metal layer or dielectric layer 7, the gallium nitride epitaxial layer 2, the electrode field plate region 1, the protective layer 4, the new metal layer 5, the silicon wafer 32 and the carrier 6. For ease of description, it is referred to here as the bonded gallium nitride epitaxial layer and diamond wafer.

[0086] Step 107: Remove the adhesive, carrier, silicon wafer, first bonding surface and second bonding surface to obtain a diamond-based gallium nitride wafer.

[0087] For example, see Figure 12 In this embodiment, the bonded assembly is immersed in a die adhesive removal solution, and ultrasonic vibration is used to accelerate the dissolution of the die adhesive, removing the die adhesive and the carrier 6. As mentioned above, the assembly includes a diamond wafer 8, a second metal layer or dielectric layer 7, a gallium nitride epitaxial layer 2, an electrode field plate region 1, a protective layer 4, a new metal layer 5 (i.e., the first bonding surface 51 and the second bonding surface 52), a silicon wafer 32, and the carrier 6. Subsequently, a wet etching process is used to sequentially remove the silicon wafer 32, the first bonding surface 51, and the second bonding surface 52 during pre-bonding, that is, to remove the silicon wafer 32 and the new metal layer 5, obtaining a diamond-based gallium nitride wafer. The wet etching process can include four steps: first, a mixture of nitric acid, hydrofluoric acid and deionized water is used to remove the silicon wafer 32; then, hydrogen peroxide solution is used to etch the titanium and tungsten layers in the new metal layer 5; next, gold etchant is used to etch the gold layer in the new metal layer 5; and finally, hydrogen peroxide solution is used to etch the tungsten and titanium layers in the new metal layer 5.

[0088] Step 108: Perform metal interconnection on the gate, source, drain and field plate on the upper surface of the diamond-based gallium nitride wafer to form an interconnect metal layer, thereby obtaining a diamond-based gallium nitride transistor.

[0089] For example, see Figure 1 As mentioned above, a protective layer 4 can be formed on the upper surface of gallium nitride 2 and the upper surface of the electrode field plate region 1. In this embodiment, the upper surface of the diamond-based gallium nitride transistor, namely the electrode plate region 1 and / or the protective layer 4, is sequentially subjected to photolithography, etching, photolithography, sputtering, photolithography, electroplating and etching processes to complete the metal interconnection of the gate, source, drain and field plate on the upper surface of the diamond-based gallium nitride wafer, forming an interconnect metal layer 9, and finally obtaining the diamond-based gallium nitride transistor.

[0090] In this embodiment, the gallium nitride epitaxial layer is transferred and bonded before metal interconnection. The gallium nitride epitaxial layer is transferred onto a diamond wafer to obtain a diamond-based gallium nitride wafer. Then, metal interconnection is performed on the gate, source, drain and field plate on the upper surface of the diamond-based gallium nitride wafer. This can avoid the situation where the protective layer of the metal interconnected electrode field plate area is difficult to uniformly cover due to the metal interconnection, and at the same time reduce the probability of damage to the metal interconnected electrode field plate area during the transfer and bonding of the gallium nitride epitaxial layer.

[0091] Furthermore, it should be noted that in this embodiment, all heating and cooling processes are slow and linear. As mentioned above, the highest temperature in all steps does not exceed 200°C. Therefore, the slow and linear heating and cooling processes and the maximum temperature not exceeding 200°C in this embodiment effectively avoid problems such as sudden temperature changes and excessively high temperatures leading to cracking and warping, given the significant difference in thermal expansion coefficients between diamond and gallium nitride, thereby improving the bonding effect.

[0092] The above-described method for fabricating diamond-based gallium nitride (GaN) transistors involves preparing an electrode field plate region on the upper surface of a silicon-based GaN wafer, sputtering a first metal layer on the upper surface of the GaN wafer, the upper surface of the electrode field plate region, and the upper surface of the silicon wafer for pre-bonding, then temporarily bonding the carrier to the silicon wafer, removing the silicon substrate of the GaN wafer to obtain a GaN epitaxial layer supported by the silicon wafer, sputtering a second metal layer or depositing a dielectric layer on the lower surface of the GaN epitaxial layer and the upper surface of the diamond wafer for bonding, and finally interconnecting the electrodes and field plate on the upper surface of the obtained diamond-based GaN wafer to obtain a diamond-based GaN transistor. The method incorporates pre-bonding, final metal interconnection, and ensures a slow, linear heating and cooling process with a maximum temperature not exceeding 200°C, effectively improving the bonding effect and thus increasing the output power of the fabricated diamond-based GaN transistor.

[0093] A simple example is the fabrication steps of the diamond-based gallium nitride transistor fabrication method described in this application, based on a silicon-based gallium nitride wafer:

[0094] (1) An electrode field plate region is prepared on the upper surface of a silicon-based gallium nitride wafer. The electrode field plate region includes a gate, a source, a drain, and a field plate.

[0095] (2) A silicon dioxide layer with a thickness of 2 micrometers is deposited on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate area, and the silicon dioxide layer is chemically and mechanically polished to obtain a silicon dioxide layer with a smooth and flat upper surface and a thickness of 1 micrometer on the upper surface of the electrode field plate area, which serves as a protective layer.

[0096] (3) The silicon-based gallium nitride wafer and the silicon wafer were ultrasonically cleaned in sequence with acetone, ethanol and deionized water for 20 minutes.

[0097] (4) A 20-nanometer-thick titanium layer, a 40-nanometer-thick tungsten layer and a 400-nanometer-thick gold layer are sputtered on the upper surface of the protective layer to form the first bonding surface, and a 20-nanometer-thick titanium layer, a 40-nanometer-thick tungsten layer and a 400-nanometer-thick gold layer are sputtered on the upper surface of the silicon wafer to form the second bonding surface.

[0098] (5) Under conditions without exposure to the atmosphere, the first surface to be bonded of the silicon-based gallium nitride wafer and the second surface to be bonded of the silicon wafer are placed opposite each other and brought into contact. Pressure is applied sequentially from the center to the edge of the silicon wafer to obtain bonded silicon-based gallium nitride wafers and silicon wafers. The bonded silicon-based gallium nitride wafers and silicon wafers are then placed in a bonding machine for pre-bonding at a pressure of 8000 mbar for 1 hour and a temperature of 200°C. After pre-bonding, the first surface to be bonded and the second surface to be bonded become a single unit, referred to as the new metal layer.

[0099] (6) Apply the adhesive to the upper surface of the carrier at a speed of 1500 rpm for 1 minute, and place the carrier with the adhesive-coated upper surface upward on a hot plate for baking at 180°C for 3 minutes to obtain the third bonding surface. The surface of the silicon wafer opposite to the second bonding surface of the silicon wafer is used as the fourth bonding surface of the silicon wafer. After the third bonding surface of the carrier and the fourth bonding surface of the silicon wafer are placed opposite each other and in contact, they are placed in the die bonder for temporary bonding.

[0100] (7) The silicon substrate of the silicon-based gallium nitride wafer is thinned to 80 micrometers by mechanical grinding. Then, the remaining silicon substrate is etched by a mixed liquid of nitric acid, hydrofluoric acid and deionized water in a ratio of 35:1:14 to remove the silicon substrate and obtain a gallium nitride epitaxial layer supported by the silicon wafer.

[0101] (8) The gallium nitride epitaxial layer and the diamond wafer were ultrasonically cleaned in sequence with acetone, ethanol and deionized water for 20 minutes.

[0102] (9) A 10 nm thick titanium layer and a 20 nm thick gold layer were sputtered on the lower surface of the gallium nitride epitaxial layer to form the fifth bonding surface, and a 10 nm thick titanium layer and a 20 nm thick gold layer were sputtered on the upper surface of the diamond wafer to form the sixth bonding surface. Then, the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer were activated using argon plasma. The discharge power of the argon plasma was 100 W and the activation time was 5 minutes.

[0103] (10) Under atmospheric conditions, the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer are placed opposite each other and in contact. Preliminary bonding is performed manually, applying pressure sequentially from the center to the edge of the diamond wafer at a pressure of 2000–4000 mbar for 1 minute, resulting in a preliminarily bonded wafer. Then, the preliminarily bonded wafer is placed in a bonding machine for bonding at a pressure of 6000 mbar for 10 hours and a temperature of 150°C. After bonding, the fifth and sixth bonding surfaces become a single unit, referred to as the second metal layer or dielectric layer.

[0104] (11) The bonded assembly was immersed in a die adhesive removal solution, and ultrasonic vibration was used to accelerate the dissolution of the die adhesive and remove the die adhesive and carrier. Then, the pre-bonded silicon wafer was removed by coupled plasma etching, and the titanium and tungsten layers in the new metal layer were etched sequentially with hydrogen peroxide solution, the gold layer in the new metal layer was etched with gold etchant, and the tungsten and titanium layers in the new metal layer were etched with hydrogen peroxide solution to obtain a diamond-based gallium nitride wafer.

[0105] (12) Photolithography, etching, photolithography, sputtering, photolithography, electroplating and etching processes are sequentially performed on the electrode plate area and / or protective layer on the upper surface of the diamond-based gallium nitride transistor to complete the metal interconnection of the gate, source, drain and field plate on the upper surface of the diamond-based gallium nitride wafer, forming an interconnection metal layer, and thus obtaining the diamond-based gallium nitride transistor.

[0106] Another simple example is the fabrication steps of the diamond-based gallium nitride transistor fabrication method described in this application, based on a silicon-based gallium nitride wafer:

[0107] (1)~(8).

[0108] The specific implementation of steps (1) to (8) in this example is the same as steps (1) to (8) in the previous example, and will not be repeated here.

[0109] (19) A 10 nm thick silicon nitride layer was deposited on the lower surface of the gallium nitride epitaxial layer using plasma-enhanced chemical vapor deposition (PECVD) to form the fifth bonding surface, and a 10 nm thick silicon nitride layer was deposited on the upper surface of the diamond wafer to form the sixth bonding surface. Subsequently, oxygen plasma was used to activate the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer. The discharge power of the oxygen plasma was 100 W, and the activation time was 5 minutes.

[0110] (20) Rinse the activated gallium nitride epitaxial layer and diamond wafer with a large amount of deionized water to ensure that the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer are covered with deionized water. Then, place the gallium nitride epitaxial layer and diamond wafer into a culture dish filled with deionized water. At the same time, use a wash bottle containing deionized water to inject deionized water into the culture dish again to reduce air bubbles in the culture dish. Then, in the deionized water environment of the culture dish, use tweezers to place and contact the fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer, apply pressure and press for 1 minute to perform spontaneous preliminary bonding, and obtain a preliminarily bonded wafer. Afterward, absorb the deionized water in the culture dish, place the culture dish in a nitrogen atmosphere for annealing, and slowly and linearly increase the annealing temperature from room temperature to 200°C for 2 hours. Then, the annealed wafer is placed in a bonding machine for bonding at a pressure of 6000 mbar for 10 hours and a temperature of 150°C. After bonding, the fifth and sixth surfaces to be bonded become a single unit, referred to as the second metal layer or dielectric layer.

[0111] (11)~(12).

[0112] The specific implementation of steps (11) to (12) in this example is the same as steps (11) to (12) in the previous example, and will not be repeated here.

[0113] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0114] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for fabricating a diamond-based gallium nitride transistor, characterized in that, include: An electrode field plate region is fabricated on the upper surface of a silicon-based gallium nitride wafer. The electrode field plate region includes a gate, a source, a drain, and a field plate. A first metal layer is sputtered on the upper surface of the gallium nitride silicon wafer and the upper surface of the electrode field plate region to form a first bonding surface, and a first metal layer is sputtered on the upper surface of the silicon wafer to form a second bonding surface; the first bonding surface of the gallium nitride silicon wafer and the second bonding surface of the silicon wafer are placed opposite each other for pre-bonding. Adhesive is coated on the upper surface of the carrier to form a third bonding surface. The third bonding surface of the carrier is placed opposite to the fourth bonding surface of the silicon wafer for temporary bonding. The fourth bonding surface of the silicon wafer is the surface opposite to the second bonding surface of the silicon wafer. The silicon substrate of the silicon-based gallium nitride wafer is removed to obtain a gallium nitride epitaxial layer supported by the silicon wafer. A second metal layer or a dielectric layer is sputtered onto the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface. A second metal layer or a dielectric layer is sputtered onto the upper surface of the diamond wafer to form a sixth bonding surface. The fifth bonding surface of the gallium nitride epitaxial layer and the sixth bonding surface of the diamond wafer are placed opposite each other for bonding. Remove the adhesive, the carrier, the silicon wafer, the first bonding surface, and the second bonding surface to obtain a diamond-based gallium nitride wafer; Metal interconnects are formed on the gate, source, drain and field plate on the upper surface of the diamond-based gallium nitride wafer to form an interconnect metal layer, thereby obtaining a diamond-based gallium nitride transistor.

2. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, Before sputtering a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a first bonding surface, and before sputtering a first metal layer on the upper surface of the silicon wafer to form a second bonding surface, the process further includes: A dielectric material is deposited on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a protective layer, and the protective layer is polished.

3. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, The step of placing the fifth bonding surface of the gallium nitride epitaxial layer opposite to the sixth bonding surface of the diamond wafer for bonding includes: The fifth bonding surface of the gallium nitride epitaxial layer is placed opposite to the sixth bonding surface of the diamond wafer, and pressure is applied sequentially from the center to the edge of the diamond wafer to perform preliminary bonding, thereby obtaining a preliminarily bonded wafer; wherein, the pressure in the preliminary bonding is 2000-4000 millibars and the time is 1-3 minutes; The wafer after preliminary bonding is then bonded; wherein the bonding pressure is 4000-6000 mbar, the time is 10-12 hours, and the temperature is 100-150°C.

4. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, The step of placing the first bonding surface of the gallium nitride silicon wafer opposite to the second bonding surface of the silicon wafer for pre-bonding includes: The first bonding surface of the silicon-based gallium nitride wafer and the second bonding surface of the silicon wafer are placed opposite each other, and pressure is applied sequentially from the center to the edge of the silicon wafer to obtain a bonded silicon-based gallium nitride wafer and a silicon wafer; The bonded gallium nitride silicon wafer and silicon wafer are pre-bonded; wherein the pre-bonding pressure is 6500-8000 mbar, the time is 1-2 hours, and the temperature is 150-250°C.

5. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, The step of removing the silicon substrate from the silicon-based gallium nitride wafer to obtain a gallium nitride epitaxial layer supported by the silicon wafer includes: The silicon substrate of the silicon-based gallium nitride wafer is thinned and polished to a predetermined thickness; The remaining silicon substrate is etched using a corrosive liquid to obtain a gallium nitride epitaxial layer supported by the silicon wafer.

6. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, Before sputtering a first metal layer on the upper surface of the silicon-based gallium nitride wafer and the upper surface of the electrode field plate region to form a first bonding surface, and before sputtering a first metal layer on the upper surface of the silicon wafer to form a second bonding surface, the process further includes: The silicon-based gallium nitride wafer and the silicon wafer are cleaned.

7. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, Before sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and before sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, the process further includes: The gallium nitride epitaxial layer and the diamond wafer are cleaned; After sputtering a second metal layer or depositing a dielectric layer on the lower surface of the gallium nitride epitaxial layer to form a fifth bonding surface, and sputtering a second metal layer or depositing a dielectric layer on the upper surface of the diamond wafer to form a sixth bonding surface, the process further includes: The gallium nitride epitaxial layer and the diamond wafer are activated using plasma.

8. The method for fabricating a diamond-based gallium nitride transistor according to claim 1, characterized in that, The first metal layer consists of a titanium layer, a tungsten layer, and a gold layer from bottom to top; The second metal layer consists of a metal buffer layer and a gold layer from bottom to top, wherein the metal buffer layer is a titanium layer, a molybdenum layer, or an aluminum layer; The dielectric layer is a silicon nitride layer, a silicon dioxide layer, or a silicon layer.

9. A diamond-based gallium nitride transistor, characterized in that, The diamond-based gallium nitride transistor is obtained by the method for fabricating a diamond-based gallium nitride transistor as described in any one of claims 1 to 8; the diamond-based gallium nitride transistor comprises: From bottom to top, the structure consists of a diamond wafer, a second metal layer or dielectric layer, and a multilayer structure formed by gallium nitride. An electrode field plate region is disposed on the upper surface of the gallium nitride, and the electrode field plate region includes a gate, a source, a drain, and a field plate; An interconnect metal layer is disposed on the upper surface of the electrode field plate region, and the gate, the source, the drain and the field plate in the electrode field plate region are interconnected by the interconnect metal layer.

10. The diamond-based gallium nitride transistor according to claim 9, characterized in that, Also includes: A protective layer is disposed on the upper surface of the gallium nitride and the upper surface of the electrode field plate region.

Images