Method, apparatus, medium, and wafer manufacturing method for eliminating wafer surface defects

Abstract

Embodiments of the present application disclose a method and device for eliminating wafer surface defects, a medium and a wafer manufacturing method. The method for eliminating wafer surface defects comprises: obtaining an associated defect type having a quantity correlation with a linear defect; determining a cause defect of the linear defect from the associated defect type; wherein the cause defect is a first generation reason of the linear defect; obtaining a second generation reason of the linear defect in a wafer processing process; generating a first elimination measure for reducing the quantity of the cause defect and a second elimination measure for indicating modification of a processing parameter in the wafer processing process respectively according to the first generation reason and the second generation reason; wherein the first elimination measure and the second elimination measure can reduce the quantity of the linear defect on the wafer surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a method, apparatus, medium and wafer manufacturing method for eliminating defects on the wafer surface. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, defects on wafers have an increasingly significant impact on device performance, making strict control over wafer defects particularly important.

[0003] Surface defects on wafers directly affect the quality and reliability of semiconductor manufacturing processes, such as photolithography, thin film deposition, etching and corrosion processes, and metal electrode fabrication. As manufacturing processes continue to evolve, existing methods for controlling wafer surface defects have become insufficient, necessitating more refined and stringent measures. Summary of the Invention

[0004] In view of this, embodiments of the present invention aim to provide a method, apparatus, medium, and wafer manufacturing method for eliminating defects on the wafer surface; capable of reducing the occurrence of small-size defects on the silicon wafer surface and improving wafer quality and reliability.

[0005] The technical solution of this invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a method for eliminating defects on a wafer surface, the method comprising:

[0007] Obtain the associated defect types that are quantitatively correlated with linear defects;

[0008] The causal defect of the linear defect is determined from the associated defect types; wherein the causal defect is the first cause of the linear defect.

[0009] To determine the second cause of the linear defect during wafer fabrication;

[0010] For the first and second causes of defects, a first elimination measure to reduce the number of defects and a second elimination measure to indicate the modification of processing parameters in the wafer processing process are generated respectively; wherein the first and second elimination measures can reduce the number of linear defects on the wafer surface.

[0011] In some examples, in the defect type pair, the number of linear defects is positively correlated with the number of causal defects.

[0012] In some examples, the causative defect is a residual defect.

[0013] In some examples, determining the causative defect of the linear defect from the associated defect types includes:

[0014] During wafer polishing, the residual defect is identified as the causative defect of the linear defect based on the chemical and physical reaction between the filler material present in the microcracks at local locations on the wafer surface and the high temperature generated during polishing, which forms a linear defect.

[0015] In some examples, obtaining a second cause of the linear defect during wafer fabrication includes:

[0016] In the wafer polishing process, the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect is determined as the second cause.

[0017] In some examples, the generation of a first elimination measure to reduce the number of causal defects and a second elimination measure to indicate modifications to processing parameters during wafer fabrication, for the first and second causes of occurrence, respectively, includes:

[0018] Based on the first cause, the first elimination measure is determined to be to reduce the amount of residual organic matter on the wafer surface to reduce the residual defects;

[0019] Based on the second cause, the second elimination measure is determined to be changing the movement trajectory of the polishing particles at the edge of the wafer.

[0020] In some examples, the second elimination measure includes:

[0021] In the wafer polishing process, truncated spherical polishing particles are used to polish the wafer surface to change the movement trajectory of the polishing particles at the edge of the wafer.

[0022] Secondly, embodiments of the present invention provide an apparatus for eliminating defects on the surface of a wafer, the apparatus comprising:

[0023] The system comprises a first acquisition section, a determination section, a second acquisition section, and a measure generation section, wherein...

[0024] The first acquisition part is configured to acquire associated defect types that are quantitatively correlated with linear defects;

[0025] The determining portion is configured to determine the causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect.

[0026] The second acquisition portion is configured to acquire a second cause of the linear defect during the wafer fabrication process;

[0027] The measure generation section is configured to generate a first elimination measure for reducing the number of causal defects and a second elimination measure for instructing modification of processing parameters during wafer fabrication, respectively, for the first cause and the second cause; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0028] Thirdly, embodiments of the present invention provide a computing device, the computing device comprising: a processor and a memory; the processor being configured to execute instructions stored in the memory to implement the method for eliminating wafer surface defects as described in the first aspect and any example thereof.

[0029] Fourthly, embodiments of the present invention provide a computer storage medium, characterized in that the storage medium stores at least one instruction, the at least one instruction being executed by a processor to implement the method for eliminating wafer surface defects as described in the first aspect and any example of the first aspect.

[0030] Fifthly, embodiments of the present invention provide a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the electronic device to perform a method for eliminating wafer surface defects as described in the first aspect and any example of the first aspect.

[0031] Sixthly, embodiments of the present invention provide a wafer manufacturing method, the method comprising:

[0032] According to the method for eliminating wafer surface defects as described in the first aspect and any example of the first aspect, a first elimination measure and a second elimination measure for eliminating linear defects are determined.

[0033] During wafer fabrication, the first elimination measure and the second elimination measure are used to eliminate linear defects on the wafer surface.

[0034] This invention provides a method, apparatus, medium, and wafer manufacturing method for eliminating wafer surface defects. It determines the causal defects of linear defects based on quantity correlation, and reduces the number of linear defects by decreasing the number of causal defects. Furthermore, it modifies the processing parameters during wafer fabrication based on the production mechanism of linear defects in the wafer fabrication process. By combining these two measures, the number of small-size defects on the wafer surface is reduced, and the wafer fabrication quality is improved. Attached Figure Description

[0035] Figure 1This is a schematic flowchart of a method for eliminating wafer surface defects provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram illustrating the combined defect statistics of multiple polished wafers provided in an embodiment of the present invention.

[0037] Figure 3 A schematic diagram illustrating the correlation between the number of two types of defects provided in an embodiment of the present invention;

[0038] Figure 4 (A) and (B) are schematic diagrams of residual defects provided in the embodiments of the present invention;

[0039] Figure 5 A schematic diagram of the distribution of linear defects provided in an embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the polishing equipment provided in an embodiment of the present invention;

[0041] Figure 7 This is a schematic diagram of the movement direction of polishing particles provided in an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of the morphology of a discontinuous linear defect provided in an embodiment of the present invention;

[0043] Figure 9 A schematic diagram of polishing particles in the shape of a truncated sphere provided in an embodiment of the present invention;

[0044] Figure 10 A schematic diagram of a device for eliminating wafer surface defects provided in an embodiment of the present invention;

[0045] Figure 11 A schematic diagram of the structure of a computing device provided in an embodiment of the present invention;

[0046] Figure 12 This is a schematic diagram of a wafer manufacturing method provided in an embodiment of the present invention. Detailed Implementation

[0047] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0048] While methods for controlling defects on the wafer surface can prevent the presence of large-sized defects, the reliability requirements of advanced processes necessitate even more refined and stringent methods to control wafer surface defects. Improving the control of small-sized defects on the wafer surface is one such method.

[0049] For small-sized defects on the wafer surface, embodiments of the present invention aim to determine elimination measures for small-sized defects on the wafer surface by combining the correlation between the number of defects and the defect production mechanism in the wafer processing. This will reduce the number of small-sized defects on the wafer surface and improve the wafer processing quality.

[0050] Based on this, see Figure 1 This invention illustrates a method for eliminating wafer surface defects, which can be applied to a computing device. The method includes:

[0051] S101: Obtain the associated defect types that are quantitatively correlated with linear defects;

[0052] Typically, after wafer fabrication is completed and before shipment, wafer defects need to be inspected. Taking polished wafers as an example, the final processing step is cleaning. After cleaning, a scanning electron microscope (SEM) can be used to inspect the surface of the polished wafer, obtaining an image of the polished wafer surface. Subsequently, the location of defects can be determined on the polished wafer surface image. Then, at the corresponding defect locations, based on the image features corresponding to different defect types (such as aspect ratio, edge slope, near-circularity, and slope variance group statistics), machine learning models, classification algorithms, etc., are used to determine the type of defect present at each defect location, and the number of defects of each type is counted.

[0053] Each polished wafer that has undergone the cleaning process was subjected to defect detection using the methods described above, and the detection results were combined and statistically analyzed. Common surface defects on polished wafers include particle defects, line jut defects, fat jut defects, mechanical pit defects, residual defects, and scratch defects. In some examples, the above defects from multiple polished wafers were combined and statistically analyzed, as shown in the following figures. Figure 2 As shown, from Figure 2 As can be seen, the main type of defect on the polished wafer surface is the line jut defect.

[0054] In some examples, by statistically analyzing the defect types and quantities for each polished wafer, it can be found that... Figure 3As shown, taking defect detection on 13 polished wafers as an example, there is a positive correlation between the number of line jut defects and residual defects. That is, the more line jut defects there are, the more residual defects there are; and the fewer line jut defects there are, the fewer residual defects there are.

[0055] S102: Determine the causal defect of the linear defect from the associated defect types;

[0056] Wherein, the causal defect is the first cause of the linear defect;

[0057] In this embodiment of the invention, the quantitative correlation between linear defects and residual defects indicates that both types of defects are caused by the same defective process. Furthermore, there is a certain degree of causal relationship between the quantitatively correlated defects; that is, if the quantity of one type of defect (e.g., defect A) is reduced, then even without additional treatment of the other type of defect (e.g., defect B), the quantity of defect B will decrease accordingly. Based on this, the causal defect is defect A, and the linear defect is defect B. In some examples, this causal relationship can be determined based on the defect formation mechanism, thereby determining that the residual defect is the causal defect of the linear defect. The specific determination process can be found in the subsequent implementation methods and examples of this step.

[0058] S103: Obtain the second cause of the linear defect during the wafer fabrication process;

[0059] In this embodiment of the invention, the causes of linear defects are not singular. Besides the residual defects described in the preceding steps, the processing technology and methods used in wafer fabrication can also contribute to the generation of linear defects. In some examples, a second cause of linear defects during wafer fabrication can be determined based on the distribution of linear defects on the wafer surface image, combined with the processing trajectory and the resulting physical and chemical changes. In some examples, the process for determining the second cause can also be found in the subsequent descriptions of the implementation methods and examples of this step.

[0060] S104: For the first cause and the second cause, generate a first elimination measure to reduce the number of the causal defects and a second elimination measure to indicate the modification of the processing parameters in the wafer processing process, respectively; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface.

[0061] In some examples of embodiments of the present invention, based on the first cause of occurrence obtained in S102 above, the number of causal defects can be reduced based on the causal relationship between causal defects and linear defects, thereby correspondingly reducing the number of linear defects. Thus, only one measure is needed to effectively and significantly reduce the number of both types of defects, thereby improving wafer quality.

[0062] In some examples, based on the second cause obtained in S103 above, the processing parameters, such as the processing technology and methods used in wafer fabrication, can be modified to eliminate linear defects generated during wafer fabrication. In this example, when modifying the processing parameters, it is not necessary to consider the causal defects, but only the generation mechanism of linear defects during the processing. This reduces the coupling between the two elimination measures and avoids the introduction of additional defects when the two elimination measures are implemented.

[0063] The above technical solution identifies the causal defects of linear defects based on quantitative correlation, and reduces the number of linear defects by decreasing the number of causal defects. Furthermore, based on the production mechanism of linear defects in wafer fabrication, the processing parameters during wafer fabrication are modified. By combining these two measures, the number of small-sized defects on the wafer surface is reduced, thereby improving wafer fabrication quality.

[0064] Based on the aforementioned technical solution, in some possible implementations, determining the causal defect of the linear defect from the associated defect types includes:

[0065] During wafer polishing, the residual defect is identified as the causative defect of the linear defect based on the chemical and physical reaction between the filler material present in the microcracks at local locations on the wafer surface and the high temperature generated during polishing, which forms a linear defect.

[0066] Specifically, in the above implementation, during wafer polishing, dislocations are generated on the silicon wafer surface. These dislocations propagate and coalesce to form larger linear cracks. Most of these cracks are propagations of microcracks that occur after exceeding the critical fracture size, ultimately leading to surface breakage at that location. Furthermore, a small number of cracks, due to impurities or pinning effects between cracks, do not reach the critical size and therefore do not propagate as microcracks, thus allowing these few cracks to remain at their corresponding local locations.

[0067] During the polishing process, silicon dust, additives in the polishing slurry such as acid-base adjusters, and other organic media fill these small areas of cracks. As the polishing process continues, the localized high temperatures generated during polishing cause a reaction between the filler and the crack, thereby enhancing the adhesion of the filler. See also Figure 4 (A) and (B) show schematic diagrams of residual defects. Based on the above explanation, the morphology of this defect in the images is similar to that of linear defects. Therefore, there is a positive correlation between the number of residual defects and the number of linear defects. That is, the more residual material, such as organic matter, there is, the more organic matter will enter the crack, thus forming more linear defects.

[0068] Based on the above explanation, for the pair of defect types, residual defects and linear defects, residual defects are one of the causes of linear defects. Therefore, the causal defect is a residual defect.

[0069] Based on the aforementioned technical solution, in some possible implementations, obtaining the second cause of the linear defect during wafer fabrication includes:

[0070] In the wafer polishing process, the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect is determined as the second cause.

[0071] Regarding the above implementation method, specifically, cracks with filling material should exhibit a uniform distribution on the wafer surface; that is, linear defects should also be uniformly distributed on the wafer surface. However, see... Figure 5 The diagram showing the distribution of linear defects in the image reveals two main points: First, linear defects do not exhibit a uniform distribution; rather, they are fewer at the wafer center and more numerous at the wafer edges. Second, at the edges, the direction of linear defects generally aligns with the tangent direction of the wafer edge, while the direction of linear defects closer to the wafer center loses this pattern.

[0072] To analyze the above schematic diagram of linear defect distribution, the polishing process needs to be analyzed first. In this embodiment of the invention, combined with... Figure 6As shown in the schematic diagram of the polishing equipment, the polishing equipment generally includes an upper platen 61, a wafer carrier 62, and a lower platen 63. The upper platen 61 and the lower platen 63 rotate in opposite directions, and the polishing slurry flows down from the holes 64 evenly distributed in the upper platen 61. Through the relative rotation of the upper and lower platens and the polishing slurry, the wafer surface is polished, thereby eliminating mechanical damage and defects on the wafer surface.

[0073] Based on the above schematic description of the polishing equipment, since the voids 64 on the upper fixed plate 61 are uniformly distributed, the polishing slurry should also be uniformly distributed on the wafer surface. However, during the polishing process, the direction of motion of the polishing particles in the polishing slurry is determined by the direction of the resultant velocity of the centrifugal velocity v1 and the linear velocity v2 of the relative rotation of the upper and lower fixed plates, such as... Figure 7 As shown, starting from the moment the disk begins to rotate, in the first stage, when the disk rotation time is less than the set critical time 1 / w, v2 is less than v1. At this time, the resultant velocity direction (i.e., the direction of motion of the polishing particles) is biased towards the linear velocity v2 direction. Then, in the second stage, when the disk rotation time is greater than the critical time, the resultant velocity direction (i.e., the direction of motion of the polishing particles) is biased towards the centrifugal velocity v1 direction. Therefore, after polishing begins, the polishing particles near the wafer center have sufficient time to complete the change in the resultant velocity direction in the above two stages. However, the polishing particles closer to the wafer edge only experience the resultant velocity direction in the first stage before being thrown out of the wafer by centrifugal force. Therefore, the motion direction of the polishing particles at the wafer edge will be along the tangent direction at their edge position.

[0074] When the movement direction of the polishing particles is not consistent with the direction of the crack filled with filler (i.e., linear defects), the crack filled with filler (i.e., linear defects) will be polished away. Therefore, the closer to the center of the wafer, the fewer linear defects there are. Figure 8 The morphology of the discontinuous linear defects shown verifies this characteristic. Figure 8 In the process, the straight-line defect is interrupted into multiple defects because the movement direction of the polishing particles is not parallel to the direction of the straight-line defect. As a result, the polishing particles eliminate the defect by grinding laterally. However, since the polishing particles are not distributed in a high density and there are gaps between the particles, the straight-line defect is not completely eliminated by grinding, resulting in a discontinuous morphology.

[0075] When the movement direction of the polishing particles is consistent with the direction of the crack with filling material, the straight-line defects at the gaps between the polishing particles will not be eliminated by polishing. Therefore, the straight-line defects exhibit the phenomenon of being distributed along the tangent of the wafer edge. That is, most of the straight-line defects on the wafer surface that are inconsistent with the movement direction of the polishing particles will be eliminated by polishing. Only the straight-line defects located at the wafer edge and along the tangent direction will not be eliminated by polishing.

[0076] In summary, the consistency between the movement direction of polishing particles at the wafer edge and the direction of linear defects can be identified as another cause of the existence of linear defects.

[0077] Based on the above scheme and its implementation, in some possible implementations, the step of generating a first elimination measure to reduce the number of causal defects and a second elimination measure to indicate the modification of processing parameters in the wafer fabrication process, respectively, for the first cause and the second cause, includes:

[0078] Based on the first cause, the first elimination measure is determined to be to reduce the amount of residual organic matter on the wafer surface to reduce the residual defects;

[0079] Based on the second cause, the second elimination measure is determined to be changing the movement trajectory of the polishing particles at the edge of the wafer.

[0080] Regarding the above example, it should be noted that after understanding the cause of the linear defect through the above solution, measures to eliminate the linear defect can be determined based on the cause. For the first elimination measure targeting the first cause, in order to reduce the amount of residual organic matter on the wafer surface, the waiting time between the completion of the polishing process (the final machining process of the wafer) and the cleaning process can be reduced. This reduces the amount of residual organic matter on the wafer surface and also prevents the organic matter from having sufficient time to fill the cracks.

[0081] As a second elimination measure for the second cause, optionally, the movement trajectory of the polishing particles can be altered by designing their shape to disrupt the uniformity of their directional distribution, thereby uniformly polishing and eliminating linear defects in all directions on the wafer surface. In some examples, polishing particles with inconsistent end-face areas can be used to polish the wafer surface during the wafer polishing process to change the movement trajectory of the polishing particles at the wafer edge. For example... Figure 9 The black, truncated spherical polishing particles shown have different end faces at both ends. One end, with a larger contact surface, generates greater friction, causing the polishing particle to rotate and thus changing its direction of movement, consequently altering the movement direction of the polishing particles at the wafer edge. Furthermore, the end with the larger contact surface randomly contacts the upper or lower mounting plate, resulting in a large number of polishing particles moving in opposite directions simultaneously. This disrupts the movement direction of the polishing particles, leading to a more uniform polishing effect that eliminates defects. Other examples include conical and frustum-shaped polishing particles, which also exhibit inconsistent end face areas; these will not be further elaborated in this embodiment.

[0082] In some examples, the area of ​​the larger end face represents the magnitude of the frictional force achievable by the polishing particles, which determines their rotational speed and thus produces different removal effects for straight-line defects. In practical implementation, polishing particles with different end face areas can be designed, and through proportioning design, even better removal effects for straight-line defects can be obtained.

[0083] Based on the same inventive concept as the aforementioned technical solution, see [link to inventive concept]. Figure 10 This illustration shows an apparatus 100 for eliminating wafer surface defects according to an embodiment of the present invention, which may include: a first acquisition section 1001, a determination section 1002, a second acquisition section 1003, and a measure generation section 1004, wherein...

[0084] The first acquisition part 1001 is configured to: acquire associated defect types that are quantitatively correlated with linear defects;

[0085] The determining portion 1002 is configured to determine the causal defect of the linear defect from the associated defect types; wherein the causal defect is a first cause of the linear defect.

[0086] The second acquisition section 1003 is configured to acquire a second cause of the linear defect during the wafer fabrication process;

[0087] The measure generation section 1004 is configured to generate a first elimination measure for reducing the number of causal defects and a second elimination measure for instructing modification of processing parameters during wafer fabrication, based on the first and second causes of occurrence; wherein the first and second elimination measures can reduce the number of linear defects on the wafer surface.

[0088] In some examples, in the defect type pair, the number of linear defects is positively correlated with the number of causal defects.

[0089] In some examples, in the defect type pair, the causative defect is a residual defect.

[0090] In some examples, the determining portion 1002 is configured as follows:

[0091] During wafer polishing, the residual defect is identified as the causative defect of the linear defect based on the chemical and physical reaction between the filler material present in the microcracks at local locations on the wafer surface and the high temperature generated during polishing, which forms a linear defect.

[0092] In some examples, the second acquisition section 1003 is configured as follows:

[0093] In the wafer polishing process, the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect is determined as the second cause.

[0094] In some examples, the measure generation section 1004 is configured as follows:

[0095] Based on the first cause, the first elimination measure is determined to be to reduce the amount of residual organic matter on the wafer surface to reduce the residual defects;

[0096] Based on the second cause, the second elimination measure is determined to be changing the movement trajectory of the polishing particles at the edge of the wafer.

[0097] In some examples, the second elimination measure includes:

[0098] In the wafer polishing process, polishing particles with inconsistent end-face areas are used to polish the wafer surface in order to change the movement trajectory of the polishing particles at the edge of the wafer.

[0099] Please refer to Figure 11 This diagram illustrates a structural block diagram of a computing device provided in an exemplary embodiment of this application. The computing device in this application may include one or more components such as a processor 1110 and a memory 1120.

[0100] Optionally, the processor 1110 connects various parts within the computing device using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1120, and by calling data stored in the memory 1120. Optionally, the processor 1110 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1110 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display on the touch screen; the NPU implements artificial intelligence (AI) functions; and the baseband chip handles wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1110, but may be implemented using a separate chip.

[0101] The memory 1120 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1120 may include a non-transitory computer-readable storage medium. The memory 1120 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1120 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the foregoing method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0102] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0103] This application also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the method for eliminating wafer surface defects as described in the above embodiments.

[0104] This application also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform a method for eliminating wafer surface defects provided in various alternative implementations of the above aspects.

[0105] Those skilled in the art will recognize that the functions described in the embodiments of this application in one or more of the above examples can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0106] Based on the methods for eliminating wafer surface defects described above, see [link to relevant documentation]. Figure 12 This illustrates a wafer manufacturing method provided by an embodiment of the present invention, which may include:

[0107] S1210: According to the method for eliminating wafer surface defects as described in any of the foregoing embodiments, a first elimination measure and a second elimination measure for eliminating linear defects are determined;

[0108] S1220: During wafer processing, the first elimination measure and the second elimination measure are used to eliminate straight-line defects on the wafer surface.

[0109] It should be noted that the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0110] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for eliminating defects on a wafer surface, characterized in that, The method includes: Obtain the associated defect types that are quantitatively correlated with linear defects; The causal defect of the linear defect is determined from the associated defect types; wherein the causal defect is a residual defect, and the causal defect is the first cause of the linear defect. To determine the second cause of the linear defect during wafer fabrication; For the first and second causes of defects, a first elimination measure to reduce the number of defects and a second elimination measure to indicate the modification of processing parameters in the wafer fabrication process are generated, respectively; wherein the first and second elimination measures can reduce the number of linear defects on the wafer surface; The step of determining the causal defect of the linear defect from the associated defect types includes: during the wafer polishing process, determining the residual defect as the causal defect of the linear defect based on the chemical and physical reaction between the filler present in the microcracks at local locations on the wafer surface and the microcracks formed by the high temperature generated during polishing. The method of obtaining the second cause of the linear defect in the wafer processing includes: during the wafer polishing process, determining the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect as the second cause.

2. The method according to claim 1, characterized in that, The number of linear defects is positively correlated with the number of causal defects.

3. The method according to claim 1, characterized in that, The method of generating a first elimination measure to reduce the number of causal defects and a second elimination measure to indicate the modification of processing parameters in the wafer fabrication process, respectively, for the first and second causes of occurrence, includes: Based on the first cause, the first elimination measure is determined to be to reduce the amount of residual organic matter on the wafer surface to reduce the residual defects; Based on the second cause, the second elimination measure is determined to be changing the movement trajectory of the polishing particles at the edge of the wafer.

4. The method according to claim 3, characterized in that, The second elimination measure includes: In the wafer polishing process, polishing particles with inconsistent end-face areas are used to polish the wafer surface in order to change the movement trajectory of the polishing particles at the edge of the wafer.

5. An apparatus for eliminating defects on the surface of a wafer, characterized in that, The device includes: a first acquisition section, a determination section, a second acquisition section, and a measure generation section, wherein, The first acquisition part is configured to acquire associated defect types that are quantitatively correlated with linear defects; The determining portion is configured to determine the causal defect of the linear defect from the associated defect types; wherein the causal defect is a residual defect, and the causal defect is a first cause of the linear defect; The second acquisition portion is configured to acquire a second cause of the linear defect during the wafer fabrication process; The measure generation section is configured to generate a first elimination measure for reducing the number of causal defects and a second elimination measure for instructing modification of processing parameters during wafer fabrication, respectively, for the first cause and the second cause; wherein the first elimination measure and the second elimination measure can reduce the number of linear defects on the wafer surface; The determination part is configured to, during the wafer polishing process, determine the residual defect as the cause defect of the linear defect based on the chemical and physical reaction between the filler present in the micro-cracks at local locations on the wafer surface and the micro-cracks formed by the high temperature generated during polishing. The second acquisition part is configured to determine the consistency between the movement direction of the polishing particles at the wafer edge and the direction of the linear defect during the wafer polishing process as the second cause of occurrence.

6. A computing device, characterized in that, The computing device includes a processor and a memory; the processor is configured to execute instructions stored in the memory to implement the method for eliminating wafer surface defects as described in any one of claims 1 to 4.

7. A computer storage medium, characterized in that, The storage medium stores at least one instruction, which is executed by a processor to implement the method for eliminating wafer surface defects as described in any one of claims 1 to 4.

8. A wafer manufacturing method, characterized in that, The method includes: The method for eliminating wafer surface defects according to any one of claims 1 to 4, wherein a first elimination measure and a second elimination measure are determined for eliminating linear defects; During wafer fabrication, the first elimination measure and the second elimination measure are used to eliminate linear defects on the wafer surface.

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