An isolation method for a tunneling field effect transistor device

Abstract

The application provides an isolation method of a tunneling field effect transistor device, and belongs to the technical field of micro-nano electronics. Three isolation structures are added on the basis of the TFET device. In the leakage current path between the source-drain regions of different tunneling field effect transistors of the same doping type, whether between the source-drain region and the second isolation structure or between the second isolation structure and the third isolation structure, there is no positive bias PN junction, and all are reverse bias or zero bias PN junctions. In combination with the first isolation structure, the inhibition effect of the leakage current between different tunneling field effect transistors can be realized. The application can effectively isolate the leakage between TFET devices without increasing the layout area, so that the TFET circuit can work normally while the low-power consumption advantage of the TFET is exerted.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to an isolation method for a tunneling field-effect transistor device. Background Technology

[0002] With the continuous advancement of semiconductor technology, device sizes are shrinking, circuit performance is improving, and chip power density is increasing dramatically. Low power consumption has become an important design direction. At the device level, reducing the power supply voltage can effectively reduce circuit power consumption. However, to maintain sufficient drive capability, the threshold voltage of MOSFET devices must also decrease, leading to an increase in off-state current and static power consumption. Tunneling field-effect transistors (TFETs) employ a band-to-band tunneling current mechanism, effectively cutting off carriers at the tail of the high-energy band. This results in an ultra-steep subthreshold slope of less than 60mV / dec, providing a high current on / off ratio and enabling low-voltage operation. TFETs are considered a promising ultra-steep device to replace MOSFETs.

[0003] Based on Sentaurus TCAD and HSPICE simulations, tunneling field-effect transistors (TFTSs) have been shown to have significantly better power-delay product (PDP) than MOSFETs under certain low-voltage, low-frequency operating conditions, indicating promising applications. However, in large-scale integrated circuit applications, the lightly doped substrate and asymmetric source-drain doping characteristics of TFTSs lead to higher leakage currents between individual TFTSs and between TFTSs and the CMOS device substrate compared to the TFTS's own off-state current. This results in increased static power consumption and may even cause circuit malfunction.

[0004] Therefore, how to effectively cut off leakage current between TFET devices and between TFET and CMOS, and ensure the static power consumption advantage of TFET devices and better apply them in circuits, has become an urgent problem to be solved. It is necessary to propose isolation methods between TFET devices based on the characteristics of TFET itself. Summary of the Invention

[0005] The purpose of this invention is to propose an isolation method for tunneling field-effect transistor (TFTS) devices to suppress leakage current between TFTS and other parts of the circuit, such as other TFTS or CMOS devices, while ensuring the advantage of low off-state current of TFTS.

[0006] The technical solution of this invention is as follows:

[0007] An isolation method for a tunneling field-effect transistor device includes the following steps:

[0008] Step 1: Select wafers corresponding to high-resistivity silicon for device and circuit fabrication;

[0009] Step 2: Form shallow trench isolation (STI) as isolation structure one. The region between the isolation structures is defined as the active region, which is used to form tunneling field-effect transistors and CMOS devices.

[0010] Step 3: Deposit an oxide layer on the substrate in an anisotropic manner to form the masking layer required for subsequent ion implantation processes;

[0011] Step 4: Define the CMOS device region using photolithography;

[0012] Step 5: Form a CMOS device substrate by ion implantation, wherein the semiconductor substrate is either doped with the first type or the second type.

[0013] Step 6: After removing the photoresist and the oxide layer formed in step 3, repeat step 3;

[0014] Step 7: Define the tunneling field-effect transistor device region using photolithography;

[0015] Step 8: Isolation structure 2 and isolation structure 3 are formed inside the active region of the tunneling field-effect transistor by ion implantation. Isolation structure 2 is a semiconductor material with the first doping type. Isolation structure 3 is formed inside the active region of the tunneling field-effect transistor and at the bottom of isolation structure 1. This isolation structure is a semiconductor material with the second doping type. The second doping type is opposite to the first doping type. There are N-type doping and P-type doping in the adjacent regions of isolation structure 2 and isolation structure 3 to compensate for each other. The position where the doping concentration is 0 is the boundary line between isolation structure 2 and isolation structure 3. This boundary line can be located at the bottom of isolation structure 1 or above or below the bottom, or at the same depth as the bottom of isolation structure 1.

[0016] Step 9: The oxide layer is etched anisotropically across the entire wafer, followed by gate stacking and heavy doping region implantation, to complete the fabrication of the tunneling field-effect transistor (TFTE) device and the CMOS device. The active region of the TFTE forms a first-type doping region and a second-type doping region, which serve as the source and drain regions of the TFTE. The first doping type is the opposite of the second doping type.

[0017] Furthermore, the wafer doping type in step 1 can be boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm.

[0018] In step 2, the thickness of STI should be between 200nm and 1000nm.

[0019] The thickness of the oxide layer deposited in step 3 and the thickness of the oxide layer etched in step 6 are between 1 nm and 2 nm.

[0020] The ion implantation conditions in step 5 are mature CMOS process conditions. The first doping type can be N-type impurity or P-type impurity. The second doping type is the opposite of the first doping type. N-type impurity can be phosphorus (P) or arsenic (As), and P-type impurity can be boron (B) or boron fluoride (BF2).

[0021] Step 6 involves regrowing a new masking layer to ensure the lattice quality of the masking layer and suppress the injection channel effect.

[0022] Combining steps 7 and 4, the fabrication of isolation structure 2 and isolation structure 3 only requires two additional photomasks: one for defining the CMOS device region and the other for defining the tunneling field-effect transistor region.

[0023] In step 8, the specific location requirement for isolation structure two is that it is a certain distance from the surface of the tunneling field-effect transistor (STI) channel, and is located entirely below the source / drain regions of the STI. The space between isolation structure two and the source / drain regions is a lightly doped semiconductor substrate. To form isolation structures two and three in step 8, the N-type impurity can be phosphorus (P) or arsenic (As), and the P-type impurity can be boron (B) or boron fluoride (BF2). The ion implantation conditions need to be adjusted so that only the isolation well corresponding to isolation structure three exists at the bottom of the STI. Simultaneously, the boundary between isolation structures two and three must be located at the bottom and above the STI boundary. The ion implantation conditions also need to ensure that the peak concentration of the isolation wells corresponding to isolation structures two and three is greater than 5E16cm⁻¹. -2 The surface concentration in the channel is less than 1E16cm. -2 The impurity distribution peak position corresponding to isolation structure two is located above 200 nm from the channel surface to the bottom of the STI. Furthermore, the STI acts as both isolation structure one and a hard mask for ion implantation. Because the STI suppresses the ion implantation channel effect, it can increase the peak concentration, decrease the bandgap concentration, and reduce the peak position depth. This results in isolation structure three forming a highly doped isolation well below the bottom of the STI. At the same depth, in regions far from the STI, the doping concentration of the isolation well decreases. The boundary between isolation structure two and isolation structure three shifts towards the depth of the substrate. In the region between shallow trench isolations, the boundary between isolation structure two and isolation structure three is located at the bottom of isolation structure one, or above or below the bottom, or at the same depth as the bottom of isolation structure one.

[0024] Step 9 describes the fabrication process for TFET and CMOS devices, including an annealing step for source / drain activation, which can simultaneously activate the second and third isolation structures.

[0025] In the isolation method proposed in this invention, the upper part of isolation structure two is a lightly doped semiconductor substrate, thus preventing deterioration of the off-state current of the tunneling field-effect transistor (TFPT). Furthermore, since the semiconductor substrate between isolation structure two and the source / drain regions is lightly doped, it is easily depleted. Therefore, the source / drain regions of TFPTs with the same doping type as isolation structure two will act as the lead-out electrodes of isolation structure two. Isolation structure three is located at the bottom of the TFPT and the bottom of isolation structure one, thus the bottoms of different TFPTs of isolation structure three are interconnected. Furthermore, isolation structure three is connected to the CMOS device substrate with the same doping type. Therefore, the voltage bias of other parts in the integrated circuit, such as other TFPTs and the CMOS device substrate, will affect the voltage of isolation structure three. Since in conventional circuit design, the voltage of the N-type doped region is always greater than or equal to the voltage of the P-type doped region, i.e., the first doping type region and the second doping type region can form a reverse-biased or zero-biased PN junction. Therefore, in the leakage paths between the source and drain regions of different tunneling field-effect transistors with the same doping type, whether between the source / drain region and isolation structure two, or between isolation structure two and isolation structure three, there is definitely no forward-biased PN junction; all are reverse-biased or zero-biased PN junctions. Further combining this with isolation structure one can suppress leakage current between different tunneling field-effect transistors. Similarly, in the leakage paths between the source / drain regions of a tunneling field-effect transistor and the CMOS device substrate with the same doping type, whether between the source / drain region and isolation structure two, between isolation structure two and isolation structure three, or between isolation structure three and the CMOS device substrate, there is definitely no forward-biased PN junction; all are reverse-biased or zero-biased PN junctions. Further combining this with isolation structure one can suppress leakage current between different tunneling field-effect transistors.

[0026] The isolation method proposed in this invention includes voltage bias in integrated circuit design, structural regions formed in integrated circuit manufacturing, and the relative positions and voltage relationships between structural regions. As a whole, it achieves the technical effect of suppressing leakage current between tunneling field-effect transistors and other parts of the circuit, such as other tunneling field-effect transistors or CMOS devices, while ensuring the advantage of low off-state current of tunneling field-effect transistors.

[0027] The isolation method for tunneling field-effect transistor (TFET) devices proposed in this invention does not have additional requirements for device spacing; the device spacing only needs to meet the STI design rules. Therefore, using the isolation scheme of this invention, leakage current between the TFET and other parts of the circuit, such as other TFETs or CMOS devices, can be effectively suppressed without increasing the layout area, allowing the TFET circuit to operate normally while leveraging its low power consumption advantage.

[0028] This invention utilizes existing mature process steps in bulk silicon CMOS without introducing new materials, resulting in a simple process. Furthermore, by leveraging the STI structure as a hard mask and its suppression of ion implantation channel effects, ion implantation of isolation structures two and three can be achieved with a single photomask, eliminating the need to design two photomasks for the relative positions of the two isolation structures, thus reducing process complexity and cost. The low static power consumption and simple, effective isolation method make tunneling field-effect transistors truly capable of large-scale application and mass production. Attached Figure Description

[0029] Figure 1 This is a cross-sectional schematic diagram of adjacent tunneling field-effect transistors and CMOS devices using the isolation method of the present invention;

[0030] Figure 2 This is a schematic diagram of the hybrid integration process steps of tunneling field-effect transistors and CMOS devices using the present invention, wherein: (a) is a diagram after the formation of isolation structure one; (b) is a diagram after the deposition of oxide layer; (c) is a diagram after the nMOS P-well implantation; (d) is a diagram after the pMOS N-well implantation; (e) is a diagram after the TFET device region is defined; (f) is a diagram after the second isolation structure implantation; (g) is a diagram after the third isolation structure implantation; and (h) is a diagram after the device fabrication is completed.

[0031] In the picture:

[0032] 1—Gate conductive layer; 2—Gate dielectric layer

[0033] 3 – P-type heavily doped region; 4 – N-type heavily doped region

[0034] 5 – Isolation structure – 6 – Lightly doped substrate

[0035] 7 - Isolation Structure Three 8 - Isolation Structure Two

[0036] 9 – P-type substrate of nMOSFET; 10 – N-type substrate of pMOSFET

[0037] 11 – Oxide layer 12 – Photoresist Detailed Implementation

[0038] The present invention will be further illustrated below with examples. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection claimed by the present invention shall be determined by the scope defined in the claims.

[0039] The following is an example. Figure 1 This is a cross-sectional view of adjacent tunneling field-effect transistors and CMOS devices using the proposed isolation method. It consists of a pMOSFET on the left, an nTFET in the middle, and an nMOSFET on the right, all fabricated on a lightly doped substrate 6. The lightly doped substrate can be either P-type or N-type lightly doped. The devices are separated by isolation structures 5, 8, and 7, with the doping types of isolation structures 2 and 3 being opposite.

[0040] As shown in Figure 2, the specific steps of the present invention are as follows:

[0041] First, a boron-doped P-type high-resistivity silicon wafer was selected for device and circuit fabrication with a resistivity of 9 Ohm-cm.

[0042] Secondly, shallow trench isolation (STI) is performed to form isolation structure one. The specific method is to anisotropically etch silicon outside the active region; then anisotropically deposit an oxide layer outside the active region; as shown in Figure (a), the STI is 300nm;

[0043] Next, as shown in Figure (b), a 2 nm oxide layer 11 is deposited on the substrate in an anisotropic manner;

[0044] Next, as shown in Figure (c), the nMOSFET region was defined by photolithography, and boron was implanted to form the P-well of the nMOSFET by ion implantation. A total of three ion implantations were performed, with conditions of 90 keV 1E 13 cm⁻¹. -3 200keV5E13cm -3 10keV1E13cm -3 After ion implantation, the adhesive is removed;

[0045] Next, as shown in Figure (d), the pMOSFET region was defined by photolithography, and phosphorus was implanted to form the N-well of the pMOSFET by ion implantation. A total of three ion implantations were performed, with conditions of 30keV, 5E, and 12cm. -3 220keV5E12cm -3 380keV5E13cm -3 After ion implantation, the adhesive is removed;

[0046] Next, the oxide layer is etched anisotropically across the entire wafer, and then a 2nm oxide layer 11 is redeposited anisotropically on the substrate.

[0047] Next, as shown in Figure (e), the TFET device region is defined by photolithography.

[0048] Next, as shown in Figure (f), phosphorus was implanted to form the second isolation structure by ion implantation at an energy of 180 keV and an implantation dose of 1e13 cm-3.

[0049] Next, as shown in Figure (g), boron was implanted to form the isolation structure III by ion implantation at an energy of 140 keV and an implantation dose of 1e13cm-3.

[0050] The specific location requirements for isolation structure two are that it is a certain distance from the surface of the tunneling field-effect transistor (STI) channel, and is situated entirely below the source / drain regions of the STI. The space between isolation structure two and the source / drain regions is a lightly doped semiconductor substrate. To form isolation structures two and three in step 8, the N-type impurity can be phosphorus (P) or arsenic (As), and the P-type impurity can be boron (B) or boron fluoride (BF2). Ion implantation conditions need to be adjusted so that only the isolation well corresponding to isolation structure three exists at the bottom of the STI, and that the boundary between isolation structures two and three is located at or above the bottom of the STI. The ion implantation conditions also need to ensure that the peak concentration of the isolation wells corresponding to isolation structures two and three is greater than 5E16cm⁻¹. -2 The surface concentration in the channel is less than 1E16cm. -2 The impurity distribution peak position corresponding to isolation structure two is located above 200 nm from the channel surface to the bottom of STI. Furthermore, STI acts as both isolation structure one and a hard mask for ion implantation. Because STI suppresses the ion implantation channel effect, it can increase peak concentration, decrease band tail concentration, and reduce peak position depth. This results in isolation structure three forming a highly doped isolation well below the bottom of STI. At the same depth, in regions far from STI, the doping concentration of the isolation well decreases. The position where the doping concentration is 0 is the boundary between isolation structure two and isolation structure three. This boundary shifts towards the depth of the substrate. In the shallow trench isolation boundary region, the boundary between isolation structure two and isolation structure three is located at or above the bottom of the shallow trench isolation. In the region between shallow trench isolations, the boundary between isolation structure two and isolation structure three is located at the bottom of isolation structure one, or above or below the bottom, or at the same depth as the bottom of isolation structure one.

[0051] Next, as shown in Figure (h), the oxide layer is etched anisotropically across the entire wafer, and subsequent steps such as gate stacking and heavy doping region implantation are performed to complete the fabrication of tunneling field-effect transistor devices and CMOS devices. The active region of the tunneling field-effect transistor forms a first doping type region and a second doping type region, which serve as the source and drain regions of the tunneling field-effect transistor. The impurities in the isolation trap are activated by the thermal budget of the subsequent source and drain activation.

[0052] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. An isolation method for a tunneling field-effect transistor device, comprising the following steps: 1) Select wafers corresponding to high-resistivity silicon for device and circuit fabrication; 2) Shallow trench isolation is formed as isolation structure one. The area between the isolation structures is defined as the active region, which is used to form tunneling field-effect transistors and CMOS devices. 3) An oxide layer is deposited on the substrate in an anisotropic manner to form the masking layer required for subsequent ion implantation processes; 4) Define the CMOS device region using photolithography; 5) The CMOS device substrate is formed by ion implantation, and the semiconductor substrate is either the first type of doping or the second type of doping. 6) After removing the photoresist and the oxide layer formed in step 3), repeat step 3). 7) Define the device region of the tunneling field-effect transistor using photolithography; 8) Isolation structure 2 and isolation structure 3 are formed inside the active region of the tunneling field-effect transistor by ion implantation. Isolation structure 2 is a semiconductor material of the first doping type. Isolation structure 3 is formed inside the active region of the tunneling field-effect transistor and at the bottom of isolation structure 1. Isolation structure 3 is a semiconductor material of the second doping type. The second doping type is opposite to the first doping type. There are N-type doping and P-type doping in the adjacent regions of isolation structure 2 and isolation structure 3 to compensate for each other. The position where the doping concentration is 0 is the boundary line between isolation structure 2 and isolation structure 3. 9) The oxide layer is etched anisotropically across the entire wafer to perform gate stacking and subsequent heavy doping region implantation steps, thereby completing the fabrication of tunneling field-effect transistor devices and CMOS devices. The active region of the tunneling field-effect transistor forms a first-type doping region and a second-type doping region, which serve as the source and drain regions of the tunneling field-effect transistor.

2. The isolation method for the tunneling field-effect transistor device as described in claim 1, characterized in that, In the shallow trench isolation boundary area, the dividing line between isolation structure two and isolation structure three is located at the bottom and above of the shallow trench isolation. In the area between the shallow trench isolations, the dividing line between isolation structure two and isolation structure three is located at the bottom of isolation structure one or above or below the bottom, or at the same depth as the bottom of isolation structure one.

3. The isolation method for the tunneling field-effect transistor device as described in claim 2, characterized in that, The second isolation structure is located at a certain distance from the surface of the tunneling field-effect transistor channel and is situated below the source and drain regions of the tunneling field-effect transistor. The space between the second isolation structure and the source and drain regions is a lightly doped semiconductor substrate.

4. The isolation method for the tunneling field-effect transistor device as described in claim 1, characterized in that, The wafer in step 1) is doped with boron or phosphorus, and the resistivity of the wafer should be greater than 8 Ohm-cm.

5. The isolation method for a tunneling field-effect transistor device as described in claim 1, characterized in that, In step 2), the thickness of the shallow trench isolation is between 200nm and 1000nm.

6. The isolation method for a tunneling field-effect transistor device as described in claim 1, characterized in that, The thickness of the oxide layer deposited in step 3) ranges from 1 nm to 2 nm.

7. The isolation method for a tunneling field-effect transistor device as described in claim 1, characterized in that, The ion implantation described in step 5) uses mature CMOS process conditions. The first doping type is N-type impurity or P-type impurity. The second doping type is the opposite of the first doping type. The N-type impurity is phosphorus or arsenic, and the P-type impurity is boron or boron fluoride.

8. The isolation method for a tunneling field-effect transistor device as described in claim 1, characterized in that, In step 8), the peak concentrations of the isolation traps corresponding to isolation structures two and three are both greater than 5E16cm⁻¹. -2 The peak position of the impurity distribution corresponding to the second isolation structure is located at a distance of more than 200nm from the channel surface to the bottom of the shallow trench isolation.

9. The isolation method for a tunneling field-effect transistor device as described in claim 1, characterized in that, In step 9), impurity activation is performed on both isolation structure 2 and isolation structure 3.

Images