Semiconductor structure and method of manufacturing a semiconductor structure
By introducing a multi-layer stacked 3D framework and support structure into the semiconductor structure, the problem of difficulty in increasing the storage density of dynamic random access memory due to size reduction is solved, and the storage density and electrical performance are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-04-24
- Publication Date
- 2026-06-19
AI Technical Summary
Dynamic random access memory (DRAM) suffers from problems such as limited storage density due to size reduction and low yield.
Introducing a multi-layered stacked 3D architecture into semiconductor structures, by setting stacked capacitors in the vertical direction and setting support structures between adjacent memory cells, can increase storage density and stability.
It improves the storage density and electrical performance of semiconductor structures, overcomes the problem of difficulty in increasing storage density due to size reduction, and provides a new direction for the development of dynamic random access memory.
Smart Images
Figure CN116978889B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for fabricating the semiconductor structure. Background Technology
[0002] In the field of integrated circuits, according to Moore's Law, the performance of an integrated circuit doubles for every doubling of the number of semiconductor devices. Therefore, in order to improve the electrical performance of integrated circuits, the size of integrated circuits is constantly shrinking and the integration density is constantly increasing.
[0003] Currently, Dynamic Random Access Memory (DRAM) is typically a single-layer structure. The size of single-layer DRAM has been reduced to its limit, making it difficult to continue shrinking to maintain the effectiveness of Moore's Law. Furthermore, the continuous shrinking of DRAM feature sizes increases the manufacturing process difficulty; the smaller the feature size, the lower the yield of DRAM. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.
[0005] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure.
[0006] A first aspect of this disclosure provides a semiconductor structure, the semiconductor structure including a substrate and at least one memory cell disposed on the substrate, each memory cell comprising:
[0007] Multiple active strips are arranged in an array above the substrate. Each active strip extends along a first direction. On a plane parallel to the substrate, any two adjacent active strips are separated by a first trench. On a plane perpendicular to the substrate, any two adjacent active strips are separated by a second trench.
[0008] At least one set of stacked capacitors, with two adjacent sets of stacked capacitors spaced apart, each set of stacked capacitors including a lower electrode, a dielectric layer covering the sidewalls of the lower electrode, and an upper electrode, the lower electrode including a portion of the structure passing through each of the active strips of the stacked capacitor, the upper electrode covering the dielectric layer and filling the first trench and the second trench located between the lower electrodes.
[0009] According to some embodiments of this disclosure, the semiconductor structure includes a plurality of memory cells, which are arranged cyclically on the substrate along the first direction.
[0010] According to some embodiments of this disclosure, the semiconductor structure further includes:
[0011] A support structure is disposed on the substrate and between adjacent memory cells, and the support structure connects two stacked capacitors of adjacent memory cells.
[0012] According to some embodiments of this disclosure, the material of the support structure includes an insulating material.
[0013] According to some embodiments of this disclosure, the stacked capacitor further includes:
[0014] Multiple recesses are provided at one end of the stacked capacitor near the support structure, each recess is provided between two adjacent active bars, and each recess is oriented toward the support structure.
[0015] According to some embodiments of this disclosure, the support structure further includes:
[0016] The protrusions are disposed on the sidewall of the support structure, and each protrusion is disposed corresponding to a recess, with each protrusion embedded in the recess.
[0017] According to some embodiments of this disclosure, each of the memory cells further includes:
[0018] An array region is disposed between two adjacent sets of stacked capacitors, and the array region is connected to the stacked capacitors through a plurality of active strips.
[0019] According to some embodiments of this disclosure, the array region includes:
[0020] Multiple word lines are arranged vertically on the substrate. Any two adjacent word lines are spaced apart on a plane parallel to the substrate. Each word line intersects with a portion of the active bars among the multiple active bars, and each word line covers a portion of the sidewall of a portion of the active bars.
[0021] Multiple bit lines, each bit line extending along a second direction, the second direction being located in a plane parallel to the substrate and perpendicular to the first direction, any two adjacent bit lines are spaced apart on the plane perpendicular to the substrate, each bit line intersects with a portion of the active strips of the plurality of active strips, and each bit line covers a portion of the sidewall of a portion of the active strips;
[0022] The multiple word lines and the multiple bit lines are separated by an isolation structure.
[0023] According to some embodiments of this disclosure, in the first direction, each of the memory cells includes two sets of stacked capacitors symmetrically disposed on both sides of the array region.
[0024] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:
[0025] A first structure is provided, the first structure including a capacitor region, the first structure including a substrate and a plurality of active strips, the plurality of active strips being arranged in an array above the substrate, each active strip extending along a first direction, in the capacitor region, on a plane parallel to the substrate, any two adjacent active strips are separated by a first trench, and on a plane perpendicular to the substrate, any two adjacent active strips are separated by a second trench, the second trench communicating with the first trench and exposing the sidewalls of the active strips located in the capacitor region;
[0026] A dielectric layer is formed in the capacitor region, and the dielectric layer covers the exposed sidewall of the active strip;
[0027] An upper electrode is formed in the capacitor region, the upper electrode covering the dielectric layer and filling the first trench and the second trench located in the capacitor region;
[0028] Using the portion of the active strip located in the capacitor region as the lower electrode, the upper electrode, the dielectric layer, and the lower electrode form a stacked capacitor vertically stacked on the substrate.
[0029] According to some embodiments of this disclosure, a first structure is provided, comprising:
[0030] A substrate is provided, on which a stacked structure is formed, the stacked structure comprising an active layer and a sacrificial layer stacked alternately in sequence;
[0031] Multiple first trenches are formed in the stacked structure, each first trench extends along the first direction, and in a direction perpendicular to the substrate, each first trench penetrates the stacked structure, and the retained active layer is divided into multiple active strips by the first trenches.
[0032] A portion of the sacrificial layer is removed to form a second trench in the capacitor region. The first trench and the second trench are connected, exposing the sidewall of the active strip located in the capacitor region.
[0033] According to some embodiments of this disclosure, the first structure further includes a first region, the capacitor region being located in the first region, and the manufacturing method further includes:
[0034] A support structure is formed in the first region, the support structure extends along a second direction and penetrates the first structure, the second direction is located in a plane parallel to the substrate and is perpendicular to the first direction, the support structure divides the first region into two independently set capacitor regions.
[0035] According to some embodiments of this disclosure, a support structure is formed, including:
[0036] The first region is etched to form a trench in the first region, the trench extending along the second direction and penetrating the first structure, and the trench exposing a portion of the substrate;
[0037] The trench is filled with deposited insulating material to form the support structure.
[0038] According to some embodiments of this disclosure, when etching the first region, the etching rate of the sacrificial layer is greater than the etching rate of the active strip, and a plurality of recesses are formed on the trench wall of the channel, each of the recesses being laterally recessed between two adjacent active strips;
[0039] A portion of the insulating material is filled into the recess, forming multiple protrusions on the sidewall of the support structure.
[0040] According to some embodiments of this disclosure, the first structure further includes an array region, and providing the first structure further includes:
[0041] Remove the sacrificial layer located in the array region;
[0042] Multiple word lines are formed in the array area. Each word line is vertically disposed on the substrate. Any two adjacent word lines are spaced apart on a plane parallel to the substrate. Each word line intersects with a portion of the active bars among the multiple active bars, and each word line covers a portion of the sidewall of a portion of the active bars.
[0043] Multiple bit lines are formed in the array region. Each bit line extends along a second direction, which is located in a plane parallel to the substrate and is perpendicular to the first direction. Any two adjacent bit lines are spaced apart on the plane perpendicular to the substrate. Each bit line intersects with a portion of the active strips in the plurality of active strips, and each bit line covers a portion of the sidewall of a portion of the active strip.
[0044] According to some embodiments of this disclosure, the provision of the first structure further includes:
[0045] An isolation structure is formed in the array region, and the isolation structure fills the gaps between the multiple word lines and the multiple bit lines.
[0046] In the semiconductor structure and semiconductor structure fabrication method provided in the embodiments of this disclosure, by adding stacked capacitors stacked in the vertical direction, the semiconductor structure has a multi-layer stacked 3D architecture, thereby increasing the storage density of the semiconductor structure. Furthermore, the stacked capacitors have an increaseable number of stacked layers, so the semiconductor structure provided in this disclosure has an continuously increasing storage density, which greatly improves the electrical performance of the semiconductor structure.
[0047] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.
[0049] Figure 1 This is a side view of a semiconductor structure according to an exemplary embodiment.
[0050] Figure 2 This is illustrated according to an exemplary embodiment. Figure 1 Top view of area A in the middle.
[0051] Figure 3 yes Figure 2 A cross-sectional view of surface aa.
[0052] Figure 4 yes Figure 2 A cross-sectional view of the bb surface.
[0053] Figure 5 yes Figure 2 A cross-sectional view of the cc plane.
[0054] Figure 6 yes Figure 2 A cross-sectional view of the dd surface.
[0055] Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.
[0056] Figure 8 This is a top view of a stacked structure formed according to an exemplary embodiment.
[0057] Figure 9 yes Figure 8Cross-sectional views of aa, bb, cc, and dd.
[0058] Figure 10 This is a top view illustrating the formation of the first trench according to an exemplary embodiment.
[0059] Figure 11 yes Figure 10 Cross-sectional views of aa, bb, cc, and dd.
[0060] Figure 12 This is a top view illustrating the formation of a third trench according to an exemplary embodiment.
[0061] Figure 13 yes Figure 12 Cross-sectional views of aa, bb, and dd.
[0062] Figure 14 This is a top view illustrating the formation of the initial gate oxide layer according to an exemplary embodiment.
[0063] Figure 15 yes Figure 14 Cross-sectional views of aa, bb, and dd.
[0064] Figure 16 This is a top view illustrating the formation of an initial high-k dielectric layer according to an exemplary embodiment.
[0065] Figure 17 yes Figure 16 Cross-sectional views of aa, bb, and dd.
[0066] Figure 18 This is a top view illustrating the formation of character lines according to an exemplary embodiment.
[0067] Figure 19 yes Figure 18 Cross-sectional views of aa, bb, and dd.
[0068] Figure 20 This is a top view of a portion of the active strip in the array region, as shown according to an exemplary embodiment.
[0069] Figure 21 yes Figure 20 Cross-sectional views of aa, bb, and dd.
[0070] Figure 22 This is a top view illustrating the formation of a source layer and a drain layer according to an exemplary embodiment.
[0071] Figure 23 yes Figure 22 Cross-sectional views of aa, bb, and dd.
[0072] Figure 24 A top view illustrating the formation of a first isolation layer according to an exemplary embodiment.
[0073] Figure 25 yes Figure 24 Cross-sectional views of aa, bb, and dd.
[0074] Figure 26 A top view illustrating the formation of bitline trenches according to an exemplary embodiment.
[0075] Figure 27 yes Figure 26 Cross-sectional views of aa, bb, and dd.
[0076] Figure 28 A top view of the bit line formation shown according to an exemplary embodiment.
[0077] Figure 29 yes Figure 28 Cross-sectional views of aa, bb, and dd.
[0078] Figure 30 A top view illustrating the formation of an isolation structure according to an exemplary embodiment.
[0079] Figure 31 yes Figure 30 Cross-sectional views of aa, bb, and dd.
[0080] Figure 32 A top view of the first region shown according to an exemplary embodiment.
[0081] Figure 33 yes Figure 32 The cross-sectional view of aa.
[0082] Figure 34 yes Figure 32 bb cross-section diagram.
[0083] Figure 35 yes Figure 32 The cc section diagram.
[0084] Figure 36 A top view of a channel formed in a first region, according to an exemplary embodiment.
[0085] Figure 37 yes Figure 36 The cross-sectional view of aa.
[0086] Figure 38 yes Figure 36 bb cross-section diagram.
[0087] Figure 39 A top view of the formation of a support structure according to an exemplary embodiment.
[0088] Figure 40 yes Figure 39 The cross-sectional view of aa.
[0089] Figure 41 yes Figure 39 bb cross-section diagram.
[0090] Figure 42 A top view of the sacrificial layer with the capacitor region removed, according to an exemplary embodiment.
[0091] Figure 43 yes Figure 42 The cross-sectional view of aa.
[0092] Figure 44 yes Figure 42 bb cross-section diagram.
[0093] Figure 45 yes Figure 42 The cc section diagram.
[0094] Figure 46 A top view illustrating the formation of a dielectric layer according to an exemplary embodiment.
[0095] Figure 47 yes Figure 46 The cross-sectional view of aa.
[0096] Figure 48 yes Figure 46 bb cross-section diagram.
[0097] Figure 49 yes Figure 46 The cc section diagram.
[0098] Figure 50 A top view illustrating the formation of the upper electrode according to an exemplary embodiment.
[0099] Figure 51 yes Figure 50 The cross-sectional view of aa.
[0100] Figure 52 yes Figure 50 bb cross-section diagram.
[0101] Figure 53 yes Figure 50 The cc section diagram.
[0102] Figure label:
[0103] 100. First structure; 101. First region; 1011. Capacitor region; 102. Array region; 110. Substrate; 120. Stacked structure; 121. Sacrificial layer; 122. Active layer; 123. Dielectric layer; 130. Active strip; 140. First trench; 150. Second trench; 160. Third trench; 200. Support structure; 210. Channel trench; 211. Recess; 220. Protrusion; 300. Stacked capacitors 310, Lower electrode; 320, Dielectric layer; 330, Upper electrode; 400, Word line; 401, Initial gate oxide layer; 402, Initial high-k dielectric layer; 410, Gate oxide layer; 420, High-k dielectric layer; 430, Word line layer; 440, Source layer; 450, Drain layer; 500, Bit line; 510, Bit line trench; 600, Isolation structure; 610, First isolation layer; 620, Second isolation layer; 700, Memory cell;
[0104] D1, first direction; D2, second direction. Detailed Implementation
[0105] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.
[0106] This exemplary embodiment provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes stacked capacitors stacked in a vertical direction, which increases the storage density of the semiconductor structure. Furthermore, the stacked capacitors have an increaseable number of stacked layers, so the semiconductor structure has an continuously increasing storage density. This overcomes the problem that dynamic random access memory (DRAM) cannot continue to increase its storage density due to size miniaturization, and provides a new direction for the development of DRAM.
[0107] This disclosure provides an exemplary embodiment of a semiconductor structure. This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example of the semiconductor structure. However, this embodiment is not limited to this. The semiconductor structure in this embodiment can also be other structures.
[0108] like Figures 1-6As shown, the semiconductor structure of this embodiment includes a substrate 110 and at least one memory cell 700 disposed on the substrate 110. Each memory cell 700 includes a plurality of active strips 130, which are arranged in an array above the substrate 110. Each active strip 130 extends along a first direction D1. On a plane parallel to the substrate 110, any two adjacent active strips 130 are separated by a first trench 140 (see reference). Figures 42-45 Separated by a second trench 150, on a plane perpendicular to the substrate 110, any two adjacent active strips 130 are separated by the second trench 150 (refer to...). Figures 42-45 Separate them.
[0109] Each memory cell 700 also includes at least one set of stacked capacitors 300. When multiple stacked capacitors 300 are provided, adjacent sets of stacked capacitors 300 are spaced apart. Each set of stacked capacitors 300 includes a lower electrode 310, a dielectric layer 320 covering the sidewalls of the lower electrode 310, and an upper electrode 330. The lower electrode 310 includes a portion of the structure passing through each active strip 130 of the stacked capacitors 300. The upper electrode 330 covers the dielectric layer 320 and fills the first trench 140 and the second trench 150 located between the lower electrodes 310 (see reference). Figures 42-45 ).
[0110] The semiconductor structure of this embodiment breaks through the inherent single-layer architecture of current dynamic random access memory (DRAM) by adding stacked capacitors arranged in the vertical direction, so that the DRAM has a multi-layer stacked 3D architecture, which increases the storage density of the semiconductor structure. Furthermore, the stacked capacitors 300 have an increaseable number of stacked layers. Therefore, the semiconductor structure of this embodiment has an continuously increasing storage density, which overcomes the problem that the storage density of DRAM is difficult to continue to increase due to the miniaturization of size, and provides a new direction for the development of DRAM.
[0111] In some embodiments, such as Figure 1 As shown, the semiconductor structure includes multiple memory cells 700, which are arranged cyclically on the substrate 110 along the first direction D1, that is, multiple memory cells 700 are repeatedly arranged on the substrate 110.
[0112] In some embodiments, such as Figures 1-6 As shown, the semiconductor structure also includes a support structure 200, which is disposed on the substrate 110 and between two adjacent memory cells 700. The support structure 200 connects two stacked capacitors 300 of the adjacent memory cells 700 to improve the stability of the semiconductor structure and prevent it from tilting or collapsing. The support structure 200 is made of an insulating material.
[0113] In some embodiments, such as Figures 1-6 As shown, refer to Figures 36-41 The stacked capacitor 300 also includes a plurality of recesses 211, which are disposed at one end of the stacked capacitor 300 near the support structure 200. Each recess 211 is disposed between two adjacent active bars 130 and is disposed toward the support structure 200.
[0114] like Figures 1-4 As shown, refer to Figures 36-41 The support structure 200 also includes protrusions 220, which are disposed on the sidewalls of the support structure 200. Each protrusion 220 corresponds to a recess 211, and each protrusion 220 is embedded in the recess 211. The protrusions 220 of the support structure 200 are embedded in the recesses 211 of the stacked capacitor 300, which increases the contact area between the support structure 200 and the stacked capacitor 300, improves the effect of the support structure 200 in supporting the semiconductor structure, and can effectively prevent the semiconductor structure from tilting or collapsing.
[0115] In some embodiments, such as Figure 1 As shown, each memory cell 700 also includes an array region 102, which is disposed between two adjacent sets of stacked capacitors 300. The array region 102 is connected to the stacked capacitors 300 through a plurality of active strips 130.
[0116] In some embodiments, such as Figure 1 As shown, in the first direction D1, each memory cell 700 includes two sets of stacked capacitors 300, which are symmetrically arranged on both sides of the array region 102, further improving the integration of the memory cell 700.
[0117] In some embodiments, such as Figures 1-6 As shown, array region 102 includes multiple word lines 400 and multiple bit lines 500. Each word line 400 is vertically disposed on substrate 110. In a plane parallel to substrate 110, any two adjacent word lines 400 are spaced apart. Each word line 400 intersects with a portion of the multiple active strips 130, and each word line 400 covers a portion of the sidewall of a portion of the active strip 130. Each bit line 500 extends along a second direction D2, which is located in a plane parallel to substrate 110 and perpendicular to a first direction D1. In a plane perpendicular to substrate 110, any two adjacent bit lines 500 are spaced apart. Each bit line 500 intersects with a portion of the multiple active strips 130, and each bit line 500 covers a portion of the sidewall of a portion of the active strip 130. The multiple word lines 400 and the multiple bit lines 500 are separated by an isolation structure 600.
[0118] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 7 As shown, Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 8-53 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 8-53 The methods for fabricating semiconductor structures are introduced.
[0119] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.
[0120] like Figure 7 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising the following steps:
[0121] Step S110: Provide a first structure, the first structure including a capacitor region, the first structure including a substrate and a plurality of active strips, the plurality of active strips being arranged in an array above the substrate, each active strip extending along a first direction, in the capacitor region, on a plane parallel to the substrate, any two adjacent active strips are separated by a first trench, on a plane perpendicular to the substrate, any two adjacent active strips are separated by a second trench, the second trench and the first trench are connected and expose the sidewalls of the active strips located in the capacitor region.
[0122] like Figures 42-45 As shown, the first structure 100 may include one or more capacitor regions 1011. In an embodiment where the first structure 100 includes multiple capacitor regions 1011, the multiple capacitor regions 1011 are independently arranged in a first direction D1. On a plane parallel to the substrate 110, multiple active strips 130 are arranged in multiple rows along a second direction D2. On a plane perpendicular to the substrate 110, multiple active strips 130 are arranged in multiple columns. Any two adjacent active strips 130 are independently arranged. The first trench 140 and the second trench 150 expose the sidewalls of the active strips 130 located in the capacitor regions 1011.
[0123] In this embodiment, as Figures 42-45 As shown, the first structure 100 includes a first region 101 and an array region 102 alternately arranged along a first direction D1. Capacitor regions 1011 are located in the first region 101, and each first region 101 includes two independently arranged capacitor regions 1011. A support structure 200 is formed in the first region 101, and the two capacitor regions 1011 of the first region 101 are separated by the support structure 200.
[0124] During implementation, a first structure 100 is provided, including the following steps:
[0125] Step S111: Provide a substrate and form a stacked structure on the substrate, the stacked structure comprising an active layer and a sacrificial layer stacked alternately in sequence.
[0126] In this embodiment, as Figure 8 , Figure 9 As shown, the stacked structure 120 can be formed on the substrate 110 using the following implementation: The substrate 110 is used as a seed crystal and placed in a reaction chamber. Gas sources for forming the sacrificial layer 121 and active layer 122 are alternately introduced into the reaction chamber. A chemical vapor deposition (CVD) process is used to alternately epitaxially grow the sacrificial layer 121 and active layer 122 on the substrate 110. The sacrificial layer 121 and active layer 122 together form the stacked structure 120. The sacrificial layer 121 and active layer 122 of the stacked structure 120 can be alternately stacked in layers of 2 to 1024 or more layers, for example, 48, 64, 128, 256, or 512 layers can be alternately stacked. In this embodiment, the top layer of the stacked structure 120 is the sacrificial layer 121.
[0127] In other embodiments, any one of chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), or sputtering is used to sequentially deposit a sacrificial layer 121 and an active layer 122 on the substrate 110.
[0128] In this embodiment, the substrate 110 can be a semiconductor substrate, which may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI (Silicon-on-insulator) substrate, or a GOI (Germanium-on-insulator) substrate, etc. The semiconductor substrate may be doped with ions; for example, it can be a P-type doped substrate or an N-type doped substrate.
[0129] The material of the sacrificial layer 121 may include germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.
[0130] The active layer 122 may be made of silicon, for example, one or more of monocrystalline silicon, polycrystalline silicon or amorphous silicon, and the active layer 122 may be doped with N-type conductive dopant ions or P-type conductive dopant ions.
[0131] In this embodiment, the substrate 110 is a silicon substrate, the sacrificial layer 121 is made of silicon germanide, and the active layer 122 is made of polycrystalline silicon.
[0132] It should be noted that, in Figure 8 In the diagram, line aa runs through the first region 101 and the array region 102, line bb runs through the first region 101 and the array region 102, line cc is located in the capacitor region 1011, and line dd is located in the array region 102. It is understood that the cross-sectional views along line aa and along line bb in this embodiment are not complete cross-sectional views of the semiconductor structure along line aa or line bb, but rather partial cross-sectional views of the semiconductor structure along line aa or line bb.
[0133] Step S112: Multiple first trenches are formed in the stacked structure. Each first trench extends along a first direction and penetrates the stacked structure in a direction perpendicular to the substrate. The retained active layer is divided into multiple active strips by the first trenches.
[0134] like Figure 10 , Figure 11 As shown, refer to Figure 8 , Figure 9 The process involves sequentially etching away portions of the sacrificial layer 121 and the active layer 122 until a portion of the top surface of the substrate 110 is exposed, at which point etching stops, forming multiple first trenches 140 in the stacked structure 120. Each first trench 140 extends along a first direction D1, and the retained active layer 122 is divided into multiple active strips 130 by the first trenches 140. On a plane parallel to the substrate 110, the active strips 130 and the first trenches 140 in the capacitor region 1011 are spaced apart, with adjacent active strips 130 separated by the first trenches 140.
[0135] In this embodiment, as Figure 10 , Figure 11 As shown, in the first direction D1, the stacked structures 120 located at both ends of the first trench 140 are not etched. The stacked structures 120 at both ends of the first trench 140 are retained as the support framework of the semiconductor structure so that the formed semiconductor structure is stable and has good stability.
[0136] Step S113: Form a dielectric layer, the dielectric layer at least filling the first trench located in the first region.
[0137] like Figures 32-35 As shown, refer to Figure 10 , Figure 11The dielectric layer 123 fills the first trench 140 located in the first region 101 to facilitate subsequent processing of the first region 101. The material of the dielectric layer 123 may include one of silicon nitride, silicon oxide, or silicon oxynitride.
[0138] Step S114: A support structure is formed in the first region. The support structure extends along the second direction and penetrates the first structure. The second direction is located in a plane parallel to the substrate and is perpendicular to the first direction. The support structure divides the first region into two independently set capacitor regions.
[0139] In this embodiment, a support structure 200 is formed in the first region 101, including: such as Figures 36-38 As shown, refer to Figures 32-35 The first region 101 is etched to remove part of the dielectric layer 123, part of the sacrificial layer 121, and part of the active strip 130, forming a channel trench 210 in the first region 101. The channel trench 210 extends along the second direction D2 and penetrates the first structure 100, exposing part of the substrate 110. The channel trench 210 divides the first region 101 into two independently configured capacitor regions 1011. Then, as... Figures 39-41 As shown, refer to Figures 36-38 The trench 210 is filled with deposited insulating material to form a support structure 200. The support structure 200 is used to connect two stacked capacitors 300 subsequently formed in the same first region 101. The support structure 200 provides good support for the stacked capacitors 300 so that the stacked capacitors 300 structure is stable and the stacked capacitors 300 can have a higher number of stacked layers.
[0140] In this embodiment, as Figures 36-38 As shown, by controlling the etching ratio of the active strip 130 and the sacrificial layer 121, the etching rate of the sacrificial layer 121 and the etching rate of the dielectric layer 123 are equal when etching the first region 101, and the etching rate of the sacrificial layer 121 is greater than the etching rate of the active strip 130. This forms multiple recesses 211 on the wall of the trench 210, each recess 211 being laterally recessed between two adjacent active strips 130. Figures 39-41 As shown, during the deposition of insulating material, some insulating material is filled into the recessed portion 211, forming multiple protrusions 220 on the sidewall of the support structure 200, so that the support structure 200 can provide better support for the subsequently formed stacked capacitor 300, ensuring the stability of the semiconductor structure and avoiding the risk of the semiconductor structure tilting or breaking.
[0141] Step S115: Remove part of the sacrificial layer to form a second trench in the capacitor region. The first trench and the second trench are connected to expose the sidewall of the active strip located in the capacitor region.
[0142] In this embodiment, as Figures 42-45 As shown, refer to Figures 39-41 as well as Figure 35 The active strip 130 in the capacitor region 1011 can be removed by dry or wet etching. By controlling the conditions, the etching process can achieve a high etching selectivity for the material of the active strip 130. All the sacrificial layer 121 and dielectric layer 123 in the capacitor region 1011 are removed. A second trench 150 is formed at the location where the sacrificial layer 121 is removed in the capacitor region 1011. The second trench 150 is connected to the first trench 140. On a plane perpendicular to the substrate 110, the active strip 130 and the second trench 150 in the capacitor region 1011 are alternately arranged, with adjacent active strips 130 separated by the second trench 150.
[0143] Step S120: A dielectric layer is formed in the capacitor region, and the dielectric layer covers the sidewalls of the exposed active strip.
[0144] In this embodiment, as Figures 46-49 As shown, refer to Figures 42-45 A dielectric material can be deposited using atomic layer deposition (ALD) to cover the sidewalls of the active strip 130 located in the capacitor region 1011, forming a dielectric layer 320. The material of the dielectric layer 320 may include at least one of strontium titanate (SrTiO3), alumina (Al2O3), zirconium oxide (ZrO), or hafnium oxide (HfO2).
[0145] Step S130: An upper electrode is formed in the capacitor region, the upper electrode covers the dielectric layer and fills the first trench and the second trench located in the capacitor region.
[0146] like Figures 50-53 As shown, refer to Figures 46-49 The upper electrode material is deposited by any one of chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition, or sputtering. The upper electrode material covers the dielectric layer 320 and fills the first trench 140 and the second trench 150 in the capacitor region 1011 to form the upper electrode 330. The portion of each active strip 130 located in the capacitor region 1011 serves as the lower electrode 310. The upper electrode 330, the dielectric layer 320, and the lower electrode 310 together form a stacked capacitor 300 vertically stacked on the substrate 110.
[0147] like Figures 50-53As shown, the stacked capacitor formed by the fabrication method of this embodiment has its upper electrode filling the first and second trenches located in the capacitor region, which increases the proportion of the upper electrode in the stacked capacitor, increases the storage space of the stacked capacitor, and reduces the process challenges and yield problems of semiconductor structure miniaturization.
[0148] This embodiment is a further description of a possible implementation of the above embodiment. Compared with the above embodiment, this embodiment adds the following step: implanting dopant ions into the active strip located in the capacitor region by ion implantation. This step is performed after the first structure is provided in step S110, and before the dielectric layer is formed in the capacitor region in step S120.
[0149] In this embodiment, doped ions are injected into the active strip 130 located in the capacitor region 1011 to increase the concentration of doped ions in the material of the active strip 130 located in the capacitor region 1011 and adjust the resistance of the active strip 130 located in the capacitor region 1011 so that the formed stacked capacitor 300 has better electrical performance.
[0150] According to an exemplary embodiment, this embodiment is a further description of a possible implementation of step S110 of the above embodiment.
[0151] During implementation, a first structure is provided, which also includes a process for fabricating an array region 102. The process for fabricating the array region 102 is performed after step S112, in which multiple first trenches are formed in the stacked structure, and before step S114, in which a support structure is formed in the first region. The process for fabricating the array region includes the following steps:
[0152] Step S101: Multiple word lines are formed in the array area. Each word line is vertically arranged on the substrate. On a plane parallel to the substrate, any two adjacent word lines are spaced apart. Each word line intersects with some of the active bars in the multiple active bars, and each word line covers part of the sidewall of the active bars.
[0153] In this embodiment, multiple word lines 400 are formed in the array region 102, which can be achieved in the following manner:
[0154] First, such as Figure 12 , Figure 13 As shown, refer to Figure 9 , Figure 10 The sacrificial layer 121 located in the array region 102 is removed, and a third trench 160 is formed at the location where the sacrificial layer 121 is removed in the array region 102. The third trench 160 is connected to the first trench 140, exposing the sidewall of the active strip 130 located in the array region 102.
[0155] Then, as Figure 14 , Figure 15As shown, refer to Figure 12 , Figure 13 An initial gate oxide layer 401 is deposited using any one of atomic layer deposition, chemical vapor deposition, or physical vapor deposition processes. The initial gate oxide layer 401 covers the sidewalls of the active strips 130 located in the array region 102. The material of the initial gate oxide layer 401 may include at least one of silicon oxide or silicon oxynitride.
[0156] like Figure 16 , Figure 17 As shown, refer to Figure 14 , Figure 15 An initial high-k dielectric layer 402 is deposited using any of the above-described deposition processes, and the initial high-k dielectric layer 402 covers the initial gate oxide layer 401. The material of the initial high-k dielectric layer 402 may include metal silicates or metal oxides. For example, the material of the initial high-k dielectric layer 402 may include at least one of tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO2), or hafnium oxide (HfO2).
[0157] Next, an initial word line layer (not shown in the figure) is deposited using any of the above-described deposition processes. The initial word line layer covers the initial high-k dielectric layer 402 and fills the first trench 140 and the third trench 160. The material of the initial word line layer may include a conductive metal, a doped semiconductor material, or a metal-semiconductor compound material. For example, the material of the initial word line layer may include one of titanium, tantalum, tungsten, or an alloy thereof, or the material of the initial word line layer may include one of doped monocrystalline silicon or polycrystalline silicon.
[0158] Then, as Figure 18 , Figure 19 As shown, refer to Figure 16 , Figure 17 The initial word line layer, initial high-k dielectric layer 402, and initial gate oxide layer 401 are etched away to form multiple independently configured word lines 400. Each word line 400 is vertically disposed on the substrate 110. On a plane parallel to the substrate 110, any two adjacent word lines 400 are spaced apart. Each word line 400 intersects with a portion of the multiple active strips 130, and each word line 400 covers a portion of the sidewalls of the active strips 130. Each word line 400 includes a gate oxide layer 410, a high-k dielectric layer 420, and a word line layer 430 that sequentially cover the active strip.
[0159] In this embodiment, multiple word lines 400 are arranged in two rows along the second direction D2, and each active bar 130 intersects with two word lines 400.
[0160] Step S102: Form the source layer and drain layer.
[0161] In this embodiment, the source layer 440 and the drain layer 450 can be formed in the following manner:
[0162] like Figure 20 , Figure 21 As shown, refer to Figure 18 , Figure 19 The active strips 130 in the array region 102 can be etched based on the first trench 140 and the third trench 160. After etching, the thickness of the active strips 130 exposed by the first trench 140 and the third trench 160 in the array region 102 is thinner than the thickness of the active strips 130 covered by the word line 400.
[0163] Then, as Figure 22 , Figure 23 As shown, refer to Figure 20 , Figure 21 The active strips 130 exposed in the array region 102 serve as seed crystals, and source layers 440 and drain layers 450 are formed on the active strips 130 on both sides of the word line 400 through epitaxial growth. The source layers 440 and drain layers 450 can cover part of the sidewalls of the gate oxide layer 410, but the source layers 440, drain layers 450, high-k dielectric layer 420, and word line layer 430 do not contact each other to avoid short circuits between adjacent word lines 400.
[0164] like Figure 22 , Figure 23 As shown, in this example, two word lines 400 connected to the same active strip 130 share a source layer 440. In other examples, two word lines 400 connected to the same active strip 130 may share a drain layer 450.
[0165] In other embodiments, source and drain regions can be formed in the active strips 130 on both sides of each word line 400 by ion implantation.
[0166] Step S103: Form the first isolation layer.
[0167] like Figure 24 , Figure 25 As shown, refer to Figure 22 , Figure 23A low-k dielectric material can be deposited using chemical vapor deposition or physical vapor deposition. The low-k dielectric material fills at least the unfilled areas in the first trench 140 and the third trench 160 located in the array region 102, forming a first isolation layer 610. The material of the first isolation layer 610 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the low-k dielectric material may also fill the first trench 140 located in the first region 101, forming a dielectric layer 123 in the first region 101.
[0168] Step S104: Multiple bit lines are formed in the array region. Each bit line extends along a second direction. The second direction is located in a plane parallel to the substrate and is perpendicular to the first direction. On the plane perpendicular to the substrate, any two adjacent bit lines are spaced apart. Each bit line intersects with a portion of the active strips in the multiple active strips, and each bit line covers a portion of the sidewall of a portion of the active strips.
[0169] In this embodiment, multiple bit lines 500 are formed in the array region 102, which can be achieved in the following manner:
[0170] First, such as Figure 26 , Figure 27 As shown, refer to Figure 24 , Figure 25 The array region 102 is etched to remove part of the first isolation layer 610, part of the source layer 440 and part of the active strip 130, forming a bit line trench 510. The bit line trench 510 extends along the second direction D2 and exposes part of the top surface of the substrate 110.
[0171] Then, as Figures 28-30 As shown, refer to Figure 26 , Figure 27 A second isolation layer 620 and a bit line 500 are alternately formed in the bit line trench 510. The second isolation layer 620 and the bit line 500 are arranged alternately on a plane perpendicular to the top surface of the substrate 110. Each bit line 500 extends along the second direction D2 and covers the sidewalls of the active strip 130 located on both sides of it.
[0172] like Figures 28-30 As shown, the first isolation layer 610 and the second isolation layer 620 in the array region 102 together form an isolation structure 600. The isolation structure 600 fills the gaps between word lines 400, the gaps between bit lines 500, and the gaps between multiple word lines 400 and multiple bit lines 500, so as to prevent short circuits in the devices in the array region 102 from causing leakage current in the semiconductor structure and to ensure that the semiconductor structure has good electrical performance.
[0173] The semiconductor structure formed in this embodiment creates word lines that are vertically disposed on the substrate. The word lines surround a portion of the sidewalls of the active strip to form a GAA (Gate All Around) structure, which reduces the process challenges and yield issues brought about by size reduction.
[0174] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.
[0175] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.
[0176] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.
[0177] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.
[0178] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
[0179] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.
[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A semiconductor structure, characterized by, The semiconductor structure includes a substrate and at least one memory cell disposed on the substrate, each memory cell comprising: Multiple active strips are arranged in an array above the substrate. Each active strip extends along a first direction. On a plane parallel to the substrate, any two adjacent active strips are separated by a first trench. On a plane perpendicular to the substrate, any two adjacent active strips are separated by a second trench. At least one set of stacked capacitors, with two adjacent sets of stacked capacitors spaced apart, each set of stacked capacitors including a lower electrode, a dielectric layer covering the sidewall of the lower electrode, and an upper electrode, the lower electrode including a partial structure through each of the active strips of the stacked capacitor, the upper electrode covering the dielectric layer and filling the first trench and the second trench located between the lower electrodes; The semiconductor structure includes a plurality of memory cells, which are arranged cyclically on the substrate along the first direction. The semiconductor structure also includes: A support structure is disposed on the substrate and between adjacent memory cells, and the support structure connects two stacked capacitors of adjacent memory cells. The stacked capacitors also include: Multiple recesses are provided at one end of the stacked capacitor near the support structure, each recess is provided between two adjacent active bars, and each recess is oriented toward the support structure.
2. The semiconductor structure of claim 1, wherein, The material of the supporting structure includes insulating material.
3. The semiconductor structure of claim 1, wherein, The support structure also includes: The protrusions are disposed on the sidewall of the support structure, and each protrusion is disposed corresponding to a recess, with each protrusion embedded in the recess.
4. The semiconductor structure of claim 1, wherein, Each of the memory units further includes: An array region is disposed between two adjacent sets of stacked capacitors, and the array region is connected to the stacked capacitors through a plurality of active strips.
5. The semiconductor structure of claim 4, wherein, The array region includes: Multiple word lines are arranged vertically on the substrate. Any two adjacent word lines are spaced apart on a plane parallel to the substrate. Each word line intersects with a portion of the active bars among the multiple active bars, and each word line covers a portion of the sidewall of a portion of the active bars. Multiple bit lines, each bit line extending along a second direction, the second direction being located in a plane parallel to the substrate and perpendicular to the first direction, any two adjacent bit lines are spaced apart on the plane perpendicular to the substrate, each bit line intersects with a portion of the active strips of the plurality of active strips, and each bit line covers a portion of the sidewall of a portion of the active strips; The multiple word lines and the multiple bit lines are separated by an isolation structure.
6. The semiconductor structure of claim 4, wherein, In the first direction, each memory cell includes two sets of stacked capacitors symmetrically arranged on both sides of the array region.
7. A method of fabricating a semiconductor structure, the method comprising: The method for fabricating the semiconductor structure includes: A first structure is provided, the first structure including a capacitor region, the first structure including a substrate and a plurality of active strips, the plurality of active strips being arranged in an array above the substrate, each active strip extending along a first direction, in the capacitor region, on a plane parallel to the substrate, any two adjacent active strips are separated by a first trench, and on a plane perpendicular to the substrate, any two adjacent active strips are separated by a second trench, the second trench communicating with the first trench and exposing the sidewalls of the active strips located in the capacitor region; A dielectric layer is formed in the capacitor region, and the dielectric layer covers the exposed sidewall of the active strip; An upper electrode is formed in the capacitor region, the upper electrode covering the dielectric layer and filling the first trench and the second trench located in the capacitor region; Using the portion of the active strip located in the capacitor region as the lower electrode, the upper electrode, the dielectric layer, and the lower electrode form a stacked capacitor vertically stacked on the substrate; A first structure is provided, comprising: providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising an active layer and a sacrificial layer stacked alternately in sequence; Multiple first trenches are formed in the stacked structure, each first trench extends along the first direction, and in a direction perpendicular to the substrate, each first trench penetrates the stacked structure, and the retained active layer is divided into multiple active strips by the first trenches. The first structure further includes a first region, the first region is etched to form a trench in the first region, the trench extends along a second direction and penetrates the first structure, and the trench exposes a portion of the substrate, and an insulating material is deposited to fill the trench to form a support structure; When etching the first region, the etching rate of the sacrificial layer is greater than the etching rate of the active strip, and multiple recesses are formed on the trench wall of the channel, with each recess recessed laterally between two adjacent active strips. A portion of the insulating material is filled into the recess, forming multiple protrusions on the sidewall of the support structure.
8. The method of fabricating a semiconductor structure of claim 7, wherein, include: A portion of the sacrificial layer is removed to form a second trench in the capacitor region. The first trench and the second trench are connected, exposing the sidewall of the active strip located in the capacitor region.
9. The method of fabricating a semiconductor structure of claim 8, wherein, The capacitor region is located in the first region, and the manufacturing method further includes: The support structure extends along a second direction and penetrates the first structure. The second direction is located in a plane parallel to the substrate and is perpendicular to the first direction. The support structure divides the first region into two independently configured capacitor regions.
10. The method of fabricating a semiconductor structure of claim 8, wherein, The first structure further includes an array region, and providing the first structure further includes: Remove the sacrificial layer located in the array region; Multiple word lines are formed in the array area. Each word line is vertically disposed on the substrate. Any two adjacent word lines are spaced apart on a plane parallel to the substrate. Each word line intersects with a portion of the active bars among the multiple active bars, and each word line covers a portion of the sidewall of a portion of the active bars. Multiple bit lines are formed in the array region. Each bit line extends along a second direction, which is located in a plane parallel to the substrate and is perpendicular to the first direction. Any two adjacent bit lines are spaced apart on the plane perpendicular to the substrate. Each bit line intersects with a portion of the active strips in the plurality of active strips, and each bit line covers a portion of the sidewall of a portion of the active strip.
11. The method of fabricating a semiconductor structure of claim 10, wherein, The provision of the first structure further includes: An isolation structure is formed in the array region, and the isolation structure fills the gaps between the multiple word lines and the multiple bit lines.